pcie_pci.c revision 14a66e5a5df38a62990b14d0672ff8f6f55caa09
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PCI-E to PCI bus bridge nexus driver
*/
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/pcie_impl.h>
#ifdef DEBUG
int pepb_debug = 0;
#else
#define PEPB_DEBUG(args)
#endif
/*
*/
void *);
struct bus_ops pepb_bus_ops = {
0,
0,
0,
0, /* (*bus_get_eventcookie)(); */
0, /* (*bus_add_eventcall)(); */
0, /* (*bus_remove_eventcall)(); */
0, /* (*bus_post_event)(); */
0, /* (*bus_intr_ctl)(); */
0, /* (*bus_config)(); */
0, /* (*bus_unconfig)(); */
pepb_fm_init, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
NULL, /* (*bus_fm_access_enter)(); */
NULL, /* (*bus_fm_access_exit)(); */
NULL, /* (*bus_power)(); */
i_ddi_intr_ops /* (*bus_intr_op)(); */
};
/*
* The goal here is to leverage off of the pcihp.c source without making
* changes to it. Call into it's cb_ops directly if needed.
*/
caddr_t, int *);
struct cb_ops pepb_cb_ops = {
pepb_open, /* open */
pepb_close, /* close */
nodev, /* strategy */
nodev, /* print */
nodev, /* dump */
nodev, /* read */
nodev, /* write */
pepb_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
pepb_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
static int pepb_probe(dev_info_t *);
DEVO_REV, /* devo_rev */
0, /* refcnt */
pepb_info, /* info */
nulldev, /* identify */
pepb_probe, /* probe */
pepb_attach, /* attach */
pepb_detach, /* detach */
nulldev, /* reset */
&pepb_cb_ops, /* driver operations */
&pepb_bus_ops /* bus operations */
};
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
"PCIe to PCI nexus driver 1.10",
&pepb_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
/*
* soft state pointer and structure template:
*/
static void *pepb_state;
typedef struct {
int port_type;
int inband_hpc;
/*
* cpr support:
*/
struct {
/*
* interrupt support
*/
int pepb_fmcap;
/* undefined port_type; cannot be 0 or a valid PCIE device type value */
#define PEPB_PORT_TYPE_NULL -1
/* panic on unknown flag, defaulted to on */
int pepb_panic_unknown = 1;
int pepb_panic_fatal = 1;
extern errorq_t *pci_target_queue;
/*
* forward function declarations:
*/
static void pepb_uninitchild(dev_info_t *);
int
_init(void)
{
int e;
return (e);
}
int
_fini(void)
{
int e;
if ((e = mod_remove(&modlinkage)) == 0) {
/*
* Destroy pci_target_queue, and set it to NULL.
*/
if (pci_target_queue)
}
return (e);
}
int
{
}
/*ARGSUSED*/
static int
{
return (DDI_PROBE_SUCCESS);
}
static int
{
int instance;
const char *drvnm;
int rv;
char *device_type;
switch (cmd) {
case DDI_RESUME:
/*
* Get the soft state structure for the bridge.
*/
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
case DDI_ATTACH:
break;
}
return (DDI_FAILURE);
}
/*
* If the link is disabled then there is no need to attach
*/
return (DDI_FAILURE);
}
/*
* Allocate and get soft state structure.
*/
return (DDI_FAILURE);
}
/*
* initialize fma support
*/
(void *)pepb->pepb_fm_ibc);
(void *)pepb->pepb_fm_ibc);
/*
* Property setup
* - pci-hotplug-type: type of hotplug potentially supported derived
* from bridge config regs
*/
device_type = "pciex";
else
device_type = "pci";
"device_type", device_type);
/*
* Initialize interrupt handlers.
* Failure means no PCIE advanced error reporting and partial native
* hotplug functionality
*/
/*
* Initialize hotplug support on this bus. At minimum
* (for non hotplug bus) this would create ":devctl" minor
* node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
* to this bus.
*/
else {
/*
* grab istate lock if interrupts are enabled to update
* inband_hpc after HP framework initializes
*/
/*
* If there is an inband PCI-E HPC then initialize it.
* The failure is not considered fatal for the system
* so log the message and ignore the failure.
*
* Also optimize intr handling where if we are not using
* native hotplug mode, we do not ask the hotplug
* framework to check interrupt status. Note that in
* this case, istate.inband_hpc will differ from
* pepb->inband_hpc.
*/
if (hp_mode != PCIEHPC_NATIVE_HP_MODE) {
"hotplug mode; disabling hp intr checking",
}
}
}
return (DDI_SUCCESS);
}
static int
{
switch (cmd) {
case DDI_SUSPEND:
return (DDI_SUCCESS);
case DDI_DETACH:
break;
default:
return (DDI_FAILURE);
}
/* remove interrupt handlers */
/* uninitialize inband PCI-E HPC if present */
(void) pciehpc_uninit(devi);
/*
* Uninitialize hotplug support on this bus.
*/
(void) pcihp_uninit(devi);
/*
* And finally free the per-pci soft state.
*/
return (DDI_SUCCESS);
}
static int
{
}
static int
{
int reglen;
int rn;
int totreg;
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
break;
case DDI_CTLOPS_PEEK:
case DDI_CTLOPS_POKE:
&pepb->pepb_peek_poke_mutex));
default:
}
*(int *)result = 0;
®len) != DDI_SUCCESS)
return (DDI_FAILURE);
if (ctlop == DDI_CTLOPS_NREGS)
else if (ctlop == DDI_CTLOPS_REGSIZE) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
static int
{
char **unit_addr;
uint_t n;
/*
* For .conf nodes, use unit-address property as name
*/
if (ndi_dev_is_persistent_node(child) == 0) {
"cannot find unit-address in %s.conf",
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
return (DDI_SUCCESS);
}
/* get child "reg" property */
return (DDI_FAILURE);
}
/* copy the device identifications */
if (func != 0)
else
return (DDI_SUCCESS);
}
static int
{
struct ddi_parent_private_data *pdptr;
char name[MAXNAMELEN];
return (DDI_FAILURE);
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
/*
* Merged ok - return failure to remove the node.
*/
return (DDI_FAILURE);
}
/* workaround for ddivs to run under PCI-E */
return (DDI_SUCCESS);
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
return (DDI_NOT_WELL_FORMED);
}
-1) != -1) {
} else
}
return (DDI_SUCCESS);
}
static void
{
struct ddi_parent_private_data *pdptr;
/*
* Do it way early.
* Otherwise ddi_map() call form pcie_error_fini crashes
*/
}
}
/*
* Strip the node to properly convert it back to prototype form
*/
}
/*
* pepb_save_config_regs
*
* This routine saves the state of the configuration registers of all
* the child nodes of each PBM.
*
* used by: pepb_detach() on suspends
*
* return value: none
*
* XXX: Need to save PCI-E config registers including MSI
*/
static void
{
int i;
}
pepb_p->config_state_index = i;
}
/*
* pepb_restore_config_regs
*
* This routine restores the state of the configuration registers of all
* the child nodes of each PBM.
*
* used by: pepb_attach() on resume
*
* return value: none
*
* XXX: Need to restore PCI-E config registers including MSI
*/
static void
{
int i;
for (i = 0; i < pepb_p->config_state_index; i++) {
}
}
/*
* sets pepb_p->port_type to a PCIE defined device type
* and returns DDI_SUCCESS if the downstream/secondary side is a PCIE bus
*/
static int
{
int pcie_loc;
DDI_PROP_DONTPASS, "pcie-capid-pointer", 0);
if (pcie_loc == 0)
return (DDI_FAILURE);
case PCIE_PCIECAP_DEV_TYPE_UP:
return (DDI_SUCCESS);
default:
break;
}
return (DDI_FAILURE);
}
/*
* <arg1> contains the softstate while <arg2> contains the inum
* responsible for the invocation
*/
static uint_t
{
int ret = DDI_INTR_UNCLAIMED;
#ifdef DEBUG
#endif
return (DDI_INTR_UNCLAIMED);
return (DDI_INTR_UNCLAIMED);
/*
* We must check all interrupt sources associated with this vector.
* We cannot expect to be interrupted again for each unacknowleged
* source.
*/
if (isrc == PCIE_BRIDGE_INTR_SRC_UNKNOWN)
goto OUT;
/*
* if HPC is initialized then call the hotplug interrupt handler
*/
if ((isrc & PCIE_BRIDGE_INTR_SRC_HP) &&
}
}
/*
* PME: just check and clear status
*/
if (isrc & PCIE_BRIDGE_INTR_SRC_PME &&
if (sts & PCIE_ROOTSTS_PME_STATUS) {
}
}
/*
* AER
*/
if (isrc & PCIE_BRIDGE_INTR_SRC_AER) {
}
fm_panic("%s-%d: PCI(-X) Express Fatal Error",
}
OUT:
#ifdef DEBUG
if (ret != DDI_INTR_CLAIMED)
#endif
return (ret);
}
/*ARGSUSED*/
static int
{
return (pepb->pepb_fmcap);
}
/*ARGSUSED*/
static int
{
return (derr->fme_status);
}
static int
{
}
static int
{
}
static int
int *rvalp)
{
rvalp));
}
static int
{
}
static int
{
}