pcie_nvidia.h revision ae115bc77f6fcde83175c75b4206dc2e50747966
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _PCIEX_PCI_NVIDIA_H
#define _PCIEX_PCI_NVIDIA_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* PCI Configuration (Nvidia, PCIe) related library functions
*/
uchar_t);
/* Generic Nvidia chipset IDs and defines */
/* CK8-04 PCIe RC and LPC-PCI Bridge device IDs */
#define NVIDIA_CK804_LPC2PCI_DEVICE_ID(did) \
(((did) == NVIDIA_CK804_DEFAULT_ISA_BRIDGE_DEVID) || \
((did) == NVIDIA_CK804_PRO_ISA_BRIDGE_DEVID) || \
/*
* Only for Nvidia's CrushK 8-04 chipsets:
* To enable hotplug; we need to map in two I/O BARs
* from ISA bridge's config space
*/
/* NV_XVR_VEND_CYA1 related defines */
/*
* C51 related defines
*/
/* C51 PCIe Root Complex Device ID defines */
#define NVIDIA_C51_DEVICE_ID_XVR16 0x2fb
#define NVIDIA_C51_DEVICE_ID_XVR1_0 0x2fc
#define NVIDIA_C51_DEVICE_ID_XVR1_1 0x2fd
#define NVIDIA_C51_DEVICE_ID(did) \
(((did) == NVIDIA_C51_DEVICE_ID_XVR16) || \
((did) == NVIDIA_C51_DEVICE_ID_XVR1_0) || \
((did) == NVIDIA_C51_DEVICE_ID_XVR1_1))
/*
* MCP55 related defines
*/
/* MCP55 PCIe Root Complex Device ID defines */
#define NVIDIA_MCP55_DEVICE_ID_XVR4 0x374
#define NVIDIA_MCP55_DEVICE_ID_XVR8 0x375
#define NVIDIA_MCP55_DEVICE_ID_XVR8_VC1 0x376
#define NVIDIA_MCP55_DEVICE_ID_XVR16 0x377
#define NVIDIA_MCP55_DEVICE_ID_XVR4_VC1 0x378
#define NVIDIA_MCP55_DEVICE_ID(did) \
(((did) == NVIDIA_MCP55_DEVICE_ID_XVR4) || \
((did) == NVIDIA_MCP55_DEVICE_ID_XVR8) || \
((did) == NVIDIA_MCP55_DEVICE_ID_XVR16) || \
((did) == NVIDIA_MCP55_DEVICE_ID_XVR4_VC1) || \
((did) == NVIDIA_MCP55_DEVICE_ID_XVR8_VC1))
/* MCP55 LPC-PCI Bridge Device ID defines */
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0 0x360
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1 0x361
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2 0x362
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3 0x363
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4 0x364
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5 0x365
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6 0x366
#define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP7 0x367
#define NVIDIA_MCP55_LPC2PCI_DEVICE_ID(did) \
(((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0) || \
((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1) || \
((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2) || \
((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3) || \
((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4) || \
((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5) || \
((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6) || \
/*
* MCP61 related defines
*/
/* MCP61 PCIe Root Complex Device ID defines */
#define NVIDIA_MCP61_DEVICE_ID_XVR4 0x3e8
#define NVIDIA_MCP61_DEVICE_ID_XVR8 0x3e9
#define NVIDIA_MCP61_DEVICE_ID(did) \
(((did) == NVIDIA_MCP61_DEVICE_ID_XVR4) || \
((did) == NVIDIA_MCP61_DEVICE_ID_XVR8))
/*
* MCP65 related defines
*/
/* MCP65 PCIe Root Complex Device ID defines */
#define NVIDIA_MCP65_DEVICE_ID_XVR4 0x458
#define NVIDIA_MCP65_DEVICE_ID_XVR8 0x459
#define NVIDIA_MCP65_DEVICE_ID_XVR16 0x45a
#define NVIDIA_MCP65_DEVICE_ID(did) \
(((did) == NVIDIA_MCP65_DEVICE_ID_XVR4) || \
((did) == NVIDIA_MCP65_DEVICE_ID_XVR8) || \
((did) == NVIDIA_MCP65_DEVICE_ID_XVR16))
/*
* Check if the given device is a Nvidia's LPC bridge
*/
(((vid) == NVIDIA_VENDOR_ID) && \
/* Check for PCIe RC Device ID */
#define NVIDIA_PCIE_RC_DEV_ID(did) \
(((did) == NVIDIA_CK804_DEVICE_ID) || \
NVIDIA_C51_DEVICE_ID(did) || \
NVIDIA_MCP55_DEVICE_ID(did) || \
NVIDIA_MCP61_DEVICE_ID(did) || \
/*
* Defines to figure out what kind of hotplug is supported
*/
#ifdef __cplusplus
}
#endif
#endif /* _PCIEX_PCI_NVIDIA_H */