mcamd.h revision 074bb90d80fdbeb2d04a8450a55ecbc96de28785
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _MCAMD_H
#define _MCAMD_H
/*
* Header file for the mc-amd AMD memory-controller driver. This should be
* included from that driver source alone - any more-widely useful definitions
* belong in mc_amd.h.
*/
#include <sys/cpu_module.h>
#include <mcamd_api.h>
#include <mcamd_err.h>
#include <mcamd_dimmcfg.h>
#ifdef __cplusplus
extern "C" {
#endif
#error "MC_CHIP_DIMMPERCS exceeds MC_UNUM_NDIMM"
#endif
/*
* The memory controller configuration registers are accessed via PCI bus 0,
* device 0x18 + nodeid, functions 0 to 3. The function numbers are
* MC_FUNC_*, defined in mc_amd.h.
*
* We do not attach to function 3 "Miscellaneous Control" pci1022,1103
* since the agpgart driver already attaches to that function; instead we
* retrieve what function 3 parameters we require via direct PCI Mechanism 1
* accesses
*
* The memory controller driver attaches to these device nodes, but publishes
* a single minor node. We need to ensure that the minor node can be
* consistently mapped back to a single (and the same) device node, so we
* need to pick one to be used. We'll use the dram address map device node,
* as it'll be the last to be attached.
*/
#define MC_FUNC_DEVIMAP MC_FUNC_DRAMCTL
#define MC_FUNC_HTCONFIG_BINDNM "pci1022,1100"
#define MC_FUNC_ADDRMAP_BINDNM "pci1022,1101"
#define MC_FUNC_DRAMCTL_BINDNM "pci1022,1102"
typedef struct mc_func {
} mc_func_t;
/*
* Node types for mch_type below. These are used in array indexing.
*/
#define MC_NT_MC 0
#define MC_NT_CS 1
#define MC_NT_DIMM 2
#define MC_NT_NTYPES 3
typedef struct mc_hdr {
union {
} _mch_ptr;
} mc_hdr_t;
struct mc_dimm {
};
/*
* Chip-select properties. If a chip-select is associated with just one
* dimm (whether it be on the A or B dram channel) that number will be
* in csp_dimmnums[0]; if the chip-select is associated with two dimms
* then csp_dimmnums[0] has the dimm from channel A and csp_dimmnums[1] has
* the partner dimm from channel B.
*/
typedef struct mccs_props {
} mccs_props_t;
/*
* Chip-select config register values
*/
typedef struct mccs_cfgrefs {
struct mc_cs {
};
/*
* Memory controller properties.
*/
typedef struct mc_props {
} mc_props_t;
/*
* Memory controller config register values
*/
typedef struct mc_cfgregs {
} mc_cfgregs_t;
struct mc {
const char *mc_revname; /* revision name string */
char *mc_snapshot; /* packed nvlist for libmc */
int mc_csdiscontig; /* chip-selects discontiguous */
};
typedef struct mcamd_hdl {
int mcamd_errno;
int mcamd_debug;
} mcamd_hdl_t;
extern void mcamd_mkhdl(mcamd_hdl_t *);
/*
* mcamd_mc_ops prototypes
*/
uint64_t *);
/*
* Internal functions
*/
#ifdef __cplusplus
}
#endif
#endif /* _MCAMD_H */