intel_nhm.h revision e8ee2240af37f707c9910893e48444352a47a0c5
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _INTEL_NHM_H
#define _INTEL_NHM_H
#ifdef __cplusplus
extern "C" {
#endif
#define NHM_EP_CPU 0x2c408086
#define NHM_WS_CPU 0x2c418086
#define NHM_CPU_RAS 0x2c1a8086
#define NHM_JF_CPU 0x2c588086
#define NHM_JF_CPU_RAS 0x2cda8086
#define NHM_WM_CPU 0x2c708086
#define NHM_WM_CPU_RAS 0x2d9a8086
#define NHM_INTERCONNECT "Intel QuickPath"
#define MAX_CPU_NODES 2
#define CPU_PCI_DEVS 6
#define CPU_PCI_FUNCS 6
#define MAX_BUS_NUMBER max_bus_number
#define MC_CONTROL_RD(cpu) \
#define MC_STATUS_RD(cpu) \
#define MC_SMI_SPARE_DIMM_ERROR_STATUS_RD(cpu) \
#define MC_CPU_RAS_RD(cpu) \
#define MC_SCRUB_CONTROL_RD(cpu) \
0x4c, reg);
reg);
0x4c, 0)
0x60, 0)
#define MC_DIMM_CLK_RATIO_STATUS(cpu) \
/*
* MC_CONTROL
*/
/*
* MC_STATUS
*/
#define WS_ECC_ENABLED 0x10
/*
* MC_CHANNEL_DIMM_INIT_PARAMS
*/
/*
* MC_DOD_CH
*/
#define DIMMWIDTH 8
/*
* MC_SAG_CH
*/
#define CH_ADDRESS_OFFSET(reg) \
#define CH_ADDRESS_SOFFSET(reg) \
/* SAG offset covers SA[39:16] so granularity is 2^16 = 64KB */
#define SAG_OFFSET_GRANULARITY 16
/* 24-bit mask for TTMAD_CR_SAG_CH*.OFFSET */
#define SAG_OFFSET_SIZE_MASK 0xffffffULL
/* 16-bit mask for lower bits not covered by CREG value (SA[15:0]) */
#define SAG_OFFSET_ADDR_MASK 0xffffULL
/*
* MC_RIR_LIMIT_CH
*/
/*
* MC_RIR_WAY_CH
*/
>> 54)
#define RIR_OFFSET_SIZE_MASK 0x3ff
#define MAX_RIR_WAY 4
#define RIR_LIMIT_GRANULARITY 28
#define RIR_INTLV_SIZE_MASK 0x3ULL
/*
* MC_RAS_ENABLES
*/
/*
* MC_RAS_STATUS
*/
/*
* MC_SSRSTATUS
*/
/*
* MC_SSR_CONTROL
*/
#define SSR_IDLE 0
#define SSR_SCRUB 1
#define SSR_SPARE 2
/*
* MC_SCRUB_CONTROL
*/
/*
* MC_DIMM_CLK_RATIO_STATUS
*/
/*
* MC_SMI_SPARE_DIMM_ERROR_STATUS_RD
*/
#define MAX_MEMORY_CONTROLLERS MAX_CPU_NODES
#define CHANNELS_PER_MEMORY_CONTROLLER 3
#define MAX_DIMMS_PER_CHANNEL 3
/*
* SAD_DRAM_RULE
*/
/*
* from SAD_DRAM_RULE*.MODE
*/
#define DIRECT 0
#define XOR 1
#define MOD3 2
#define INTERLEAVE_NWAY 8
#define MAX_SAD_DRAM_RULE 8
#define SAD_LIMIT_GRANULARITY 26
#define SAD_LIMIT_ADDR_MASK 0x3ffffffULL
#define SAD_INTLV_DIRECT_BIT 6
#define SAD_INTLV_XOR_BIT 16
#define SAD_INTLV_SIZE_MASK 0x7ULL
#define SAD_INTLV_ADDR_MASK 0x3fULL
/*
* TAD_DRAM_RULE
*/
#define MAX_TAD_DRAM_RULE 8
#define VRANK_SZ 0x10000000
typedef struct sad {
char mode;
char enable;
char interleave;
} sad_t;
typedef struct tad {
char mode;
char enable;
char interleave;
} tad_t;
typedef struct sag_ch {
char divby3;
char remove6;
char remove7;
char remove8;
} sag_ch_t;
typedef struct rir_way {
} way_t;
typedef struct rir {
char interleave;
} rir_t;
typedef struct dod_type {
int NUMCol;
int NUMRow;
int NUMRank;
int NUMBank;
int DIMMPresent;
int RankOffset;
} dod_t;
/*
* MC_CHANNEL_MAPPER
*/
extern int max_bus_number;
#ifdef __cplusplus
}
#endif
#endif /* _INTEL_NHM_H */