nb5000.h revision 8573850824dba94c5cab43927f5abaccb11d8c3a
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _NB5000_H
#define _NB5000_H
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/cpu_module.h>
#define NB_5000_MAX_MEM_CONTROLLERS 2
#define NB_MAX_CHANNELS_PER_BRANCH 2
#define NB_5100_RANKS_PER_CHANNEL 6
#define NB_MEM_BRANCH_SELECT \
#define NB_MAX_MEM_BRANCH_SELECT 3
#define NB_MAX_MEM_RANK_SELECT 7
#define NB_RANKS_IN_SELECT 4
#define NB_PCI_DEV 10
#define NB_PCI_NFUNC 4
#define DOCMD_PEX_MASK 0x00
#define DOCMD_5400_PEX_MASK 0x000
#define DOCMD_PEX 0xf0
#define DOCMD_5400_PEX 0xff0
#define SPD_BUSY 0x1000
#define SPD_BUS_ERROR 0x2000
#define SPD_READ_DATA_VALID 0x8000
#define SPD_EEPROM_WRITE 0xa8000000
#define MC_MIRROR 0x10000
#define MC_PATROL_SCRUB 0x80
#define MC_DEMAND_SCRUB 0x40
#define MCA_SCHDIMM 0x4000
#define TLOW_MAX 0x100000000ULL
#define MTR_PRESENT(mtr) \
0x0400 : 0x0100))
#define MTR_ETHROTTLE(mtr) \
? 0x0200 : 0x0080))
0x0100 : 0x0040) ? 8 : 4)
#define MTR_NUMBANK(mtr) \
0x0040 : 0x0020) ? 8 : 4)
/* FERR_GLOBAL and NERR_GLOBAL */
/* FBD channel Fatal Error */
/* FBD channel Non-Fatal Error */
/* DDR channel0,1 Non-Fatal Error */
/* Timeout */
/* intelligent throttling disabled */
/* CRC read error */
/* non-redundant retry or FBD */
/* configuration write error on retry */
#define ERR_FAT_FBD_MASK 0x007fffff
/* Timeout */
/* redundant retry */
/* FBD sync status */
/* spare-copy data ECC */
/* data ECC */
/* demand data ECC */
/* CRC read error */
/* error on first attempt */
/* attempt */
/* patrol data ECC */
/* resilver or spare copy data ECC */
/* mirrored demand data ECC */
/* non-mirrored demand data ECC */
/* patrol data ECC */
/* resilver or spare copy data ECC */
/* mirrored demand data ECC */
/* non-mirrored demand data ECC */
/* replay */
#define ERR_NF_FBD_MASK 0x01ffffff
#define ERR_NF_FBD_MA (ERR_NF_FBD_M14)
/* Timeout */
/* redundant retry */
/* Timeout */
/* FBD sync status */
/* spare-copy data ECC */
/* data ECC */
/* demand data ECC */
/* CRC read error */
/* error on first attempt */
/* attempt */
/* patrol data ECC */
/* resilver or spare copy data ECC */
/* mirrored demand data ECC */
/* non-mirrored demand data ECC */
/* patrol data ECC */
/* resilver or spare copy data ECC */
/* mirrored demand data ECC */
/* non-mirrored demand data ECC */
/* replay */
/* intelligent throttling disabled */
/* CRC read error */
/* non-redundant retry or FBD */
/* configuration write error on retry */
/* MCH 7300 errata 34 (reserved mask bits) */
/* FERR_NF_MEM: MC First non-fatal errors */
#define ERR_NF_MEM_MASK 0x0003fffff
#define EMASK_MEM_M21 ERR_NF_MEM_M21
#define EMASK_MEM_M20 ERR_NF_MEM_M20
#define EMASK_MEM_M18 ERR_NF_MEM_M18
#define EMASK_MEM_M16 ERR_NF_MEM_M16
#define EMASK_MEM_M15 ERR_NF_MEM_M15
#define EMASK_MEM_M14 ERR_NF_MEM_M14
#define EMASK_MEM_M12 ERR_NF_MEM_M12
#define EMASK_MEM_M11 ERR_NF_MEM_M11
#define EMASK_MEM_M10 ERR_NF_MEM_M10
#define EMASK_MEM_M6 ERR_NF_MEM_M6
#define EMASK_MEM_M5 ERR_NF_MEM_M5
#define EMASK_MEM_M4 ERR_NF_MEM_M4
#define EMASK_MEM_M1 ERR_NF_MEM_M1
/* the ways during SF lookup */
/* non-coherent address space */
/* the ways during SF lookup */
/* MCH 5000 errata 2 */
#define EMASK_INT_5000 EMASK_INT_B1
/* MCH 7300 errata 17 & 20 */
/* MCH 7300 errata 17,20 & 21 */
#define EMASK_INT_5400 0
(nb_chipset == INTEL_NB_5100) ? 0 : \
(nb_chipset == INTEL_NB_5100) ? 0 : \
(GE_FERR_MEM0_NF|GE_FERR_MEM1_NF) : 0)
/* request */
/* Parity */
/* change (correctable) */
#define PEX_NF_IO8 0x00000080
#define PEX_NF_IO7 0x00000040
#define PEX_NF_IO3 0x00000004
#define PEX_NF_IO2 0x00000002
#define GE_FERR_FSB(ferr) ( \
(nb_chipset == INTEL_NB_7300) && \
(nb_chipset == INTEL_NB_7300) && \
-1)
#define GE_NERR_TO_FERR_FSB(nerr) \
#define GE_ERR_PEX(ferr) ( \
(nb_chipset == INTEL_NB_5400) && \
-1)
GE_PCIEX2_FATAL| GE_ESI_FATAL) : \
0x40, 0) : \
#define NRECFSB_WR(fsb) \
if (nb_chipset == INTEL_NB_7300) { \
0); \
} else { \
}
if (nb_chipset == INTEL_NB_7300) { \
0); \
} else { \
}
#define NRECADDR_WR(fsb) \
if (nb_chipset == INTEL_NB_7300) { \
0); \
0); \
} else { \
}
#define FERR_GLOBAL_WR(val) \
if (nb_chipset == INTEL_NB_7300) \
{ \
} else { \
}
{ \
if (nb_chipset == INTEL_NB_7300) \
else \
}
{ \
if (nb_chipset == INTEL_NB_7300) \
else \
}
{ \
if (nb_chipset == INTEL_NB_7300) \
else \
}
{ \
if (nb_chipset == INTEL_NB_7300) \
else \
}
{ \
if (nb_chipset == INTEL_NB_7300) \
else \
}
nb_chipset == INTEL_NB_7300) { \
}
nb_chipset == INTEL_NB_7300) { \
}
val & 0xff); \
} else { \
}
val & 0xff); \
} else { \
}
val & 0xff); \
} else { \
}
val & 0xff); \
} else { \
}
EMASK_5400_INT_WR(val); \
} else { \
EMASK_5000_INT_WR(val); \
}
} else { \
}
} else { \
}
} else { \
}
} else { \
}
#define NRECFGLOG_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define NRECFBDA_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define NRECFBDB_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define NRECFBDC_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define NRECFBDD_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define NRECFBDE_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define NRECFBDF_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
#define REDMEMB_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else \
#define RECMEMA_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else \
0xe2, 0)
#define RECMEMB_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else \
#define RECFGLOG_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define RECFBDA_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define RECFBDB_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define RECFBDC_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define RECFBDD_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define RECFBDE_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
else \
#define RECFBDF_WR(branch) \
if (nb_chipset == INTEL_NB_5400) \
else if (nb_chipset == INTEL_NB_7300) \
#define FERR_NF_MEM_WR(val) \
#define NERR_NF_MEM_WR(val) \
#define EMASK_MEM_WR(val) \
#define ERR0_MEM_WR(val) \
#define ERR1_MEM_WR(val) \
#define ERR2_MEM_WR(val) \
#define MCERR_MEM_WR(val) \
#define VALIDLOG_RD(branch) \
#define MEM_NRECMEMA_RD(branch) \
#define MEM_NRECMEMB_RD(branch) \
#define MEM_REDMEMA_RD(branch) \
#define MEM_REDMEMB_RD(branch) \
#define MEM_RECMEMA_RD(branch) \
#define MEM_RECMEMB_RD(branch) \
#define MEM_NRECMEMA_WR(branch) \
#define MEM_NRECMEMB_WR(branch) \
#define MEM_REDMEMA_WR(branch) \
#define MEM_REDMEMB_WR(branch) \
#define MEM_RECMEMA_WR(branch) \
#define MEM_RECMEMB_WR(branch) \
0))
nb_chipset == INTEL_NB_5400 ? \
((branch) == 0) ? \
nb_pci_getw(0, 21, 0, \
(nb_number_memory_controllers == 2) ? \
nb_pci_getw(0, 22, 0, \
nb_chipset == INTEL_NB_5100 ? \
(nb_number_memory_controllers == 2) ? \
nb_chipset == INTEL_NB_5000Z ? \
(((branch) == 0) ? \
(nb_number_memory_controllers == 2) ? \
nb_chipset == INTEL_NB_5000Z ? \
(nb_number_memory_controllers == 2) ? \
if ((branch) == 0) { \
nb_chipset == INTEL_NB_5000X || \
nb_chipset == INTEL_NB_5000V || \
} else if (nb_number_memory_controllers == 2) { \
nb_chipset == INTEL_NB_5000X || \
nb_chipset == INTEL_NB_5000V || \
}
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
(nb_chipset == INTEL_NB_7300 ? \
(nb_chipset == INTEL_NB_7300 ? \
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
: 0
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
((branch) == 0) ? \
(nb_number_memory_controllers == 2) ? \
(nb_number_memory_controllers == 2) ? \
if (nb_chipset == INTEL_NB_5100) \
else if ((branch) == 0) \
else if (nb_number_memory_controllers == 2) \
#define BANK_MASK 7
nb_chipset == INTEL_NB_5100) { \
} else { \
}
/* throttling disabled */
/* throttling disabled */
/* dimm type */
#define SPD_MEM_TYPE 2
#define SPD_DDR2 8
#define SPD_FBDIMM 9
#ifdef __cplusplus
}
#endif
#endif /* _NB5000_H */