0N/A/*
0N/A * CDDL HEADER START
0N/A *
0N/A * The contents of this file are subject to the terms of the
0N/A * Common Development and Distribution License (the "License").
0N/A * You may not use this file except in compliance with the License.
0N/A *
0N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
0N/A * or http://www.opensolaris.org/os/licensing.
0N/A * See the License for the specific language governing permissions
0N/A * and limitations under the License.
0N/A *
0N/A * When distributing Covered Code, include this CDDL HEADER in each
0N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
0N/A * If applicable, add the following below this CDDL HEADER, with the
0N/A * fields enclosed by brackets "[]" replaced with your own identifying
0N/A * information: Portions Copyright [yyyy] [name of copyright owner]
0N/A *
0N/A * CDDL HEADER END
0N/A */
1162N/A/*
0N/A * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
0N/A * Use is subject to license terms.
0N/A */
0N/A
0N/A#pragma ident "%Z%%M% %I% %E% SMI"
0N/A
0N/A#ifndef __RADEON_IO32_H__
850N/A#define __RADEON_IO32_H__
850N/A
850N/A
850N/A#ifdef _MULTI_DATAMODEL
0N/A/*
0N/A * For radeon_cp_init()
0N/A */
0N/Atypedef struct drm_radeon_init_32 {
0N/A int func;
850N/A unsigned int sarea_priv_offset;
0N/A int is_pci; /* for overriding only */
0N/A int cp_mode;
0N/A int gart_size;
0N/A int ring_size;
1020N/A int usec_timeout;
1020N/A
1020N/A unsigned int fb_bpp;
1020N/A unsigned int front_offset, front_pitch;
1020N/A unsigned int back_offset, back_pitch;
0N/A unsigned int depth_bpp;
0N/A unsigned int depth_offset, depth_pitch;
936N/A
1020N/A unsigned int fb_offset DEPRECATED;
0N/A unsigned int mmio_offset DEPRECATED;
0N/A unsigned int ring_offset;
0N/A unsigned int ring_rptr_offset;
0N/A unsigned int buffers_offset;
1070N/A unsigned int gart_textures_offset;
0N/A} drm_radeon_init_32_t;
0N/A
1073N/A/*
0N/A * radeon_cp_buffers()
0N/A */
0N/Atypedef struct drm_dma_32 {
0N/A int context;
0N/A int send_count;
943N/A uint32_t send_indices;
943N/A uint32_t send_sizes;
943N/A drm_dma_flags_t flags;
1469N/A int request_count;
943N/A int request_size;
0N/A uint32_t request_indices;
1163N/A uint32_t request_sizes;
1013N/A int granted_count;
1162N/A} drm_dma_32_t;
1162N/A
1013N/A/*
1013N/A * drm_radeon_clear()
0N/A */
974N/Atypedef struct drm_radeon_clear_32 {
974N/A unsigned int flags;
0N/A unsigned int clear_color;
1013N/A unsigned int clear_depth;
0N/A unsigned int color_mask;
1370N/A unsigned int depth_mask;
1370N/A uint32_t depth_boxes;
1370N/A} drm_radeon_clear_32_t;
1370N/A
0N/A/*
0N/A * For radeon_cp_texture()
0N/A */
1013N/Atypedef struct drm_radeon_tex_image_32 {
1370N/A unsigned int x, y;
974N/A unsigned int width, height;
974N/A uint32_t data;
0N/A} drm_radeon_tex_image_32_t;
0N/A
0N/Atypedef struct drm_radeon_texture_32 {
0N/A unsigned int offset;
0N/A int pitch;
1013N/A int format;
1370N/A int width;
0N/A int height;
0N/A uint32_t image;
0N/A} drm_radeon_texture_32_t;
1370N/A
0N/A/*
0N/A * for radeon_cp_stipple()
0N/A */
1370N/Atypedef struct drm_radeon_stipple_32 {
1020N/A uint32_t mask;
0N/A} drm_radeon_stipple_32_t;
0N/A
0N/A/*
0N/A * radeon_cp_vertex2()
974N/A */
974N/Atypedef struct drm_radeon_vertex2_32 {
974N/A int idx;
1020N/A int discard;
1013N/A int nr_states;
974N/A uint32_t state;
974N/A int nr_prims;
0N/A uint32_t prim;
0N/A} drm_radeon_vertex2_32_t;
0N/A
0N/A/*
1370N/A * radeon_cp_cmdbuf()
0N/A */
0N/Atypedef struct drm_radeon_kcmd_buffer_32 {
974N/A int bufsz;
1013N/A uint32_t buf;
974N/A int nbox;
1013N/A uint32_t boxes;
271N/A} drm_radeon_kcmd_buffer_32_t;
271N/A
1013N/A/*
271N/A * radeon_cp_getparam()
0N/A */
0N/Atypedef struct drm_radeon_getparam_32 {
974N/A int param;
1013N/A uint32_t value;
974N/A} drm_radeon_getparam_32_t;
1472N/A
1469N/A
0N/A/*
0N/A * radeon_mem_alloc()
974N/A */
1122N/Atypedef struct drm_radeon_mem_alloc_32 {
974N/A int region;
0N/A int alignment;
int size;
uint32_t region_offset; /* offset from start of fb or GART */
} drm_radeon_mem_alloc_32_t;
/*
* radeon_irq_emit()
*/
typedef struct drm_radeon_irq_emit_32 {
uint32_t irq_seq;
} drm_radeon_irq_emit_32_t;
/*
* radeon_cp_setparam()
*/
#pragma pack(1)
typedef struct drm_radeon_setparam_32 {
unsigned int param;
uint64_t value;
} drm_radeon_setparam_32_t;
#pragma pack()
#endif /* _MULTI_DATAMODEL */
#endif /* __RADEON_IO32_H__ */