0f7bfed6285b1bd6a65b05cc5f6ab4687ca999e6miao chen - Sun Microsystems - Beijing China * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Use is subject to license terms.
e57b9183811d515e3bbcd1a104516f0102fde114cg * radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
e57b9183811d515e3bbcd1a104516f0102fde114cg * All rights reserved.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Permission is hereby granted, free of charge, to any person obtaining a
e57b9183811d515e3bbcd1a104516f0102fde114cg * copy of this software and associated documentation files (the "Software"),
e57b9183811d515e3bbcd1a104516f0102fde114cg * to deal in the Software without restriction, including without limitation
e57b9183811d515e3bbcd1a104516f0102fde114cg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
e57b9183811d515e3bbcd1a104516f0102fde114cg * and/or sell copies of the Software, and to permit persons to whom the
e57b9183811d515e3bbcd1a104516f0102fde114cg * Software is furnished to do so, subject to the following conditions:
e57b9183811d515e3bbcd1a104516f0102fde114cg * The above copyright notice and this permission notice (including the next
e57b9183811d515e3bbcd1a104516f0102fde114cg * paragraph) shall be included in all copies or substantial portions of the
e57b9183811d515e3bbcd1a104516f0102fde114cg * Software.
e57b9183811d515e3bbcd1a104516f0102fde114cg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
e57b9183811d515e3bbcd1a104516f0102fde114cg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
e57b9183811d515e3bbcd1a104516f0102fde114cg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
e57b9183811d515e3bbcd1a104516f0102fde114cg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
e57b9183811d515e3bbcd1a104516f0102fde114cg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
e57b9183811d515e3bbcd1a104516f0102fde114cg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
e57b9183811d515e3bbcd1a104516f0102fde114cg * DEALINGS IN THE SOFTWARE.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Authors:
e57b9183811d515e3bbcd1a104516f0102fde114cg * Kevin E. Martin <martin@valinux.com>
e57b9183811d515e3bbcd1a104516f0102fde114cg * Gareth Hughes <gareth@valinux.com>
e57b9183811d515e3bbcd1a104516f0102fde114cg * Enable debugging information outputs. Need to recompile
e57b9183811d515e3bbcd1a104516f0102fde114cg * #define RADEON_FIFO_DEBUG 1
e57b9183811d515e3bbcd1a104516f0102fde114cg/* General customization: */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
e57b9183811d515e3bbcd1a104516f0102fde114cg * Interface history:
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.1 - ??
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.2 - Add vertex2 ioctl (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add stencil capability to clear ioctl (gareth, keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Increase MAX_TEXTURE_LEVELS (brian)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.3 - Add cmdbuf ioctl (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add support for new radeon packets (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add getparam ioctl (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.4 - Add scratch registers to get_param ioctl.
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.5 - Add r200 packets to cmdbuf ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add r200 function to init ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add 'scalar2' instruction to cmdbuf
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.6 - Add static GART memory manager
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add irq handler (won't be turned on unless X server knows to)
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add irq ioctls and irq_active getparam.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add wait command for cmdbuf ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add GART offset query for getparam
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
e57b9183811d515e3bbcd1a104516f0102fde114cg * and R200_PP_CUBIC_OFFSET_F1_[0..5].
e57b9183811d515e3bbcd1a104516f0102fde114cg * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add 'GET' queries for starting additional clients on different
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add texture rectangle support for r100.
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
e57b9183811d515e3bbcd1a104516f0102fde114cg * clients use to tell the DRM where they think the framebuffer is
e57b9183811d515e3bbcd1a104516f0102fde114cg * located in the card's address space
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
e57b9183811d515e3bbcd1a104516f0102fde114cg * and GL_EXT_blend_[func|equation]_separate on r200
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.12- Add R300 CP microcode support - this just loads the CP on r300
e57b9183811d515e3bbcd1a104516f0102fde114cg * (No 3D support yet - just microcode loading).
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add hyperz support, add hyperz flags to clear ioctl.
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.14- Add support for color tiling
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add R100/R200 surface allocation/free support
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.15- Add support for texture micro tiling
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add support for r100 cube maps
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
e57b9183811d515e3bbcd1a104516f0102fde114cg * texture filtering on r200
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.17- Add initial support for R300 (3D).
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.18- Add support for GL_ATI_fragment_shader, new packets
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_ATF_TFACTOR
e57b9183811d515e3bbcd1a104516f0102fde114cg * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.19- Add support for gart table in FB memory and PCIE r300
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.20- Add support for r300 texrect
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.21- Add support for card type getparam
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.23- Add new radeon memory map work from benh
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
e57b9183811d515e3bbcd1a104516f0102fde114cg * new packet type)
e57b9183811d515e3bbcd1a104516f0102fde114cg * Radeon chip families
e57b9183811d515e3bbcd1a104516f0102fde114cg * Chip flags
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_file_t *filp; /* 0: free, -1: heap, other: real files */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* SW interrupt */
e57b9183811d515e3bbcd1a104516f0102fde114cg struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
e57b9183811d515e3bbcd1a104516f0102fde114cg /* starting from here on, data is preserved accross an open */
e57b9183811d515e3bbcd1a104516f0102fde114cg * Check whether the given hardware address is inside the framebuffer or the
e57b9183811d515e3bbcd1a104516f0102fde114cg * GART area.
0bdffa0f07e70f45f6810116ca9d547631a4c3f8hh (off <= (dev_priv->fb_location + dev_priv->fb_size - 1))) || \
0bdffa0f07e70f45f6810116ca9d547631a4c3f8hh (off <= (dev_priv->gart_vm_start + dev_priv->gart_size - 1))))
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_wait_ring(drm_radeon_private_t *dev_priv, int n);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_do_cp_idle(drm_radeon_private_t *dev_priv);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_mem_release(drm_file_t *filp, struct mem_block *heap);
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int *sequence);
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int *sequence);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
0f7bfed6285b1bd6a65b05cc5f6ab4687ca999e6miao chen - Sun Microsystems - Beijing Chinaextern int radeon_driver_irq_preinstall(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_irq_postinstall(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_irq_uninstall(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_vblank_crtc_get(struct drm_device *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_firstopen(struct drm_device *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_preclose(drm_device_t *dev, drm_file_t *filp);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_postclose(drm_device_t *dev, drm_file_t *filp);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_open(drm_device_t *dev, drm_file_t *filp_priv);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long arg);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void r300_init_reg_flags(void);
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Flags for stats.boxes */
e57b9183811d515e3bbcd1a104516f0102fde114cg * Register definitions, register access macros and drmAddMap constants
e57b9183811d515e3bbcd1a104516f0102fde114cg * for Radeon kernel driver.
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCHOFF(x) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x)) : \
e57b9183811d515e3bbcd1a104516f0102fde114cg/* CP registers */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* CP command packets */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* GEN_INDX_PRIM is unsupported starting with R300 */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* MPEG settings from VHA code */
e57b9183811d515e3bbcd1a104516f0102fde114cg// set as reference header
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Constants */
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
e57b9183811d515e3bbcd1a104516f0102fde114cg (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
e57b9183811d515e3bbcd1a104516f0102fde114cg * Engine control helper macros
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg * Misc helper macros
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Perfbox functionality only. */
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg return (__ret); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg * Ring control
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg "ADVANCE_RING(): mismatch: nr: " \
e57b9183811d515e3bbcd1a104516f0102fde114cg "%x write: %x line: %d\n", \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Flush writes to ring */ \
e57b9183811d515e3bbcd1a104516f0102fde114cg /* read from PCI bus to ensure correct posting */ \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg while (_i > 0) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg while (_size > 0) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg#endif /* __RADEON_DRV_H__ */