e57b9183811d515e3bbcd1a104516f0102fde114cg/*
0f7bfed6285b1bd6a65b05cc5f6ab4687ca999e6miao chen - Sun Microsystems - Beijing China * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Use is subject to license terms.
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
e57b9183811d515e3bbcd1a104516f0102fde114cg *
e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
e57b9183811d515e3bbcd1a104516f0102fde114cg * All rights reserved.
e57b9183811d515e3bbcd1a104516f0102fde114cg *
e57b9183811d515e3bbcd1a104516f0102fde114cg * Permission is hereby granted, free of charge, to any person obtaining a
e57b9183811d515e3bbcd1a104516f0102fde114cg * copy of this software and associated documentation files (the "Software"),
e57b9183811d515e3bbcd1a104516f0102fde114cg * to deal in the Software without restriction, including without limitation
e57b9183811d515e3bbcd1a104516f0102fde114cg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
e57b9183811d515e3bbcd1a104516f0102fde114cg * and/or sell copies of the Software, and to permit persons to whom the
e57b9183811d515e3bbcd1a104516f0102fde114cg * Software is furnished to do so, subject to the following conditions:
e57b9183811d515e3bbcd1a104516f0102fde114cg *
e57b9183811d515e3bbcd1a104516f0102fde114cg * The above copyright notice and this permission notice (including the next
e57b9183811d515e3bbcd1a104516f0102fde114cg * paragraph) shall be included in all copies or substantial portions of the
e57b9183811d515e3bbcd1a104516f0102fde114cg * Software.
e57b9183811d515e3bbcd1a104516f0102fde114cg *
e57b9183811d515e3bbcd1a104516f0102fde114cg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
e57b9183811d515e3bbcd1a104516f0102fde114cg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
e57b9183811d515e3bbcd1a104516f0102fde114cg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
e57b9183811d515e3bbcd1a104516f0102fde114cg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
e57b9183811d515e3bbcd1a104516f0102fde114cg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
e57b9183811d515e3bbcd1a104516f0102fde114cg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
e57b9183811d515e3bbcd1a104516f0102fde114cg * DEALINGS IN THE SOFTWARE.
e57b9183811d515e3bbcd1a104516f0102fde114cg *
e57b9183811d515e3bbcd1a104516f0102fde114cg * Authors:
e57b9183811d515e3bbcd1a104516f0102fde114cg * Kevin E. Martin <martin@valinux.com>
e57b9183811d515e3bbcd1a104516f0102fde114cg * Gareth Hughes <gareth@valinux.com>
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#ifndef __RADEON_DRV_H__
e57b9183811d515e3bbcd1a104516f0102fde114cg#define __RADEON_DRV_H__
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Enable debugging information outputs. Need to recompile
e57b9183811d515e3bbcd1a104516f0102fde114cg *
e57b9183811d515e3bbcd1a104516f0102fde114cg * #define RADEON_FIFO_DEBUG 1
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* General customization: */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_NAME "radeon"
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_DESC "ATI Radeon"
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_DATE "20060524"
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Interface history:
e57b9183811d515e3bbcd1a104516f0102fde114cg *
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.1 - ??
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.2 - Add vertex2 ioctl (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add stencil capability to clear ioctl (gareth, keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Increase MAX_TEXTURE_LEVELS (brian)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.3 - Add cmdbuf ioctl (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add support for new radeon packets (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add getparam ioctl (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.4 - Add scratch registers to get_param ioctl.
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.5 - Add r200 packets to cmdbuf ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add r200 function to init ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add 'scalar2' instruction to cmdbuf
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.6 - Add static GART memory manager
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add irq handler (won't be turned on unless X server knows to)
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add irq ioctls and irq_active getparam.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add wait command for cmdbuf ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add GART offset query for getparam
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
e57b9183811d515e3bbcd1a104516f0102fde114cg * and R200_PP_CUBIC_OFFSET_F1_[0..5].
e57b9183811d515e3bbcd1a104516f0102fde114cg * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add 'GET' queries for starting additional clients on different
e57b9183811d515e3bbcd1a104516f0102fde114cg * VT's.
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Add texture rectangle support for r100.
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
e57b9183811d515e3bbcd1a104516f0102fde114cg * clients use to tell the DRM where they think the framebuffer is
e57b9183811d515e3bbcd1a104516f0102fde114cg * located in the card's address space
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
e57b9183811d515e3bbcd1a104516f0102fde114cg * and GL_EXT_blend_[func|equation]_separate on r200
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.12- Add R300 CP microcode support - this just loads the CP on r300
e57b9183811d515e3bbcd1a104516f0102fde114cg * (No 3D support yet - just microcode loading).
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add hyperz support, add hyperz flags to clear ioctl.
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.14- Add support for color tiling
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add R100/R200 surface allocation/free support
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.15- Add support for texture micro tiling
e57b9183811d515e3bbcd1a104516f0102fde114cg * - Add support for r100 cube maps
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
e57b9183811d515e3bbcd1a104516f0102fde114cg * texture filtering on r200
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.17- Add initial support for R300 (3D).
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.18- Add support for GL_ATI_fragment_shader, new packets
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and
e57b9183811d515e3bbcd1a104516f0102fde114cg * R200_EMIT_ATF_TFACTOR
e57b9183811d515e3bbcd1a104516f0102fde114cg * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.19- Add support for gart table in FB memory and PCIE r300
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.20- Add support for r300 texrect
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.21- Add support for card type getparam
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.23- Add new radeon memory map work from benh
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
e57b9183811d515e3bbcd1a104516f0102fde114cg * new packet type)
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_MAJOR 1
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_MINOR 25
e57b9183811d515e3bbcd1a104516f0102fde114cg#define DRIVER_PATCHLEVEL 0
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Radeon chip families
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cgenum radeon_family {
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_R100,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RV100,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RS100,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RV200,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RS200,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_R200,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RV250,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RS300,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RV280,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_R300,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_R350,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RV350,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RV380,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_R420,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RV410,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_RS400,
e57b9183811d515e3bbcd1a104516f0102fde114cg CHIP_LAST,
e57b9183811d515e3bbcd1a104516f0102fde114cg};
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgenum radeon_cp_microcode_version {
e57b9183811d515e3bbcd1a104516f0102fde114cg UCODE_R100,
e57b9183811d515e3bbcd1a104516f0102fde114cg UCODE_R200,
e57b9183811d515e3bbcd1a104516f0102fde114cg UCODE_R300,
e57b9183811d515e3bbcd1a104516f0102fde114cg};
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Chip flags
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FAMILY_MASK 0x0000ffffUL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FLAGS_MASK 0xffff0000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_IS_MOBILITY 0x00010000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_IS_IGP 0x00020000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SINGLE_CRTC 0x00040000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_IS_AGP 0x00080000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HAS_HIERZ 0x00100000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_IS_PCIE 0x00200000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NEW_MEMMAP 0x00400000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_IS_PCI 0x00800000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define GET_RING_HEAD(dev_priv) \
e57b9183811d515e3bbcd1a104516f0102fde114cg (dev_priv->writeback_works ? \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_READ32((dev_priv)->ring_rptr, 0) : \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_READ(RADEON_CP_RB_RPTR))
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SET_RING_HEAD(dev_priv, val) \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_WRITE32((dev_priv)->ring_rptr, 0, (val))
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct drm_radeon_freelist {
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int age;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_buf_t *buf;
e57b9183811d515e3bbcd1a104516f0102fde114cg struct drm_radeon_freelist *next;
e57b9183811d515e3bbcd1a104516f0102fde114cg struct drm_radeon_freelist *prev;
e57b9183811d515e3bbcd1a104516f0102fde114cg} drm_radeon_freelist_t;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct drm_radeon_ring_buffer {
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 *start;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 *end;
e57b9183811d515e3bbcd1a104516f0102fde114cg int size;
e57b9183811d515e3bbcd1a104516f0102fde114cg int size_l2qw;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 tail;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 tail_mask;
e57b9183811d515e3bbcd1a104516f0102fde114cg int space;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg int high_mark;
e57b9183811d515e3bbcd1a104516f0102fde114cg} drm_radeon_ring_buffer_t;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct drm_radeon_depth_clear_t {
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 rb3d_cntl;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 rb3d_zstencilcntl;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 se_cntl;
e57b9183811d515e3bbcd1a104516f0102fde114cg} drm_radeon_depth_clear_t;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgstruct drm_radeon_driver_file_fields {
e57b9183811d515e3bbcd1a104516f0102fde114cg int64_t radeon_fb_delta;
e57b9183811d515e3bbcd1a104516f0102fde114cg};
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgstruct mem_block {
e57b9183811d515e3bbcd1a104516f0102fde114cg struct mem_block *next;
e57b9183811d515e3bbcd1a104516f0102fde114cg struct mem_block *prev;
e57b9183811d515e3bbcd1a104516f0102fde114cg int start;
e57b9183811d515e3bbcd1a104516f0102fde114cg int size;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_file_t *filp; /* 0: free, -1: heap, other: real files */
e57b9183811d515e3bbcd1a104516f0102fde114cg};
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgstruct radeon_surface {
e57b9183811d515e3bbcd1a104516f0102fde114cg int refcount;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 lower;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 upper;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 flags;
e57b9183811d515e3bbcd1a104516f0102fde114cg};
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgstruct radeon_virt_surface {
e57b9183811d515e3bbcd1a104516f0102fde114cg int surface_index;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 lower;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 upper;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 flags;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_file_t *filp;
e57b9183811d515e3bbcd1a104516f0102fde114cg};
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct drm_radeon_private {
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_radeon_ring_buffer_t ring;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_radeon_sarea_t *sarea_priv;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 fb_location;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 fb_size;
e57b9183811d515e3bbcd1a104516f0102fde114cg int new_memmap;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg int gart_size;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 gart_vm_start;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long gart_buffers_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg int cp_mode;
e57b9183811d515e3bbcd1a104516f0102fde114cg int cp_running;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_radeon_freelist_t *head;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_radeon_freelist_t *tail;
e57b9183811d515e3bbcd1a104516f0102fde114cg int last_buf;
e57b9183811d515e3bbcd1a104516f0102fde114cg volatile u32 *scratch;
e57b9183811d515e3bbcd1a104516f0102fde114cg int writeback_works;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg int usec_timeout;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg int microcode_version;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg struct {
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 boxes;
e57b9183811d515e3bbcd1a104516f0102fde114cg int freelist_timeouts;
e57b9183811d515e3bbcd1a104516f0102fde114cg int freelist_loops;
e57b9183811d515e3bbcd1a104516f0102fde114cg int requested_bufs;
e57b9183811d515e3bbcd1a104516f0102fde114cg int last_frame_reads;
e57b9183811d515e3bbcd1a104516f0102fde114cg int last_clear_reads;
e57b9183811d515e3bbcd1a104516f0102fde114cg int clears;
e57b9183811d515e3bbcd1a104516f0102fde114cg int texture_uploads;
e57b9183811d515e3bbcd1a104516f0102fde114cg } stats;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg int do_boxes;
e57b9183811d515e3bbcd1a104516f0102fde114cg int page_flipping;
e57b9183811d515e3bbcd1a104516f0102fde114cg int current_page;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 color_fmt;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int front_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int front_pitch;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int back_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int back_pitch;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 depth_fmt;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int depth_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int depth_pitch;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 front_pitch_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 back_pitch_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 depth_pitch_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_radeon_depth_clear_t depth_clear;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long ring_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long ring_rptr_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long buffers_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long gart_textures_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_local_map_t *sarea;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_local_map_t *mmio;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_local_map_t *cp_ring;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_local_map_t *ring_rptr;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_local_map_t *gart_textures;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg struct mem_block *gart_heap;
e57b9183811d515e3bbcd1a104516f0102fde114cg struct mem_block *fb_heap;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg /* SW interrupt */
e57b9183811d515e3bbcd1a104516f0102fde114cg wait_queue_head_t swi_queue;
e57b9183811d515e3bbcd1a104516f0102fde114cg atomic_t swi_emitted;
e57b9183811d515e3bbcd1a104516f0102fde114cg int vblank_crtc;
e57b9183811d515e3bbcd1a104516f0102fde114cg uint32_t irq_enable_reg;
e57b9183811d515e3bbcd1a104516f0102fde114cg int irq_enabled;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg struct radeon_surface surfaces[RADEON_MAX_SURFACES];
e57b9183811d515e3bbcd1a104516f0102fde114cg struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long pcigart_offset;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_ati_pcigart_info gart_info;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 scratch_ages[5];
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg /* starting from here on, data is preserved accross an open */
e57b9183811d515e3bbcd1a104516f0102fde114cg uint32_t flags; /* see radeon_chip_flags */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg} drm_radeon_private_t;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct drm_radeon_buf_priv {
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 age;
e57b9183811d515e3bbcd1a104516f0102fde114cg} drm_radeon_buf_priv_t;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct drm_radeon_kcmd_buffer {
e57b9183811d515e3bbcd1a104516f0102fde114cg int bufsz;
e57b9183811d515e3bbcd1a104516f0102fde114cg char *buf;
e57b9183811d515e3bbcd1a104516f0102fde114cg int nbox;
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_clip_rect_t __user *boxes;
e57b9183811d515e3bbcd1a104516f0102fde114cg} drm_radeon_kcmd_buffer_t;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_no_wb;
e57b9183811d515e3bbcd1a104516f0102fde114cgextern drm_ioctl_desc_t radeon_ioctls[];
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_max_ioctl;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Check whether the given hardware address is inside the framebuffer or the
e57b9183811d515e3bbcd1a104516f0102fde114cg * GART area.
e57b9183811d515e3bbcd1a104516f0102fde114cg */
0bdffa0f07e70f45f6810116ca9d547631a4c3f8hh#define RADEON_CHECK_OFFSET(dev_priv, off) \
0bdffa0f07e70f45f6810116ca9d547631a4c3f8hh (((off >= dev_priv->fb_location) && \
0bdffa0f07e70f45f6810116ca9d547631a4c3f8hh (off <= (dev_priv->fb_location + dev_priv->fb_size - 1))) || \
0bdffa0f07e70f45f6810116ca9d547631a4c3f8hh ((off >= dev_priv->gart_vm_start) && \
0bdffa0f07e70f45f6810116ca9d547631a4c3f8hh (off <= (dev_priv->gart_vm_start + dev_priv->gart_size - 1))))
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg /* radeon_cp.c */
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_cp_init(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_cp_start(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_cp_stop(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_cp_reset(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_cp_idle(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_cp_resume(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_engine_reset(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_fullscreen(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_cp_buffers(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_freelist_reset(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern drm_buf_t *radeon_freelist_get(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_wait_ring(drm_radeon_private_t *dev_priv, int n);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_do_cp_idle(drm_radeon_private_t *dev_priv);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_mem_alloc(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_mem_free(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_mem_takedown(struct mem_block **heap);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_mem_release(drm_file_t *filp, struct mem_block *heap);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg /* radeon_irq.c */
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_irq_emit(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_irq_wait(DRM_IOCTL_ARGS);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_do_release(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_vblank_wait(drm_device_t *dev,
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int *sequence);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_vblank_wait2(drm_device_t *dev,
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int *sequence);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
0f7bfed6285b1bd6a65b05cc5f6ab4687ca999e6miao chen - Sun Microsystems - Beijing Chinaextern int radeon_driver_irq_preinstall(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_irq_postinstall(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_irq_uninstall(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_vblank_crtc_get(struct drm_device *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_unload(struct drm_device *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_firstopen(struct drm_device *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_preclose(drm_device_t *dev, drm_file_t *filp);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_postclose(drm_device_t *dev, drm_file_t *filp);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void radeon_driver_lastclose(drm_device_t *dev);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int radeon_driver_open(drm_device_t *dev, drm_file_t *filp_priv);
e57b9183811d515e3bbcd1a104516f0102fde114cgextern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned long arg);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* r300_cmdbuf.c */
e57b9183811d515e3bbcd1a104516f0102fde114cgextern void r300_init_reg_flags(void);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cgextern int r300_do_cp_cmdbuf(drm_device_t *dev,
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_file_t *fpriv, drm_radeon_kcmd_buffer_t *cmdbuf);
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Flags for stats.boxes */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BOX_DMA_IDLE 0x1
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BOX_RING_FULL 0x2
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BOX_FLIP 0x4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BOX_WAIT_IDLE 0x8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BOX_TEXTURE_LOAD 0x10
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Register definitions, register access macros and drmAddMap constants
e57b9183811d515e3bbcd1a104516f0102fde114cg * for Radeon kernel driver.
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AGP_COMMAND 0x0f60
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AGP_ENABLE (1<<8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AUX_SCISSOR_CNTL 0x26f0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_0_ENABLE (1 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_1_ENABLE (1 << 29)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_2_ENABLE (1 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BUS_CNTL 0x0030
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BUS_MASTER_DIS (1 << 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CLOCK_CNTL_DATA 0x000c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PLL_WR_EN (1 << 7)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CLOCK_CNTL_INDEX 0x0008
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CONFIG_APER_SIZE 0x0108
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CONFIG_MEMSIZE 0x00f8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC_OFFSET 0x0224
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC_OFFSET_CNTL 0x0228
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC_TILE_EN (1 << 15)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC2_OFFSET 0x0324
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC2_OFFSET_CNTL 0x0328
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_INDEX 0x0030
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_DATA 0x0034
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_CNTL 0x10
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_EN (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_BASE 0x13
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_START_LO 0x14
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_START_HI 0x15
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_END_LO 0x16
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIE_TX_GART_END_HI 0x17
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MPP_TB_CONFIG 0x01c0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MEM_CNTL 0x0140
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MEM_SDRAM_MODE_REG 0x0158
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AGP_BASE 0x0170
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_COLOROFFSET 0x1c40
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_COLORPITCH 0x1c48
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SRC_X_Y 0x1590
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DP_GUI_MASTER_CNTL 0x146c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_BRUSH_NONE (15 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_DST_16BPP (4 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_DST_24BPP (5 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_DST_32BPP (6 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_DST_DATATYPE_SHIFT 8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GMC_WR_MSK_DIS (1 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ROP3_S 0x00cc0000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ROP3_P 0x00f00000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DP_WRITE_MASK 0x16cc
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SRC_PITCH_OFFSET 0x1428
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DST_PITCH_OFFSET 0x142c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DST_PITCH_OFFSET_C 0x1c80
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DST_TILE_LINEAR (0 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DST_TILE_MACRO (1 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DST_TILE_MICRO ((uint_t)2 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DST_TILE_BOTH ((uint_t)3 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_REG0 0x15e0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_REG1 0x15e4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_REG2 0x15e8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_REG3 0x15ec
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_REG4 0x15f0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_REG5 0x15f4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_UMSK 0x0770
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCH_ADDR 0x0774
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCRATCHOFF(x) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define GET_SCRATCH(x) (dev_priv->writeback_works ? \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x)) : \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_READ(RADEON_SCRATCH_REG0 + 4*(x)))
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GEN_INT_CNTL 0x0040
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC_VBLANK_MASK (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC2_VBLANK_MASK (1 << 9)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SW_INT_ENABLE (1 << 25)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GEN_INT_STATUS 0x0044
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC_VBLANK_STAT (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC2_VBLANK_STAT (1 << 9)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SW_INT_TEST (1 << 25)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SW_INT_TEST_ACK (1 << 25)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SW_INT_FIRE (1 << 26)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HOST_PATH_CNTL 0x0130
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HDP_SOFT_RESET (1 << 26)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ISYNC_CNTL 0x1724
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RBBM_GUICNTL 0x172c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MC_AGP_LOCATION 0x014c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MC_FB_LOCATION 0x0148
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MCLK_CNTL 0x0012
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FORCEON_MCLKA (1 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FORCEON_MCLKB (1 << 17)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FORCEON_YCLKA (1 << 18)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FORCEON_YCLKB (1 << 19)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FORCEON_MC (1 << 20)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FORCEON_AIC (1 << 21)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_BORDER_COLOR_0 0x1d40
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_BORDER_COLOR_1 0x1d44
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_BORDER_COLOR_2 0x1d48
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CNTL 0x1c38
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_ENABLE (1 << 1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_LUM_MATRIX 0x1d00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_MISC 0x1c14
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_ROT_MATRIX_0 0x1d58
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_TXFILTER_0 0x1c54
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_TXOFFSET_0 0x1c5c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_TXFILTER_1 0x1c6c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_TXFILTER_2 0x1c84
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB2D_DC_FLUSH (3 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB2D_DC_FREE (3 << 2)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB2D_DC_FLUSH_ALL 0xf
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB2D_DC_BUSY 0x80000000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_CNTL 0x1c3c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PLANE_MASK_ENABLE (1 << 1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DITHER_ENABLE (1 << 2)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ROUND_ENABLE (1 << 3)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCALE_DITHER_ENABLE (1 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DITHER_INIT (1 << 5)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ROP_ENABLE (1 << 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_STENCIL_ENABLE (1 << 7)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_Z_ENABLE (1 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ZBLOCK16 (1 << 15)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DEPTHOFFSET 0x1c24
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DEPTHPITCH 0x1c28
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_PLANEMASK 0x1d84
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_STENCILREFMASK 0x1d7c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZCACHE_MODE 0x3250
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZC_FLUSH (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZC_FREE (1 << 2)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZC_FLUSH_ALL 0x5
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZC_BUSY 0x80000000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DC_FLUSH (3 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DC_FREE (3 << 2)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DC_FLUSH_ALL 0xf
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_DC_BUSY 0x80000000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_Z_TEST_MASK (7 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_Z_TEST_ALWAYS (7 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FORCE_Z_DIRTY (1 << 29)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_Z_WRITE_ENABLE (1 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_Z_DECOMPRESSION_ENABLE 0x80000000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RBBM_SOFT_RESET 0x00f0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_CP (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_HI (1 << 1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_SE (1 << 2)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_RE (1 << 3)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_PP (1 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_E2 (1 << 5)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_RB (1 << 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SOFT_RESET_HDP (1 << 7)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RBBM_STATUS 0x0e40
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RBBM_FIFOCNT_MASK 0x007f
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RBBM_ACTIVE 0X80000000UL
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RE_LINE_PATTERN 0x1cd0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RE_MISC 0x26c4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RE_TOP_LEFT 0x26c0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RE_WIDTH_HEIGHT 0x1c44
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RE_STIPPLE_ADDR 0x1cc8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RE_STIPPLE_DATA 0x1ccc
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_TL_0 0x1cd8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_BR_0 0x1cdc
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_TL_1 0x1ce0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_BR_1 0x1ce4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_TL_2 0x1ce8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCISSOR_BR_2 0x1cec
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_COORD_FMT 0x1c50
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_CNTL 0x1c4c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FFACE_CULL_CW (0 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BFACE_SOLID (3 << 1)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FFACE_SOLID (3 << 3)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ALPHA_SHADE_FLAT (1 << 10)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FOG_SHADE_FLAT (1 << 14)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FOG_SHADE_GOURAUD (2 << 14)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ROUND_MODE_TRUNC (0 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_CNTL_STATUS 0x2140
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_LINE_WIDTH 0x1db8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_VPORT_XSCALE 0x1d98
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_ZBIAS_FACTOR 0x1db0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE_CNTL 0x0b00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_TRANSLATION_DIS (1 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE0_INFO 0x0b0c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_TILE_MODE_MASK (3 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE1_INFO 0x0b1c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE2_INFO 0x0b2c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE3_INFO 0x0b3c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE4_INFO 0x0b4c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE5_INFO 0x0b5c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE6_INFO 0x0b6c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE7_INFO 0x0b7c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SW_SEMAPHORE 0x013c
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_UNTIL 0x1720
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_CRTC_PFLIP (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_2D_IDLE (1 << 14)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_3D_IDLE (1 << 15)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZMASKOFFSET 0x3234
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* CP registers */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_ME_RAM_ADDR 0x07d4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_ME_RAM_RADDR 0x07d8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_ME_RAM_DATAH 0x07dc
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_ME_RAM_DATAL 0x07e0
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_RB_BASE 0x0700
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_RB_CNTL 0x0704
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_BUF_SWAP_32BIT (2 << 16)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RB_NO_UPDATE (1 << 27)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_RB_RPTR_ADDR 0x070c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_RB_RPTR 0x0710
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_RB_WPTR 0x0714
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_RB_WPTR_DELAY 0x0718
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRE_WRITE_TIMER_SHIFT 0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRE_WRITE_LIMIT_SHIFT 23
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_IB_BASE 0x0738
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_CSQ_CNTL 0x0740
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CSQ_PRIBM_INDBM (4 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AIC_CNTL 0x01d0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AIC_STAT 0x01d4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AIC_PT_BASE 0x01d8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AIC_LO_ADDR 0x01dc
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AIC_HI_ADDR 0x01e0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AIC_TLB_ADDR 0x01e4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_AIC_TLB_DATA 0x01e8
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* CP command packets */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET0 0x00000000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_ONE_REG_WR (1 << 15)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET1 0x40000000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET2 0x80000000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET3 0xC0000000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_NOP 0x00001000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_NEXT_CHAR 0x00001900
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PLY_NEXTSCAN 0x00001D00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_SET_SCISSORS 0x00001E00
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* GEN_INDX_PRIM is unsupported starting with R300 */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_FOR_IDLE 0x00002600
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_3D_DRAW_VBUF 0x00002800
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_3D_DRAW_IMMD 0x00002900
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_3D_DRAW_INDX 0x00002A00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_LOAD_PALETTE 0x00002C00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_3D_LOAD_VBPNTR 0x00002F00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_3D_CLEAR_ZMASK 0x00003200
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_INDX_BUFFER 0x00003300
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_3D_DRAW_INDX_2 0x00003600
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_3D_CLEAR_HIZ 0x00003700
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_3D_CLEAR_CMASK 0x00003802
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CNTL_HOSTDATA_BLT 0x00009400
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CNTL_PAINT_MULTI 0x00009A00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CNTL_BITBLT_MULTI 0x00009B00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CNTL_SET_SCISSORS 0xC0001E00
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET_MASK 0xC0000000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VTX_Z_PRESENT 0x80000000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_NONE (0 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_POINT (1 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_LINE (2 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_TYPE_MASK 0xf
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_WALK_IND (1 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_WALK_LIST (2 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PRIM_WALK_RING (3 << 4)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_ORDER_BGRA (0 << 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_ORDER_RGBA (1 << 6)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MAOS_ENABLE (1 << 7)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VTX_FMT_R128_MODE (0 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_NUM_VERTICES_SHIFT 16
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_FORMAT_CI8 2
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_FORMAT_ARGB1555 3
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_FORMAT_RGB565 4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_FORMAT_ARGB8888 6
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_FORMAT_RGB332 7
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_FORMAT_RGB8 9
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_COLOR_FORMAT_ARGB4444 15
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_I8 0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_AI88 1
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_RGB332 2
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_ARGB1555 3
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_RGB565 4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_ARGB4444 5
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_ARGB8888 6
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_RGBA8888 7
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_Y8 8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_VYUY422 10
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_YVYU422 11
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_DXT1 12
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_DXT23 14
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_TXFORMAT_DXT45 15
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_0 0x2f00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_1 0x2f10
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_2 0x2f20
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_3 0x2f30
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_4 0x2f40
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_5 0x2f50
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_6 0x2f60
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXCBLEND_7 0x2f70
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TFACTOR_0 0x2ee0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_VTX_FMT_0 0x2088
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_VAP_CNTL 0x2080
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_TCL_MATRIX_SEL_0 0x2230
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXFILTER_5 0x2ca0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXFILTER_4 0x2c80
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXFILTER_3 0x2c60
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXFILTER_2 0x2c40
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXFILTER_1 0x2c20
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXFILTER_0 0x2c00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXOFFSET_5 0x2d78
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXOFFSET_4 0x2d60
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXOFFSET_3 0x2d48
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXOFFSET_2 0x2d30
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXOFFSET_1 0x2d18
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TXOFFSET_0 0x2d00
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_FACES_0 0x2c18
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_FACES_1 0x2c38
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_FACES_2 0x2c58
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_FACES_3 0x2c78
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_FACES_4 0x2c98
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_FACES_5 0x2cb8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_VTE_CNTL 0x20b0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TAM_DEBUG3 0x2d9c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_CNTL_X 0x2cc4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_VAP_CNTL_STATUS 0x2140
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RE_SCISSOR_TL_0 0x1cd8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RE_SCISSOR_TL_1 0x1ce0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RE_SCISSOR_TL_2 0x1ce8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_VTX_STATE_CNTL 0x2180
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RE_POINTSIZE 0x2648
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_TEX_SIZE_1 0x1d0c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_TEX_SIZE_2 0x1d14
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CUBIC_FACES_0 0x1d24
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CUBIC_FACES_1 0x1d28
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CUBIC_FACES_2 0x1d2c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_SE_TCL_STATE_FLUSH 0x2284
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
e57b9183811d515e3bbcd1a104516f0102fde114cg#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_3D_DRAW_IMMD_2 0xC0003500
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_VTX_FMT_1 0x208c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RE_CNTL 0x1c50
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_RB3D_BLENDCOLOR 0x3218
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_TRI_PERF 0x2cf8
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_AFS_0 0x2f80
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_VAP_PVS_CNTL_1 0x22D0
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* MPEG settings from VHA code */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_SETTO16_1 0x2694
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_SETTO16_2 0x2680
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_SETTO0_1 0x1840
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_FB_OFFSET 0x19e4
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_SETTO1AND70S 0x19d8
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_DST_PITCH 0x1408
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg// set as reference header
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Constants */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_LAST_DISPATCH 1
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MAX_VB_AGE 0x7fffffff
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_MAX_VB_VERTS (0xffff)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_RING_HIGH_MARK 128
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PCIGART_TABLE_SIZE (32*1024)
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_READ(reg) \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_READ32(dev_priv->mmio, (reg))
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WRITE(reg, val) \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_WRITE32(dev_priv->mmio, (reg), (val))
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_READ8(reg) \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_READ8(dev_priv->mmio, (reg))
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WRITE8(reg, val) \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_WRITE8(dev_priv->mmio, (reg), (val))
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WRITE_PLL(addr, val) \
e57b9183811d515e3bbcd1a104516f0102fde114cgdo { \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
e57b9183811d515e3bbcd1a104516f0102fde114cg ((addr) & 0x1f) | RADEON_PLL_WR_EN); \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WRITE_PCIE(addr, val) \
e57b9183811d515e3bbcd1a104516f0102fde114cgdo { \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WRITE8(RADEON_PCIE_INDEX, \
e57b9183811d515e3bbcd1a104516f0102fde114cg ((addr) & 0xff)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define CP_PACKET0(reg, n) \
e57b9183811d515e3bbcd1a104516f0102fde114cg (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
e57b9183811d515e3bbcd1a104516f0102fde114cg#define CP_PACKET0_TABLE(reg, n) \
e57b9183811d515e3bbcd1a104516f0102fde114cg (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
e57b9183811d515e3bbcd1a104516f0102fde114cg#define CP_PACKET1(reg0, reg1) \
e57b9183811d515e3bbcd1a104516f0102fde114cg (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
e57b9183811d515e3bbcd1a104516f0102fde114cg#define CP_PACKET2() \
e57b9183811d515e3bbcd1a104516f0102fde114cg (RADEON_CP_PACKET2)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define CP_PACKET3(pkt, n) \
e57b9183811d515e3bbcd1a104516f0102fde114cg (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Engine control helper macros
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WAIT_HOST_IDLECLEAN)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WAIT_HOST_IDLECLEAN)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_UNTIL_IDLE() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WAIT_3D_IDLECLEAN | \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WAIT_HOST_IDLECLEAN)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(RADEON_WAIT_CRTC_PFLIP); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FLUSH_CACHE() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(RADEON_RB3D_DC_FLUSH); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PURGE_CACHE() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FLUSH_ZCACHE() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(RADEON_RB3D_ZC_FLUSH); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PURGE_ZCACHE() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Misc helper macros
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Perfbox functionality only. */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RING_SPACE_TEST_WITH_RETURN(dev_priv) \
e57b9183811d515e3bbcd1a104516f0102fde114cgdo { \
e57b9183811d515e3bbcd1a104516f0102fde114cg if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg u32 head = GET_RING_HEAD(dev_priv); \
e57b9183811d515e3bbcd1a104516f0102fde114cg if (head == dev_priv->ring.tail) \
e57b9183811d515e3bbcd1a104516f0102fde114cg dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
e57b9183811d515e3bbcd1a104516f0102fde114cg } \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define VB_AGE_TEST_WITH_RETURN(dev_priv) \
e57b9183811d515e3bbcd1a104516f0102fde114cgdo { \
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
e57b9183811d515e3bbcd1a104516f0102fde114cg if (sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg int __ret = radeon_do_cp_idle(dev_priv); \
e57b9183811d515e3bbcd1a104516f0102fde114cg if (__ret) \
e57b9183811d515e3bbcd1a104516f0102fde114cg return (__ret); \
e57b9183811d515e3bbcd1a104516f0102fde114cg sarea_priv->last_dispatch = 0; \
e57b9183811d515e3bbcd1a104516f0102fde114cg radeon_freelist_reset(dev); \
e57b9183811d515e3bbcd1a104516f0102fde114cg } \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_DISPATCH_AGE(age) do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_LAST_DISPATCH_REG, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(age); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_FRAME_AGE(age) do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_LAST_FRAME_REG, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(age); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CLEAR_AGE(age) do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(RADEON_LAST_CLEAR_REG, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(age); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg/*
e57b9183811d515e3bbcd1a104516f0102fde114cg * Ring control
e57b9183811d515e3bbcd1a104516f0102fde114cg */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define BEGIN_RING(n) do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg if (dev_priv->ring.space <= (n) * sizeof (u32)) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg COMMIT_RING(); \
e57b9183811d515e3bbcd1a104516f0102fde114cg (void) radeon_wait_ring(dev_priv, (n) * sizeof (u32)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg } \
e57b9183811d515e3bbcd1a104516f0102fde114cg _nr = n; dev_priv->ring.space -= (n) * sizeof (u32); \
e57b9183811d515e3bbcd1a104516f0102fde114cg ring = dev_priv->ring.start; \
e57b9183811d515e3bbcd1a104516f0102fde114cg write = dev_priv->ring.tail; \
e57b9183811d515e3bbcd1a104516f0102fde114cg mask = dev_priv->ring.tail_mask; \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define ADVANCE_RING() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg if (((dev_priv->ring.tail + _nr) & mask) != write) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_ERROR( \
e57b9183811d515e3bbcd1a104516f0102fde114cg "ADVANCE_RING(): mismatch: nr: " \
e57b9183811d515e3bbcd1a104516f0102fde114cg "%x write: %x line: %d\n", \
e57b9183811d515e3bbcd1a104516f0102fde114cg ((dev_priv->ring.tail + _nr) & mask), \
e57b9183811d515e3bbcd1a104516f0102fde114cg write, __LINE__); \
e57b9183811d515e3bbcd1a104516f0102fde114cg } else \
e57b9183811d515e3bbcd1a104516f0102fde114cg dev_priv->ring.tail = write; \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#if defined(lint) || defined(__lint)
e57b9183811d515e3bbcd1a104516f0102fde114cg#define COMMIT_RING() /* For lint clean */
e57b9183811d515e3bbcd1a104516f0102fde114cg#else
e57b9183811d515e3bbcd1a104516f0102fde114cg#define COMMIT_RING() do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Flush writes to ring */ \
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_MEMORYBARRIER(); \
e57b9183811d515e3bbcd1a104516f0102fde114cg GET_RING_HEAD(dev_priv); \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); \
e57b9183811d515e3bbcd1a104516f0102fde114cg /* read from PCI bus to ensure correct posting */ \
e57b9183811d515e3bbcd1a104516f0102fde114cg RADEON_READ(RADEON_CP_RB_RPTR); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg#endif
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define OUT_RING(x) do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg ring[write++] = (x); \
e57b9183811d515e3bbcd1a104516f0102fde114cg write &= mask; \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define OUT_RING_REG(reg, val) do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(CP_PACKET0(reg, 0)); \
e57b9183811d515e3bbcd1a104516f0102fde114cg OUT_RING(val); \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#define OUT_RING_TABLE(tab, sz) do { \
e57b9183811d515e3bbcd1a104516f0102fde114cg int _size = (sz); \
e57b9183811d515e3bbcd1a104516f0102fde114cg int *_tab = (int *)(uintptr_t)(tab); \
e57b9183811d515e3bbcd1a104516f0102fde114cg \
e57b9183811d515e3bbcd1a104516f0102fde114cg if (write + _size > mask) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg int _i = (mask+1) - write; \
e57b9183811d515e3bbcd1a104516f0102fde114cg _size -= _i; \
e57b9183811d515e3bbcd1a104516f0102fde114cg while (_i > 0) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg *(int *)(ring + write) = *_tab++; \
e57b9183811d515e3bbcd1a104516f0102fde114cg write++; \
e57b9183811d515e3bbcd1a104516f0102fde114cg _i--; \
e57b9183811d515e3bbcd1a104516f0102fde114cg } \
e57b9183811d515e3bbcd1a104516f0102fde114cg write = 0; \
e57b9183811d515e3bbcd1a104516f0102fde114cg _tab += _i; \
e57b9183811d515e3bbcd1a104516f0102fde114cg } \
e57b9183811d515e3bbcd1a104516f0102fde114cg while (_size > 0) { \
e57b9183811d515e3bbcd1a104516f0102fde114cg *(ring + write) = *_tab++; \
e57b9183811d515e3bbcd1a104516f0102fde114cg write++; \
e57b9183811d515e3bbcd1a104516f0102fde114cg _size--; \
e57b9183811d515e3bbcd1a104516f0102fde114cg } \
e57b9183811d515e3bbcd1a104516f0102fde114cg write &= mask; \
e57b9183811d515e3bbcd1a104516f0102fde114cg} while (*"\0")
e57b9183811d515e3bbcd1a104516f0102fde114cg
e57b9183811d515e3bbcd1a104516f0102fde114cg#endif /* __RADEON_DRV_H__ */