e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Use is subject to license terms.
e57b9183811d515e3bbcd1a104516f0102fde114cg * radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
e57b9183811d515e3bbcd1a104516f0102fde114cg * All rights reserved.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Permission is hereby granted, free of charge, to any person obtaining a
e57b9183811d515e3bbcd1a104516f0102fde114cg * copy of this software and associated documentation files (the "Software"),
e57b9183811d515e3bbcd1a104516f0102fde114cg * to deal in the Software without restriction, including without limitation
e57b9183811d515e3bbcd1a104516f0102fde114cg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
e57b9183811d515e3bbcd1a104516f0102fde114cg * and/or sell copies of the Software, and to permit persons to whom the
e57b9183811d515e3bbcd1a104516f0102fde114cg * Software is furnished to do so, subject to the following conditions:
e57b9183811d515e3bbcd1a104516f0102fde114cg * The above copyright notice and this permission notice (including the next
e57b9183811d515e3bbcd1a104516f0102fde114cg * paragraph) shall be included in all copies or substantial portions of the
e57b9183811d515e3bbcd1a104516f0102fde114cg * Software.
e57b9183811d515e3bbcd1a104516f0102fde114cg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
e57b9183811d515e3bbcd1a104516f0102fde114cg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
e57b9183811d515e3bbcd1a104516f0102fde114cg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
e57b9183811d515e3bbcd1a104516f0102fde114cg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
e57b9183811d515e3bbcd1a104516f0102fde114cg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
e57b9183811d515e3bbcd1a104516f0102fde114cg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
e57b9183811d515e3bbcd1a104516f0102fde114cg * DEALINGS IN THE SOFTWARE.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Authors:
e57b9183811d515e3bbcd1a104516f0102fde114cg * Kevin E. Martin <martin@valinux.com>
e57b9183811d515e3bbcd1a104516f0102fde114cg * Gareth Hughes <gareth@valinux.com>
e57b9183811d515e3bbcd1a104516f0102fde114cg * Keith Whitwell <keith@tungstengraphics.com>
e57b9183811d515e3bbcd1a104516f0102fde114cg#pragma ident "%Z%%M% %I% %E% SMI"
e57b9183811d515e3bbcd1a104516f0102fde114cg * WARNING: If you change any of these defines, make sure to change the
e57b9183811d515e3bbcd1a104516f0102fde114cg * defines in the X server file (radeon_sarea.h)
e57b9183811d515e3bbcd1a104516f0102fde114cg * Old style state flags, required for sarea interface (1.1 and 1.2
e57b9183811d515e3bbcd1a104516f0102fde114cg * clears) and 1.2 drm_vertex2 ioctl.
e57b9183811d515e3bbcd1a104516f0102fde114cg /* handled client-side */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* version 1.2 and newer */
e57b9183811d515e3bbcd1a104516f0102fde114cg * New style per-packet identifiers for use in cmd_buffer ioctl with
e57b9183811d515e3bbcd1a104516f0102fde114cg * the RADEON_EMIT_PACKET command. Comments relate new packets to old
e57b9183811d515e3bbcd1a104516f0102fde114cg * state bits and the packet size:
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
e57b9183811d515e3bbcd1a104516f0102fde114cg * Commands understood by cmd_buffer ioctl. More can be added but
e57b9183811d515e3bbcd1a104516f0102fde114cg * obviously these can't be removed or changed:
e57b9183811d515e3bbcd1a104516f0102fde114cg /* emit one of the register packets above */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* emit hw packet wrapped in cliprects */
e57b9183811d515e3bbcd1a104516f0102fde114cg * emit hw wait commands -- note:
e57b9183811d515e3bbcd1a104516f0102fde114cg * doesn't make the cpu wait, just
e57b9183811d515e3bbcd1a104516f0102fde114cg * the graphics hardware
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef union {
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Allowed parameters for R300_CMD_PACKET3 */
e57b9183811d515e3bbcd1a104516f0102fde114cg * Commands understood by cmd_buffer ioctl for R300.
e57b9183811d515e3bbcd1a104516f0102fde114cg * The interface has not been stabilized, so some of these may be removed
e57b9183811d515e3bbcd1a104516f0102fde114cg * and eventually reordered before stabilization.
e57b9183811d515e3bbcd1a104516f0102fde114cg/* emit sequence ending 3d rendering */
e57b9183811d515e3bbcd1a104516f0102fde114cg * sys/user.h defines u
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef union {
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int u;
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Primitive types */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Vertex/indirect buffer size */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Byte offsets for indirect buffer data */
e57b9183811d515e3bbcd1a104516f0102fde114cg * There are 2 heaps (local/GART). Each region within a heap is a
e57b9183811d515e3bbcd1a104516f0102fde114cg * minimum of 64k, and there are at most 64 of them per heap.
e57b9183811d515e3bbcd1a104516f0102fde114cg * Blits have strict offset rules. All blit offset must be aligned on
e57b9183811d515e3bbcd1a104516f0102fde114cg * a 1K-byte boundary.
e57b9183811d515e3bbcd1a104516f0102fde114cg#endif /* __RADEON_SAREA_DEFINES__ */
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct {
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct {
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Context state */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Vertex format state */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Line state */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Bumpmap state */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Mask state */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Viewport state */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Setup state */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Misc state */
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct {
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Zbias state */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Setup registers for each texture unit */
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct {
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct {
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct {
e57b9183811d515e3bbcd1a104516f0102fde114cgtypedef struct {
e57b9183811d515e3bbcd1a104516f0102fde114cg * The channel for communication of state information to the
e57b9183811d515e3bbcd1a104516f0102fde114cg * kernel on firing a vertex buffer with either of the
e57b9183811d515e3bbcd1a104516f0102fde114cg * obsoleted vertex/index ioctls.
e57b9183811d515e3bbcd1a104516f0102fde114cg drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
e57b9183811d515e3bbcd1a104516f0102fde114cg /* The current cliprects, or a subset thereof. */
e57b9183811d515e3bbcd1a104516f0102fde114cg /* Counters for client-side throttling of rendering clients. */
e57b9183811d515e3bbcd1a104516f0102fde114cg tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1];
e57b9183811d515e3bbcd1a104516f0102fde114cg int pfCurrentPage; /* which buffer is being displayed? */
e57b9183811d515e3bbcd1a104516f0102fde114cg int tiling_enabled; /* set by drm, read by 2d + 3d clients */
e57b9183811d515e3bbcd1a104516f0102fde114cg * WARNING: If you change any of these defines, make sure to change the
e57b9183811d515e3bbcd1a104516f0102fde114cg * defines in the Xserver file (xf86drmRadeon.h)
e57b9183811d515e3bbcd1a104516f0102fde114cg * KW: actually it's illegal to change any of this (backwards compatibility).
e57b9183811d515e3bbcd1a104516f0102fde114cg * Radeon specific ioctls
e57b9183811d515e3bbcd1a104516f0102fde114cg * The device specific ioctl range is 0x40 to 0x79.
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
e57b9183811d515e3bbcd1a104516f0102fde114cg float f[5];
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int depth_mask; /* misnamed field: should be stencil */
e57b9183811d515e3bbcd1a104516f0102fde114cg * v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
e57b9183811d515e3bbcd1a104516f0102fde114cg * - allows multiple primitives and state changes in a single ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * - supports driver change to emit native primitives
e57b9183811d515e3bbcd1a104516f0102fde114cg * v1.3 - obsoletes drm_radeon_vertex2
e57b9183811d515e3bbcd1a104516f0102fde114cg * - allows arbitarily large cliprect list
e57b9183811d515e3bbcd1a104516f0102fde114cg * - allows updating of tcl packet, vector and scalar state
e57b9183811d515e3bbcd1a104516f0102fde114cg * - allows memory-efficient description of state updates
e57b9183811d515e3bbcd1a104516f0102fde114cg * - allows state to be emitted without a primitive
e57b9183811d515e3bbcd1a104516f0102fde114cg * (for clears, ctx switches)
e57b9183811d515e3bbcd1a104516f0102fde114cg * - allows more than one dma buffer to be referenced per ioctl
e57b9183811d515e3bbcd1a104516f0102fde114cg * - supports tcl driver
e57b9183811d515e3bbcd1a104516f0102fde114cg * - may be extended in future versions with new cmd types, packets
e57b9183811d515e3bbcd1a104516f0102fde114cg unsigned int x, y; /* Blit coordinates */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* enum for card type parameters */
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.3: An ioctl to get parameters that aren't available to the 3d
e57b9183811d515e3bbcd1a104516f0102fde114cg * client any other way.
e57b9183811d515e3bbcd1a104516f0102fde114cg/* card offset of 1st GART buffer */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Added with DRM version 1.6. */
e57b9183811d515e3bbcd1a104516f0102fde114cg#define RADEON_PARAM_GART_BASE 6 /* offset of GART base */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Added with DRM version 1.8. */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* 1.6: Set up a memory manager for regions of shared memory: */
e57b9183811d515e3bbcd1a104516f0102fde114cg int __user *region_offset; /* offset from start of fb or GART */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* 1.6: Userspace can request & wait on irq's: */
e57b9183811d515e3bbcd1a104516f0102fde114cg * 1.10: Clients tell the DRM where they think the framebuffer is located in
e57b9183811d515e3bbcd1a104516f0102fde114cg * the card's address space, via a new generic ioctl to set parameters
e57b9183811d515e3bbcd1a104516f0102fde114cg/* determined framebuffer location */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* enable/disable color tiling */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* PCI Gart Location */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* Use new memory map */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* PCI GART Table Size */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* VBLANK CRTC */
e57b9183811d515e3bbcd1a104516f0102fde114cg/* 1.14: Clients can allocate/free a surface */
e57b9183811d515e3bbcd1a104516f0102fde114cg#endif /* __RADEON_DRM_H__ */