0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China/* BEGIN CSTYLED */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Copyright (c) 2009, Intel Corporation.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * All Rights Reserved.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Permission is hereby granted, free of charge, to any person obtaining a
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * copy of this software and associated documentation files (the "Software"),
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * to deal in the Software without restriction, including without limitation
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * and/or sell copies of the Software, and to permit persons to whom the
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Software is furnished to do so, subject to the following conditions:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * The above copyright notice and this permission notice (including the next
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * paragraph) shall be included in all copies or substantial portions of the
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * IN THE SOFTWARE.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Eric Anholt <eric@anholt.net>
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Use is subject to license terms.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China#include "drmP.h"
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China#include "drm.h"
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China#include "i915_drm.h"
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China#include "i915_drv.h"
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China/** @file i915_gem_tiling.c
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Support for managing tiling state of buffer objects.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * The idea behind tiling is to increase cache hit rates by rearranging
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * pixel data so that a group of pixel accesses are in the same cacheline.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Performance improvement from doing this on the back/depth buffer are on
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * the order of 30%.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Intel architectures make this somewhat more complicated, though, by
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * adjustments made to addressing of data when the memory is in interleaved
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * mode (matched pairs of DIMMS) to improve memory bandwidth.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * For interleaved memory, the CPU sends every sequential 64 bytes
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * to an alternate memory channel so it can get the bandwidth from both.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * The GPU also rearranges its accesses for increased bandwidth to interleaved
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * memory, and it matches what the CPU does for non-tiled. However, when tiled
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * it does it a little differently, since one walks addresses not just in the
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * X direction but also Y. So, along with alternating channels when bit
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 6 of the address flips, it also alternates when other bits flip -- Bits 9
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * are common to both the 915 and 965-class hardware.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * The CPU also sometimes XORs in higher bits as well, to improve
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * bandwidth doing strided access like we do so frequently in graphics. This
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * is called "Channel XOR Randomization" in the MCH documentation. The result
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * All of this bit 6 XORing has an effect on our memory management,
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * as we need to make sure that the 3d driver can correctly address object
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * If we don't have interleaved memory, all tiling is safe and no swizzling is
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * When bit 17 is XORed in, we simply refuse to tile at all. Bit
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 17 is not just a page offset, so as we page an objet out and back in,
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * individual pages in it will have different bit 17 addresses, resulting in
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * each 64 bytes being swapped with its neighbor!
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Otherwise, if interleaved, we have to tell the 3d driver what the address
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * swizzling it needs to do is, since it's writing with the CPU to the pages
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * to match what the GPU expects.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Detects bit 6 swizzling of address lookup between IGD access and CPU
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * access through main memory.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing Chinai915_gem_detect_bit_6_swizzle(struct drm_device *dev)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China drm_i915_private_t *dev_priv = dev->dev_private;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (!IS_I9XX(dev)) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* As far as we know, the 865 doesn't have these bit 6
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * swizzling issues.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China } else if (IS_MOBILE(dev)) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* On mobile 9xx chipsets, channel interleave by the CPU is
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * determined by DCC. For single-channel, neither the CPU
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * nor the GPU do swizzling. For dual channel interleaved,
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * the GPU's interleave is bit 9 and 10 for X tiled, and bit
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 9 for Y tiled. The CPU's interleave is independent, and
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * can be based on either bit 11 (haven't seen this yet) or
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * bit 17 (common).
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China dcc = I915_READ(DCC);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China switch (dcc & DCC_ADDRESSING_MODE_MASK) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (dcc & DCC_CHANNEL_XOR_DISABLE) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* This is the base swizzling by the GPU for
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * tiled buffers.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_9_10;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_9;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* Bit 11 swizzling by the CPU in addition. */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_9_11;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* Bit 17 swizzling by the CPU in addition. */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (dcc == 0xffffffff) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_ERROR("Couldn't read from MCHBAR. "
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China "Disabling tiling.\n");
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* The 965, G33, and newer, have a very flexible memory
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * configuration. It will enable dual-channel mode
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * (interleaving) on as much memory as it can, and the GPU
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * will additionally sometimes enable different bit 6
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * swizzling for tiled objects from the CPU.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Here's what I found on the G965:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * slot fill memory size swizzling
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 0A 0B 1A 1B 1-ch 2-ch
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 512 0 0 0 512 0 O
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 512 0 512 0 16 1008 X
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 512 0 0 512 16 1008 X
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 0 512 0 512 16 1008 X
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * 1024 1024 1024 0 2048 1024 O
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * We could probably detect this based on either the DRB
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * matching, which was the case for the swizzling required in
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * the table above, or from the 1-ch value being less than
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * the minimum size of a rank.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_9_10;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_9;
2e6e901d9406e1a048063c872149376a6bf7cb63miao chen - Sun Microsystems - Beijing China /* FIXME: check with memory config on IGDNG */
2e6e901d9406e1a048063c872149376a6bf7cb63miao chen - Sun Microsystems - Beijing China if (IS_IGDNG(dev)) {
2e6e901d9406e1a048063c872149376a6bf7cb63miao chen - Sun Microsystems - Beijing China swizzle_x = I915_BIT_6_SWIZZLE_9_10;
2e6e901d9406e1a048063c872149376a6bf7cb63miao chen - Sun Microsystems - Beijing China swizzle_y = I915_BIT_6_SWIZZLE_9;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China dev_priv->mm.bit_6_swizzle_x = swizzle_x;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China dev_priv->mm.bit_6_swizzle_y = swizzle_y;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Returns the size of the fence for a tiled object of the given size.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing Chinai915_get_fence_size(struct drm_device *dev, int size)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (IS_I965G(dev)) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* The 965 can have fences at any page boundary. */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China return (size + PAGE_SIZE-1) & ~(PAGE_SIZE-1);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* Align the size to a power of two greater than the smallest
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (IS_I9XX(dev))
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China start = 1024 * 1024;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China start = 512 * 1024;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China for (i = start; i < size; i <<= 1)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China/* Check pitch constriants for all chips & tiling formats */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing Chinai915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China int tile_width;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* Linear is always fine */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (tiling_mode == I915_TILING_NONE)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China tile_width = 128;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China tile_width = 512;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (stride == 0)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* 965+ just needs multiples of tile width */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (IS_I965G(dev)) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (stride & (tile_width - 1))
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* Pre-965 needs power of two tile widths */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (stride < tile_width)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* We don't handle the aperture area covered by the fence being bigger
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * than the object size.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (i915_get_fence_size(dev, size) != size)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Sets the tiling mode of an object, returning the required swizzling of
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * bit 6 of addresses in the object.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing Chinai915_gem_set_tiling(DRM_IOCTL_ARGS)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China struct drm_i915_gem_set_tiling args;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China drm_i915_private_t *dev_priv = dev->dev_private;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China struct drm_gem_object *obj;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China struct drm_i915_gem_object *obj_priv;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (dev->driver->use_gem != 1)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_COPYFROM_WITH_RETURN(&args,
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China (struct drm_i915_gem_set_tiling __user *) data, sizeof(args));
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China obj = drm_gem_object_lookup(fpriv, args.handle);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (obj == NULL)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China obj_priv = obj->driver_private;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (!i915_tiling_ok(dev, args.stride, obj->size, args.tiling_mode)) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China drm_gem_object_unreference(obj);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_DEBUG("i915 tiling is not OK");
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China spin_lock(&dev->struct_mutex);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (args.tiling_mode == I915_TILING_NONE) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (args.tiling_mode == I915_TILING_X)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* If we can't handle the swizzling, make it untiled. */
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (args.swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.tiling_mode = I915_TILING_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (args.tiling_mode != obj_priv->tiling_mode) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China /* Unbind the object, as switching tiling means we're
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * switching the cache organization due to fencing, probably.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China ret = i915_gem_object_unbind(obj, 1);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (ret != 0) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.tiling_mode = obj_priv->tiling_mode;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China spin_unlock(&dev->struct_mutex);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China drm_gem_object_unreference(obj);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_ERROR("tiling switch!! unbind error %d", ret);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China obj_priv->tiling_mode = args.tiling_mode;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China obj_priv->stride = args.stride;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China ret = DRM_COPY_TO_USER((struct drm_i915_gem_set_tiling __user *) data, &args, sizeof(args));
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_ERROR(" gem set tiling error! %d", ret);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China drm_gem_object_unreference(obj);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China spin_unlock(&dev->struct_mutex);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China * Returns the current tiling mode and required bit 6 swizzling for the object.
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing Chinai915_gem_get_tiling(DRM_IOCTL_ARGS)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China struct drm_i915_gem_get_tiling args;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China drm_i915_private_t *dev_priv = dev->dev_private;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China struct drm_gem_object *obj;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China struct drm_i915_gem_object *obj_priv;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (dev->driver->use_gem != 1)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_COPYFROM_WITH_RETURN(&args,
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China (struct drm_i915_gem_get_tiling __user *) data, sizeof(args));
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China obj = drm_gem_object_lookup(fpriv, args.handle);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China if (obj == NULL)
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China obj_priv = obj->driver_private;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China spin_lock(&dev->struct_mutex);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.tiling_mode = obj_priv->tiling_mode;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China switch (obj_priv->tiling_mode) {
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China case I915_TILING_X:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China case I915_TILING_Y:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China case I915_TILING_NONE:
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China args.swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_ERROR("unknown tiling mode\n");
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China ret = DRM_COPY_TO_USER((struct drm_i915_gem_get_tiling __user *) data, &args, sizeof(args));
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China DRM_ERROR(" gem get tiling error! %d", ret);
0035d21c77a24d02faf34c10aabc120ca692efb5miao chen - Sun Microsystems - Beijing China drm_gem_object_unreference(obj);