ata_common.h revision 0f2c99a46e005b1add7df43157ee8516e585157a
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0f2c99a46e005b1add7df43157ee8516e585157ayt * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Use is subject to license terms.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#pragma ident "%Z%%M% %I% %E% SMI"
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfextern "C" {
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * device types
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Largest sector allowed in 28 bit mode
0f2c99a46e005b1add7df43157ee8516e585157ayt * Largest sector count allowed for device firmware file in one command.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * ata-options property configuration bits
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* ad_flags (per-drive) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define AD_INT13LBA 0x80 /* supports LBA at Int13 interface */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* max targets and luns */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * PCI-IDE Bus Mastering Scatter/Gather list size
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Controller port address defaults
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * port offsets from base address ioaddr1
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * port offsets from base address ioaddr2
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Device control register */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * ATA-6 spec
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * In 48-bit addressing, reading the LBA location and count
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * registers when the high-order bit is set reads the "previous
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * content" (LBA bits 47:24, count bits 15:8) instead of the
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * "most recent" values (LBA bits 23:0, count bits 7:0).
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Status bits from AT_STATUS register
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Status bits from AT_ERROR register
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATE_BBK_ICRC 0x80 /* bad block detected in ATA-1 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* ICRC error in ATA-4 and newer */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Drive selectors for AT_DRVHD register
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATDH_LBA 0x40 /* addressing in LBA mode not chs */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATDH_DRIVE0 0xa0 /* or into AT_DRVHD to select drive 0 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATDH_DRIVE1 0xb0 /* or into AT_DRVHD to select drive 1 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Feature register bits
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * common bits and options for set features (ATC_SET_FEAT)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Test which version of ATA is supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Test if supported version >= ATA-n */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Test whether a device is a CD drive */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* macros from old common hba code */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf (ddi_prop_op(DDI_DEV_T_ANY, (devi), PROP_LEN_AND_VAL_BUF, \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf (ddi_getlongprop(DDI_DEV_T_ANY, (devi), DDI_PROP_DONTPASS, \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * per-controller soft-state data structure
507c32411f3f101e90ca2120f042b5ee698ba1d5mlftypedef struct ata_ctl {
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf struct ata_drv *ac_active_drvp; /* active drive, if any */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf struct ata_pkt *ac_active_pktp; /* active packet, if any */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * port addresses associated with ioaddr1
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * port addresses associated with ioaddr2
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * handle and port addresss for PCI-IDE Bus Master controller
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf uchar_t ac_pciide_bm; /* Bus Mastering PCI-IDE device */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Scatter/Gather list for PCI-IDE Bus Mastering controllers
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * data for managing ARQ on ATAPI devices
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf struct ata_pkt *ac_arq_pktp; /* pkt for performing ATAPI ARQ */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf struct ata_pkt *ac_fault_pktp; /* pkt that caused ARQ */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* ac_flags (per-controller) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Bug 1256489:
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * If AC_BSY_WAIT needs to be set for laptops that do
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * suspend/resume but do not correctly wait for the busy bit to
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * drop after a resume.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* ac_timing_flags (per-controller) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define AC_BSY_WAIT 0x1 /* tweak timing in ata_start & atapi_start */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify drive data */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* OFFSET COMMENT */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_trksiz; /* 4 # of unformatted bytes/track */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_secsiz; /* 5 # of unformatted bytes/sector */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_bufsz; /* 21 Buffer size in 512 byte incr */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_validinfo; /* 53 bit0: wds 54-58, bit1: 64-70 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_cursectrk; /* 56 # of current sectors/track */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_cursccp[2]; /* 57 current sectors capacity */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_addrsec[2]; /* 60 LBA only: no of addr secs */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_advpiomode; /* 64 advanced PIO modes supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_minmwdma; /* 65 min multi-word dma cycle info */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_recmwdma; /* 66 rec multi-word dma cycle info */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_minpioflow; /* 68 min PIO cycle info w/flow ctl */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_majorversion; /* 80 major versions supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_minorversion; /* 81 minor version number supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_cmdset83; /* 83 more command sets supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_cmdset84; /* 84 more command sets supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_erasetimex; /* 90 enhanced security erase time */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_addrsecxt[4]; /* 100 extended max LBA sector */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_lastlun; /* 126 last LUN, as per SFF-8070i */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf ushort_t ai_curmedser[30]; /* 176-205 current media serial number */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Drive: general config bits - word 0 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Drive: common capability bits - word 49 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_RESERVED_IDPKT 0x1000 /* rsrvd for identify pkt dev */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Driver ai_validinfo (word 53) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_VALIDINFO_83 0x0004 /* word 83 supported fields valid */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_VALIDINFO_70_64 0x0002 /* word 70:64 sup. fields valid */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Drive: ai_dworddma (word 63) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MDMA_SEL_MASK 0x0700 /* Multiword DMA selected */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MDMA_2_SEL 0x0400 /* Multiword DMA mode 2 selected */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MDMA_1_SEL 0x0200 /* Multiword DMA mode 1 selected */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MDMA_0_SEL 0x0100 /* Multiword DMA mode 0 selected */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MDMA_2_SUP 0x0004 /* Multiword DMA mode 2 supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MDMA_1_SUP 0x0002 /* Multiword DMA mode 1 supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MDMA_0_SUP 0x0001 /* Multiword DMA mode 0 supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Drive: ai_advpiomode (word 64) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_ADVPIO_4_SUP 0x0002 /* PIO mode 4 supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_ADVPIO_3_SUP 0x0001 /* PIO mode 3 supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Drive: ai_majorversion (word 80) */
0f2c99a46e005b1add7df43157ee8516e585157ayt#define ATAC_MAJVER_8 0x0100 /* ATA/ATAPI-8 version supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MAJVER_6 0x0040 /* ATA/ATAPI-6 version supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_MAJVER_4 0x0010 /* ATA/ATAPI-4 version supported */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Drive: command set supported/enabled bits - words 83 and 86 */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* Identify Drive: ai_features85 (word 85) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATAC_FEATURES85_WCE 0x0020 /* write cache enabled */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* per-drive data struct */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlftypedef struct ata_drv {
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* Used by atapi side only */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* Used by disk side only */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Geometry note: The following three values are the geometry
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * that the driver will use. They may differ from the
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * geometry reported by the controller and/or BIOS. See note
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * on ata_fix_large_disk_geometry in ata_disk.c for more
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * details.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Support for 48-bit LBA (ATA-6)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlftypedef struct ata_tgt {
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf/* values for ad_pciide_dma */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (ata_pkt_t *) to (gcmd_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (gcmd_t *) to (ata_pkt_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define GCMD2APKT(gcmdp) ((ata_pkt_t *)gcmdp->cmd_private)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (gtgt_t *) to (ata_ctl_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define GTGTP2ATAP(gtgtp) ((ata_ctl_t *)GTGTP2HBA(gtgtp))
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (gtgt_t *) to (ata_tgt_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define GTGTP2ATATGTP(gtgtp) ((ata_tgt_t *)GTGTP2TARGET(gtgtp))
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (gtgt_t *) to (ata_drv_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define GTGTP2ATADRVP(gtgtp) (GTGTP2ATATGTP(gtgtp)->at_drvp)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (gcmd_t *) to (ata_tgt_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define GCMD2TGT(gcmdp) GTGTP2ATATGTP(GCMDP2GTGTP(gcmdp))
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (gcmd_t *) to (ata_drv_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define GCMD2DRV(gcmdp) GTGTP2ATADRVP(GCMDP2GTGTP(gcmdp))
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (ata_pkt_t *) to (ata_drv_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * (struct hba_tran *) to (ata_ctl_t *)
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * ata common packet structure
507c32411f3f101e90ca2120f042b5ee698ba1d5mlftypedef struct ata_pkt {
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf uchar_t ap_pciide_dma; /* This pkt uses DMA transfer mode */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf prde_t ap_sg_list[ATA_DMA_NSEGS]; /* Scatter/Gather list */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* command, starting sector number, sector count */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* saved status and error registers for error case */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* disk/atapi callback routines */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf int (*ap_start)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf int (*ap_intr)(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* Used by disk side */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf caddr_t ap_v_addr_sav; /* Original I/O buffer address. */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* left to read/write. */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf /* Used by atapi side */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf uchar_t ap_cdb_pad; /* padding after SCSI CDB (in shorts) */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf struct scsi_arq_status *ap_scbp; /* ptr to SCSI status block */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * defines for ap_flags
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define AP_XFERRED_DATA 0x0400 /* atapi: data transferred */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define AP_GOT_STATUS 0x0800 /* atapi: status received */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define AP_ARQ_ON_ERROR 0x1000 /* atapi: do ARQ on error */
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * public function prototypes
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_check_drive_blacklist(struct ata_id *aidp, uint_t flags);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_command(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, int expect_drdy,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf int silent, uint_t busy_wait, uchar_t cmd, uchar_t feature,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf uchar_t count, uchar_t sector, uchar_t head, uchar_t cyl_low,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_get_status_clear_intr(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_prop_create(dev_info_t *tgt_dip, ata_drv_t *ata_drvp, char *name);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_queue_cmd(int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *),
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_set_feature(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_wait(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_wait3(ddi_acc_handle_t io_hdl, caddr_t ioaddr, uchar_t onbits1,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * It's not clear to which of the two following delay mechanisms is
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * We really need something better than drv_usecwait(). The
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * granularity for drv_usecwait() currently is 10 usec. This means that
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * the ATA_DELAY_400NSEC macro delays 25 timers longer than necessary.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * Doing 4 inb()'s from the alternate status register is guaranteed
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * to take at least 400 nsecs (it may take as long as 4 usecs.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * The problem with inb() is that on an x86 platform it also causes
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * a CPU synchronization, CPU write buffer flush, cache flush, and
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * flushes posted writes in any PCI bridge devices between the CPU
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * and the ATA controller.
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#define ATA_DELAY_400NSEC(H, A) \
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf * PCIIDE DMA (Bus Mastering) functions and data in ata_dma.c
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_pciide_alloc(dev_info_t *dip, ata_ctl_t *ata_ctlp);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfvoid ata_pciide_dma_sg_func(gcmd_t *gcmdp, ddi_dma_cookie_t *dmackp,
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfvoid ata_pciide_dma_setup(ata_ctl_t *ata_ctlp, prde_t *srcp, int sg_cnt);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfvoid ata_pciide_dma_start(ata_ctl_t *ata_ctlp, uchar_t direction);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlfint ata_pciide_status_dmacheck_clear(ata_ctl_t *ata_ctlp);
507c32411f3f101e90ca2120f042b5ee698ba1d5mlf#endif /* _ATA_COMMON_H */