amd_iommu_log.h revision 7125fcbd464abbefeb0c10e07d1a93245fc59863
2N/A/*
2N/A * CDDL HEADER START
2N/A *
2N/A * The contents of this file are subject to the terms of the
2N/A * Common Development and Distribution License (the "License").
2N/A * You may not use this file except in compliance with the License.
2N/A *
2N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2N/A * or http://www.opensolaris.org/os/licensing.
2N/A * See the License for the specific language governing permissions
2N/A * and limitations under the License.
2N/A *
2N/A * When distributing Covered Code, include this CDDL HEADER in each
2N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2N/A * If applicable, add the following below this CDDL HEADER, with the
2N/A * fields enclosed by brackets "[]" replaced with your own identifying
2N/A * information: Portions Copyright [yyyy] [name of copyright owner]
2N/A *
2N/A * CDDL HEADER END
2N/A */
2N/A/*
2N/A * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
2N/A * Use is subject to license terms.
2N/A */
2N/A
2N/A#ifndef _AMD_IOMMU_LOG_H
2N/A#define _AMD_IOMMU_LOG_H
2N/A
2N/A#ifdef __cplusplus
2N/Aextern "C" {
2N/A#endif
2N/A
2N/A#include <sys/amd_iommu.h>
2N/A
2N/A#ifdef _KERNEL
2N/A
2N/A#define EV2OFF(e) ((e) << 4)
2N/A#define OFF2EV(o) ((o) >> 4)
2N/A
2N/Atypedef enum {
2N/A AMD_IOMMU_EVENT_INVALID = 0,
2N/A AMD_IOMMU_EVENT_DEVTAB_ILLEGAL_ENTRY = 1,
2N/A AMD_IOMMU_EVENT_IO_PAGE_FAULT = 2,
2N/A AMD_IOMMU_EVENT_DEVTAB_HW_ERROR = 3,
2N/A AMD_IOMMU_EVENT_PGTABLE_HW_ERROR = 4,
2N/A AMD_IOMMU_EVENT_CMDBUF_ILLEGAL_CMD = 5,
2N/A AMD_IOMMU_EVENT_CMDBUF_HW_ERROR = 6,
2N/A AMD_IOMMU_EVENT_IOTLB_INVAL_TO = 7,
2N/A AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ = 8
2N/A} amd_iommu_event_t;
2N/A
2N/A/* Common to all events */
2N/A#define AMD_IOMMU_EVENT_TYPE (31 << 16 | 28)
2N/A
2N/A/* Illegal device Table Entry Event bits */
2N/A#define AMD_IOMMU_EVENT_DEVTAB_ILL_DEVICEID (15 << 16 | 0)
2N/A#define AMD_IOMMU_EVENT_DEVTAB_ILL_TR (24 << 16 | 24)
2N/A#define AMD_IOMMU_EVENT_DEVTAB_ILL_RZ (23 << 16 | 23)
2N/A#define AMD_IOMMU_EVENT_DEVTAB_ILL_RW (21 << 16 | 21)
2N/A#define AMD_IOMMU_EVENT_DEVTAB_ILL_INTR (19 << 16 | 19)
2N/A#define AMD_IOMMU_EVENT_DEVTAB_ILL_VADDR_LO (31 << 16 | 2)
2N/A
/* IO Page Fault event bits */
#define AMD_IOMMU_EVENT_IO_PGFAULT_DEVICEID (15 << 16 | 0)
#define AMD_IOMMU_EVENT_IO_PGFAULT_TR (24 << 16 | 24)
#define AMD_IOMMU_EVENT_IO_PGFAULT_RZ (23 << 16 | 23)
#define AMD_IOMMU_EVENT_IO_PGFAULT_PE (22 << 16 | 22)
#define AMD_IOMMU_EVENT_IO_PGFAULT_RW (21 << 16 | 21)
#define AMD_IOMMU_EVENT_IO_PGFAULT_PR (20 << 16 | 20)
#define AMD_IOMMU_EVENT_IO_PGFAULT_INTR (19 << 16 | 19)
#define AMD_IOMMU_EVENT_IO_PGFAULT_DOMAINID (15 << 16 | 0)
/* Device Table HW Error event bits */
#define AMD_IOMMU_EVENT_DEVTAB_HWERR_DEVICEID (15 << 16 | 0)
#define AMD_IOMMU_EVENT_DEVTAB_HWERR_TYPE (26 << 16 | 25)
#define AMD_IOMMU_EVENT_DEVTAB_HWERR_TR (24 << 16 | 24)
#define AMD_IOMMU_EVENT_DEVTAB_HWERR_RW (21 << 16 | 21)
#define AMD_IOMMU_EVENT_DEVTAB_HWERR_INTR (19 << 16 | 19)
#define AMD_IOMMU_EVENT_DEVTAB_HWERR_PHYSADDR_LO (31 << 16 | 4)
/* Page Table HW Error event bits */
#define AMD_IOMMU_EVENT_PGTABLE_HWERR_DEVICEID (15 << 16 | 0)
#define AMD_IOMMU_EVENT_DEVTAB_HWERR_TYPE (26 << 16 | 25)
#define AMD_IOMMU_EVENT_PGTABLE_HWERR_TR (24 << 16 | 24)
#define AMD_IOMMU_EVENT_PGTABLE_HWERR_RW (21 << 16 | 21)
#define AMD_IOMMU_EVENT_PGTABLE_HWERR_INTR (19 << 16 | 19)
#define AMD_IOMMU_EVENT_PGTABLE_HWERR_DOMAINID (15 << 16 | 0)
#define AMD_IOMMU_EVENT_PGTABLE_HWERR_PHYSADDR_LO (31 << 16 | 3)
/* Illegal Command Error event bits */
#define AMD_IOMMU_EVENT_CMDBUF_ILLEGAL_CMD_PHYS_LO (31 << 16 | 4)
/* Command Buffer HW Error event bits */
#define AMD_IOMMU_EVENT_CMDBUF_HWERR_TYPE (26 << 16 | 25)
#define AMD_IOMMU_EVENT_CMDBUF_HWERR_PHYS_LO (31 << 16 | 4)
/* IOTLB Invalidation TO event bits */
#define AMD_IOMMU_EVENT_IOTLB_INVAL_TO_DEVICEID (15 << 16 | 0)
#define AMD_IOMMU_EVENT_IOTLB_INVAL_TO_TYPE (26 << 16 | 25)
#define AMD_IOMMU_EVENT_IOTLB_INVAL_TO_PHYS_LO (31 << 16 | 4)
/* Illegal Device request event bits */
#define AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ_DEVICEID (15 << 16 | 0)
#define AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ_TYPE (27 << 16 | 25)
#define AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ_TR (24 << 16 | 24)
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _AMD_IOMMU_LOG_H */