amd8111s_main.c revision 193974072f41a843678abf5f61979c748687e66b
d62bc4badc1c1f1549c961cfb8b420e650e1272byz * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Use is subject to license terms.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Redistribution and use in source and binary forms, with or without
75ab5f91d942eea4138efe4799ca0589870c3899lh * modification, are permitted provided that the following conditions are met:
75ab5f91d942eea4138efe4799ca0589870c3899lh * + Redistributions of source code must retain the above copyright notice,
75ab5f91d942eea4138efe4799ca0589870c3899lh * + this list of conditions and the following disclaimer.
75ab5f91d942eea4138efe4799ca0589870c3899lh * + Redistributions in binary form must reproduce the above copyright
75ab5f91d942eea4138efe4799ca0589870c3899lh * + notice, this list of conditions and the following disclaimer in the
75ab5f91d942eea4138efe4799ca0589870c3899lh * + documentation and/or other materials provided with the distribution.
75ab5f91d942eea4138efe4799ca0589870c3899lh * + Neither the name of Advanced Micro Devices, Inc. nor the names of its
75ab5f91d942eea4138efe4799ca0589870c3899lh * + contributors may be used to endorse or promote products derived from
75ab5f91d942eea4138efe4799ca0589870c3899lh * + this software without specific prior written permission.
75ab5f91d942eea4138efe4799ca0589870c3899lh * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
75ab5f91d942eea4138efe4799ca0589870c3899lh * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
75ab5f91d942eea4138efe4799ca0589870c3899lh * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
75ab5f91d942eea4138efe4799ca0589870c3899lh * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
75ab5f91d942eea4138efe4799ca0589870c3899lh * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR
75ab5f91d942eea4138efe4799ca0589870c3899lh * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
75ab5f91d942eea4138efe4799ca0589870c3899lh * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75ab5f91d942eea4138efe4799ca0589870c3899lh * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
75ab5f91d942eea4138efe4799ca0589870c3899lh * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
75ab5f91d942eea4138efe4799ca0589870c3899lh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75ab5f91d942eea4138efe4799ca0589870c3899lh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
75ab5f91d942eea4138efe4799ca0589870c3899lh * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
75ab5f91d942eea4138efe4799ca0589870c3899lh * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Import/Export/Re-Export/Use/Release/Transfer Restrictions and
75ab5f91d942eea4138efe4799ca0589870c3899lh * Compliance with Applicable Laws. Notice is hereby given that
75ab5f91d942eea4138efe4799ca0589870c3899lh * the software may be subject to restrictions on use, release,
75ab5f91d942eea4138efe4799ca0589870c3899lh * transfer, importation, exportation and/or re-exportation under
75ab5f91d942eea4138efe4799ca0589870c3899lh * the laws and regulations of the United States or other
75ab5f91d942eea4138efe4799ca0589870c3899lh * countries ("Applicable Laws"), which include but are not
75ab5f91d942eea4138efe4799ca0589870c3899lh * limited to U.S. export control laws such as the Export
75ab5f91d942eea4138efe4799ca0589870c3899lh * Administration Regulations and national security controls as
75ab5f91d942eea4138efe4799ca0589870c3899lh * defined thereunder, as well as State Department controls under
75ab5f91d942eea4138efe4799ca0589870c3899lh * the U.S. Munitions List. Permission to use and/or
75ab5f91d942eea4138efe4799ca0589870c3899lh * redistribute the software is conditioned upon compliance with
75ab5f91d942eea4138efe4799ca0589870c3899lh * all Applicable Laws, including U.S. export control laws
75ab5f91d942eea4138efe4799ca0589870c3899lh * regarding specifically designated persons, countries and
75ab5f91d942eea4138efe4799ca0589870c3899lh * nationals of countries subject to national security controls.
75ab5f91d942eea4138efe4799ca0589870c3899lh/* include files */
75ab5f91d942eea4138efe4799ca0589870c3899lh/* Global macro Definations */
193974072f41a843678abf5f61979c748687e66bSherry Moorestatic char ident[] = "AMD8111 10/100M Ethernet";
75ab5f91d942eea4138efe4799ca0589870c3899lh * Driver Entry Points
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic int amd8111s_attach(dev_info_t *, ddi_attach_cmd_t);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic int amd8111s_detach(dev_info_t *, ddi_detach_cmd_t);
75ab5f91d942eea4138efe4799ca0589870c3899lh * GLD Entry points prototype
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void amd8111s_m_ioctl(void *, queue_t *, mblk_t *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic int amd8111s_m_multicst(void *, boolean_t, const uint8_t *addr);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic int amd8111s_m_start(void *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void amd8111s_m_stop(void *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic int amd8111s_unattach(dev_info_t *, struct LayerPointers *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic boolean_t amd8111s_allocate_buffers(struct LayerPointers *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic boolean_t amd8111s_allocate_descriptors(struct LayerPointers *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void amd8111s_free_descriptors(struct LayerPointers *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic boolean_t amd8111s_alloc_dma_ringbuf(struct LayerPointers *,
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void amd8111s_free_dma_ringbuf(struct amd8111s_dma_ringbuf *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void amd8111s_log(struct LayerPointers *adapter, int level,
75ab5f91d942eea4138efe4799ca0589870c3899lh char *fmt, ...);
75ab5f91d942eea4138efe4799ca0589870c3899lh 0, /* devo_refcnt */
75ab5f91d942eea4138efe4799ca0589870c3899lh &mod_driverops, /* Type of module. This one is a driver */
75ab5f91d942eea4138efe4799ca0589870c3899lh ident, /* short description */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Global Variables
75ab5f91d942eea4138efe4799ca0589870c3899lh/* PIO access attributes for registers */
75ab5f91d942eea4138efe4799ca0589870c3899lh#define AMD8111S_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL)
75ab5f91d942eea4138efe4799ca0589870c3899lh * Standard Driver Load Entry Point
75ab5f91d942eea4138efe4799ca0589870c3899lh * It will be called at load time of driver.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Standard Driver Entry Point for Query.
75ab5f91d942eea4138efe4799ca0589870c3899lh * It will be called at any time to get Driver info.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Standard Driver Entry Point for Unload.
75ab5f91d942eea4138efe4799ca0589870c3899lh * It will be called at unload time of driver.
75ab5f91d942eea4138efe4799ca0589870c3899lh/* Adjust Interrupt Coalescing Register to coalesce interrupts */
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh * Loopback Support
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_set_loop_mode(struct LayerPointers *adapter, uint32_t mode)
75ab5f91d942eea4138efe4799ca0589870c3899lh * If the mode isn't being changed, there's nothing to do ...
75ab5f91d942eea4138efe4799ca0589870c3899lh * Validate the requested mode and prepare a suitable message
75ab5f91d942eea4138efe4799ca0589870c3899lh * to explain the link down/up cycle that the change will
75ab5f91d942eea4138efe4799ca0589870c3899lh * probably induce ...
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (mode) {
75ab5f91d942eea4138efe4799ca0589870c3899lh if (adapter->pOdl->loopback_mode == AMD8111S_LB_INTERNAL_MAC) {
75ab5f91d942eea4138efe4799ca0589870c3899lh cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_EXTERNAL_100");
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Tell GLD the state of the physical link. */
75ab5f91d942eea4138efe4799ca0589870c3899lh cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_EXTERNAL_10");
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Tell GLD the state of the physical link. */
75ab5f91d942eea4138efe4799ca0589870c3899lh cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_INTERNAL_MAC");
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable Port Manager */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Tell GLD the state of the physical link. */
75ab5f91d942eea4138efe4799ca0589870c3899lh * All OK; tell the caller to reprogram
75ab5f91d942eea4138efe4799ca0589870c3899lh * the PHY and/or MAC for the new mode ...
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_loopback_ioctl(struct LayerPointers *adapter, struct iocblk *iocp,
75ab5f91d942eea4138efe4799ca0589870c3899lh * Validate format of ioctl
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (cmd) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* NOTREACHED */
75ab5f91d942eea4138efe4799ca0589870c3899lh "wrong LB_GET_INFO_SIZE size");
75ab5f91d942eea4138efe4799ca0589870c3899lh "Wrong LB_GET_INFO size");
75ab5f91d942eea4138efe4799ca0589870c3899lh "Wrong LB_GET_MODE size");
75ab5f91d942eea4138efe4799ca0589870c3899lh "Wrong LB_SET_MODE size");
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh * Decide how to reply
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (status) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Error, reply with a NAK and EINVAL or the specified error
75ab5f91d942eea4138efe4799ca0589870c3899lh * OK, reply already sent
75ab5f91d942eea4138efe4799ca0589870c3899lh * OK, reply with an ACK
75ab5f91d942eea4138efe4799ca0589870c3899lh * OK, send prepared reply as ACK or NAK
75ab5f91d942eea4138efe4799ca0589870c3899lh * Copy one packet from dma memory to mblk. Inc dma descriptor pointer.
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_recv_copy(struct LayerPointers *pLayerPointers, mblk_t **last_mp)
75ab5f91d942eea4138efe4799ca0589870c3899lh struct amd8111s_statistics *statistics = &pOdl->statistics;
75ab5f91d942eea4138efe4799ca0589870c3899lh * If the frame is received with errors, then set MCNT
75ab5f91d942eea4138efe4799ca0589870c3899lh * of that pkt in ReceiveArray to 0. This packet would
75ab5f91d942eea4138efe4799ca0589870c3899lh * be discarded later and not indicated to OS.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Length of incoming packet */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Copy from virtual address of incoming packet */
75ab5f91d942eea4138efe4799ca0589870c3899lh bcopy((long *)*(pNonphysical->RxBufDescQRead->USpaceMap),
75ab5f91d942eea4138efe4799ca0589870c3899lh * Get the received packets from NIC card and send them to GLD.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh * Print message in release-version driver.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_log(struct LayerPointers *adapter, int level, char *fmt, ...)
75ab5f91d942eea4138efe4799ca0589870c3899lh * To allocate & initilize all resources.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Called by amd8111s_attach().
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned long *pmem_req_array;
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned long *pmem_set_array;
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < MEM_REQ_MAX; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Initilize memory on lower layers
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Allocate Rx/Tx descriptors */
75ab5f91d942eea4138efe4799ca0589870c3899lh if (amd8111s_allocate_descriptors(pLayerPointers) != B_TRUE) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate Rx buffer for each Rx descriptor. Then call mil layer
75ab5f91d942eea4138efe4799ca0589870c3899lh * routine to fill physical address of Rx buffer into Rx descriptor.
75ab5f91d942eea4138efe4799ca0589870c3899lh if (amd8111s_allocate_buffers(pLayerPointers) == B_FALSE) {
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Free All memory allocated so far
75ab5f91d942eea4138efe4799ca0589870c3899lh while ((*pmem_req_array) && (pmem_req_array != pmem_set_array)) {
75ab5f91d942eea4138efe4799ca0589870c3899lh return (1);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (1);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate and initialize Tx/Rx descriptors
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_allocate_descriptors(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate Rx descriptors
75ab5f91d942eea4138efe4799ca0589870c3899lh if (ddi_dma_alloc_handle(devinfo, &pcn_desc_dma_attr_t, DDI_DMA_SLEEP,
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_alloc_handle for Rx desc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh length = sizeof (struct rx_desc) * RX_RING_SIZE + ALIGNMENT;
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_mem_handle for Rx desc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_addr_bind_handle for Rx desc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Initialize Rx descriptors related variables */
75ab5f91d942eea4138efe4799ca0589870c3899lh ((pOdl->rx_desc_dma_cookie.dmac_laddress + ALIGNMENT) & ~ALIGNMENT);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate Tx descriptors
75ab5f91d942eea4138efe4799ca0589870c3899lh if (ddi_dma_alloc_handle(devinfo, &pcn_desc_dma_attr_t, DDI_DMA_SLEEP,
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_alloc_handle for Tx desc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh length = sizeof (struct tx_desc) * TX_RING_SIZE + ALIGNMENT;
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_mem_handle for Tx desc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_addr_bind_handle for Tx desc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Set the DMA area to all zeros */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Initialize Tx descriptors related variables */
75ab5f91d942eea4138efe4799ca0589870c3899lh pMil->pNonphysical->TxDescQEnd = &(pMil->Tx_desc[TX_RING_SIZE -1]);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Physical Addr of Tx_desc_original & Tx_desc */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Setting the reserved bits in the tx descriptors */
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < TX_RING_SIZE; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh pMil->pNonphysical->TxDescQWrite = pMil->pNonphysical->TxDescQStart;
75ab5f91d942eea4138efe4799ca0589870c3899lh * Free Tx/Rx descriptors
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_free_descriptors(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Free Rx descriptors */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Free Rx descriptors */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate Tx/Rx Ring buffer
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_alloc_dma_ringbuf(struct LayerPointers *pLayerPointers,
75ab5f91d942eea4138efe4799ca0589870c3899lh pRing->msg_buf = kmem_zalloc(sizeof (struct amd8111s_msgbuf) *
75ab5f91d942eea4138efe4799ca0589870c3899lh pRing->dma_cookie = kmem_zalloc(sizeof (ddi_dma_cookie_t) *
75ab5f91d942eea4138efe4799ca0589870c3899lh "kmem_zalloc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_alloc_handle failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_mem_alloc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_mem_alloc failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh "ddi_dma_addr_bind_handle failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh * Free Tx/Rx ring buffer
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_free_dma_ringbuf(struct amd8111s_dma_ringbuf *pRing)
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate all Tx buffer.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate a Rx buffer for each Rx descriptor. Then
75ab5f91d942eea4138efe4799ca0589870c3899lh * call mil routine to fill physical address of Rx
75ab5f91d942eea4138efe4799ca0589870c3899lh * buffer into Rx descriptors
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_allocate_buffers(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate rx Buffers
75ab5f91d942eea4138efe4799ca0589870c3899lh if (amd8111s_alloc_dma_ringbuf(pLayerPointers, &pOdl->rx_buf,
75ab5f91d942eea4138efe4799ca0589870c3899lh "amd8111s_alloc_dma_ringbuf for tx failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate Tx buffers
75ab5f91d942eea4138efe4799ca0589870c3899lh if (amd8111s_alloc_dma_ringbuf(pLayerPointers, &pOdl->tx_buf,
75ab5f91d942eea4138efe4799ca0589870c3899lh "amd8111s_alloc_dma_ringbuf for tx failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh * Initilize the mil Queues
75ab5f91d942eea4138efe4799ca0589870c3899lh "amd8111s_allocate_buffers failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh * Free all Rx/Tx buffer
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_free_buffers(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Free Tx buffers */
75ab5f91d942eea4138efe4799ca0589870c3899lh amd8111s_free_dma_ringbuf(&pLayerPointers->pOdl->tx_buf);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Free Rx Buffers */
75ab5f91d942eea4138efe4799ca0589870c3899lh amd8111s_free_dma_ringbuf(&pLayerPointers->pOdl->rx_buf);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Try to recycle all the descriptors and Tx buffers
75ab5f91d942eea4138efe4799ca0589870c3899lh * which are already freed by hardware.
75ab5f91d942eea4138efe4799ca0589870c3899lh pNonphysical->TxDescQRead != pNonphysical->TxDescQWrite) {
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pNonphysical->TxDescQRead > pNonphysical->TxDescQEnd) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Get packets in the Tx buffer, then copy them to the send buffer.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Trigger hardware to send out packets.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_send_serial(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* to verify if it needs to recycle the tx Buf */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Fill packet length */
75ab5f91d942eea4138efe4799ca0589870c3899lh pNonphysical->TxDescQWrite->Tx_BCNT = (uint16_t)pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Fill physical buffer address */
75ab5f91d942eea4138efe4799ca0589870c3899lh pNonphysical->TxDescQWrite->Tx_Base_Addr = (unsigned int)
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pNonphysical->TxDescQWrite > pNonphysical->TxDescQEnd) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Call mdlTransmit to send the pkt out on the network */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Softintr entrance. try to send out packets in the Tx buffer.
75ab5f91d942eea4138efe4799ca0589870c3899lh * If reschedule is True, call mac_tx_update to re-enable the
75ab5f91d942eea4138efe4799ca0589870c3899lh * transmit
75ab5f91d942eea4138efe4799ca0589870c3899lh * Get a Tx buffer
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic struct amd8111s_msgbuf *
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_send(struct LayerPointers *pLayerPointers, mblk_t *mp)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* alloc send buffer */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* copy packet to send buffer */
75ab5f91d942eea4138efe4799ca0589870c3899lh * (GLD Entry Point) Send the message block to lower layer
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Send fail */
75ab5f91d942eea4138efe4799ca0589870c3899lh return (mp);
75ab5f91d942eea4138efe4799ca0589870c3899lh * (GLD Entry Point) Interrupt Service Routine
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned int intrCauses;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Read the interrupt status from mdl */
75ab5f91d942eea4138efe4799ca0589870c3899lh if (intrCauses == 0) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Link status changed */
75ab5f91d942eea4138efe4799ca0589870c3899lh * RINT0: Receive Interrupt is set by the controller after the last
75ab5f91d942eea4138efe4799ca0589870c3899lh * descriptor of a receive frame for this ring has been updated by
75ab5f91d942eea4138efe4799ca0589870c3899lh * writing a 0 to the OWNership bit.
75ab5f91d942eea4138efe4799ca0589870c3899lh * TINT0: Transmit Interrupt is set by the controller after the OWN bit
75ab5f91d942eea4138efe4799ca0589870c3899lh * in the last descriptor of a transmit frame in this particular ring
75ab5f91d942eea4138efe4799ca0589870c3899lh * has been cleared to indicate the frame has been copied to the
75ab5f91d942eea4138efe4799ca0589870c3899lh * transmit FIFO.
75ab5f91d942eea4138efe4799ca0589870c3899lh * if desc ring is NULL and tx buf is not NULL, it should
75ab5f91d942eea4138efe4799ca0589870c3899lh * drain tx buffer
75ab5f91d942eea4138efe4799ca0589870c3899lh * To re-initilize data structures.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Reset all Tx/Rx queues and descriptors */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Send all pending tx packets
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh struct tx_desc *pTx_desc = adapter->pMil->pNonphysical->TxDescQStart;
75ab5f91d942eea4138efe4799ca0589870c3899lh int i, desc_count = 0;
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 30; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh while ((pTx_desc->Tx_OWN == 0) && (desc_count < TX_RING_SIZE)) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* This packet has been transmitted */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Wait 1 ms */
75ab5f91d942eea4138efe4799ca0589870c3899lh * (GLD Entry Point) To start card will be called at
75ab5f91d942eea4138efe4799ca0589870c3899lh * ifconfig plumb
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * (GLD Entry Point) To stop card will be called at
75ab5f91d942eea4138efe4799ca0589870c3899lh * ifconfig unplumb
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh struct LayerPointers *pLayerPointers = (struct LayerPointers *)arg;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Ensure send all pending tx packets */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Stop the controller and disable the controller interrupt
75ab5f91d942eea4138efe4799ca0589870c3899lh * To clean up all
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_free_resource(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Free Rx/Tx descriptors */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Free memory on lower layers */
75ab5f91d942eea4138efe4799ca0589870c3899lh * (GLD Enty pointer) To add/delete multi cast addresses
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_m_multicst(void *arg, boolean_t add, const uint8_t *addr)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Add a multicast entry */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Delete a multicast entry */
75ab5f91d942eea4138efe4799ca0589870c3899lh mdlDeleteMulticastAddress(pLayerPointers, (UCHAR *)addr);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * The size of MIB registers is only 32 bits. Dump them before one
75ab5f91d942eea4138efe4799ca0589870c3899lh * of them overflows.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh * Rx Counters
75ab5f91d942eea4138efe4799ca0589870c3899lh * Tx Counters
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear all MIB registers */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG16(pLayerPointers, pLayerPointers->pMdl->Mem_Address
75ab5f91d942eea4138efe4799ca0589870c3899lh * (GLD Entry Point) set/unset promiscus mode
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * (Gld Entry point) Changes the Mac address of card
75ab5f91d942eea4138efe4799ca0589870c3899lh mdlSetMacAddress(pLayerPointers, (unsigned char *)macaddr);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Reset the card
75ab5f91d942eea4138efe4799ca0589870c3899lh * attach(9E) -- Attach a device to the system
75ab5f91d942eea4138efe4799ca0589870c3899lh * Called once for each board after successfully probed.
75ab5f91d942eea4138efe4799ca0589870c3899lh * a. creating minor device node for the instance.
75ab5f91d942eea4138efe4799ca0589870c3899lh * b. allocate & Initilize four layers (call odlInit)
75ab5f91d942eea4138efe4799ca0589870c3899lh * c. get MAC address
75ab5f91d942eea4138efe4799ca0589870c3899lh * d. initilize pLayerPointers to gld private pointer
75ab5f91d942eea4138efe4799ca0589870c3899lh * e. register with GLD
75ab5f91d942eea4138efe4799ca0589870c3899lh * if any action fails does clean up & returns DDI_FAILURE
75ab5f91d942eea4138efe4799ca0589870c3899lh * else retursn DDI_SUCCESS
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (cmd) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Get device instance number */
75ab5f91d942eea4138efe4799ca0589870c3899lh ddi_set_driver_private(devinfo, (caddr_t)pLayerPointers);
75ab5f91d942eea4138efe4799ca0589870c3899lh pOdl = (struct odl *)kmem_zalloc(sizeof (struct odl), KM_SLEEP);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Here, we only allocate memory for struct odl and initilize it.
75ab5f91d942eea4138efe4799ca0589870c3899lh * All other memory allocation & initilization will be done in odlInit
75ab5f91d942eea4138efe4799ca0589870c3899lh * later on this routine.
75ab5f91d942eea4138efe4799ca0589870c3899lh if (ddi_get_iblock_cookie(devinfo, 0, &pLayerPointers->pOdl->iblock)
75ab5f91d942eea4138efe4799ca0589870c3899lh "attach: get iblock cookies failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh rw_init(&pOdl->chip_lock, NULL, RW_DRIVER, (void *)pOdl->iblock);
75ab5f91d942eea4138efe4799ca0589870c3899lh mutex_init(&pOdl->mdlSendLock, "amd8111s Send Protection Lock",
75ab5f91d942eea4138efe4799ca0589870c3899lh mutex_init(&pOdl->mdlRcvLock, "amd8111s Rcv Protection Lock",
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Setup PCI space */
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pci_config_setup(devinfo, &pOdl->pci_handle) != DDI_SUCCESS) {
75ab5f91d942eea4138efe4799ca0589870c3899lh pOdl->vendor_id = pci_config_get16(*pci_handle, PCI_CONF_VENID);
75ab5f91d942eea4138efe4799ca0589870c3899lh pOdl->device_id = pci_config_get16(*pci_handle, PCI_CONF_DEVID);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Allocate and initialize all resource and map device registers.
75ab5f91d942eea4138efe4799ca0589870c3899lh * If failed, it returns a non-zero value.
75ab5f91d942eea4138efe4799ca0589870c3899lh pLayerPointers->attach_progress |= AMD8111S_ATTACH_RESOURCE;
75ab5f91d942eea4138efe4799ca0589870c3899lh dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
75ab5f91d942eea4138efe4799ca0589870c3899lh if (ddi_regs_map_setup(devinfo, 1, &addrp, 0, 4096, &dev_attr,
75ab5f91d942eea4138efe4799ca0589870c3899lh "attach: ddi_regs_map_setup failed");
75ab5f91d942eea4138efe4799ca0589870c3899lh pLayerPointers->pMdl->Mem_Address = (unsigned long)addrp;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Initialize HW */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Setup the interrupt
75ab5f91d942eea4138efe4799ca0589870c3899lh if (ddi_add_intr(devinfo, 0, &pOdl->iblock, 0, amd8111s_intr,
75ab5f91d942eea4138efe4799ca0589870c3899lh pLayerPointers->attach_progress |= AMD8111S_ATTACH_INTRADDED;
75ab5f91d942eea4138efe4799ca0589870c3899lh * Setup soft intr
75ab5f91d942eea4138efe4799ca0589870c3899lh if (ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &pOdl->drain_id,
75ab5f91d942eea4138efe4799ca0589870c3899lh pLayerPointers->attach_progress |= AMD8111S_ATTACH_RESCHED;
75ab5f91d942eea4138efe4799ca0589870c3899lh * Initilize the mac structure
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Get MAC address */
75ab5f91d942eea4138efe4799ca0589870c3899lh mdlGetMacAddress(pLayerPointers, (unsigned char *)pOdl->MacAddress);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 1518 - 14 (ether header) - 4 (CRC) */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Finally, we're ready to register ourselves with the MAC layer
75ab5f91d942eea4138efe4799ca0589870c3899lh * interface; if this succeeds, we're ready to start.
75ab5f91d942eea4138efe4799ca0589870c3899lh pLayerPointers->attach_progress |= AMD8111S_ATTACH_MACREGED;
75ab5f91d942eea4138efe4799ca0589870c3899lh * detach(9E) -- Detach a device from the system
75ab5f91d942eea4138efe4799ca0589870c3899lh * It is called for each device instance when the system is preparing to
75ab5f91d942eea4138efe4799ca0589870c3899lh * unload a dynamically unloadable driver.
75ab5f91d942eea4138efe4799ca0589870c3899lh * a. check if any driver buffers are held by OS.
75ab5f91d942eea4138efe4799ca0589870c3899lh * b. do clean up of all allocated memory if it is not in use by OS.
75ab5f91d942eea4138efe4799ca0589870c3899lh * c. un register with GLD
75ab5f91d942eea4138efe4799ca0589870c3899lh * d. return DDI_SUCCESS on succes full free & unregister
75ab5f91d942eea4138efe4799ca0589870c3899lh * else GLD_FAILURE
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (cmd) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Get the driver private (struct LayerPointers *) structure
75ab5f91d942eea4138efe4799ca0589870c3899lh if ((pLayerPointers = (struct LayerPointers *)ddi_get_driver_private
75ab5f91d942eea4138efe4799ca0589870c3899lhamd8111s_unattach(dev_info_t *devinfo, struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_MACREGED) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Unregister driver from the GLD interface */
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_INTRADDED) {
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_RESCHED) {
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_REGS) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Stop HW */
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_RESOURCE) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Free All memory allocated */
75ab5f91d942eea4138efe4799ca0589870c3899lh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_PCI) {
75ab5f91d942eea4138efe4799ca0589870c3899lh kmem_free(pLayerPointers, sizeof (struct LayerPointers));
75ab5f91d942eea4138efe4799ca0589870c3899lh * (GLD Entry Point)GLD will call this entry point perodicaly to
75ab5f91d942eea4138efe4799ca0589870c3899lh * get driver statistices.
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (stat) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Current Status
75ab5f91d942eea4138efe4799ca0589870c3899lh * Capabilities
75ab5f91d942eea4138efe4799ca0589870c3899lh * Rx Counters
75ab5f91d942eea4138efe4799ca0589870c3899lh * Tx Counters
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Memory Read Function Used by MDL to set card registers.
75ab5f91d942eea4138efe4799ca0589870c3899lhunsigned char
75ab5f91d942eea4138efe4799ca0589870c3899lh return (ddi_get8(pLayerPointers->pOdl->MemBasehandle, (uint8_t *)x));
75ab5f91d942eea4138efe4799ca0589870c3899lhWRITE_REG8(struct LayerPointers *pLayerPointers, long x, int y)
75ab5f91d942eea4138efe4799ca0589870c3899lh ddi_put8(pLayerPointers->pOdl->MemBasehandle, (uint8_t *)(x), y);
75ab5f91d942eea4138efe4799ca0589870c3899lhWRITE_REG16(struct LayerPointers *pLayerPointers, long x, int y)
75ab5f91d942eea4138efe4799ca0589870c3899lh ddi_put16(pLayerPointers->pOdl->MemBasehandle, (uint16_t *)(x), y);
75ab5f91d942eea4138efe4799ca0589870c3899lhWRITE_REG32(struct LayerPointers *pLayerPointers, long x, int y)
75ab5f91d942eea4138efe4799ca0589870c3899lh ddi_put32(pLayerPointers->pOdl->MemBasehandle, (uint32_t *)(x), y);
75ab5f91d942eea4138efe4799ca0589870c3899lhWRITE_REG64(struct LayerPointers *pLayerPointers, long x, char *y)
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {