amd8111s_hw.c revision 75ab5f91d942eea4138efe4799ca0589870c3899
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* + Redistributions of source code must retain the above copyright notice,
* + this list of conditions and the following disclaimer.
*
* + Redistributions in binary form must reproduce the above copyright
* + notice, this list of conditions and the following disclaimer in the
*
* + Neither the name of Advanced Micro Devices, Inc. nor the names of its
* + contributors may be used to endorse or promote products derived from
* + this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Compliance with Applicable Laws. Notice is hereby given that
* the software may be subject to restrictions on use, release,
* the laws and regulations of the United States or other
* countries ("Applicable Laws"), which include but are not
* limited to U.S. export control laws such as the Export
* Administration Regulations and national security controls as
* defined thereunder, as well as State Department controls under
* redistribute the software is conditioned upon compliance with
* all Applicable Laws, including U.S. export control laws
* regarding specifically designated persons, countries and
* nationals of countries subject to national security controls.
*/
#include "amd8111s_hw.h"
#include "amd8111s_main.h"
#pragma inline(mdlTransmit)
#pragma inline(mdlReceive)
#pragma inline(mdlReadInterrupt)
#pragma inline(mdlEnableInterrupt)
#pragma inline(mdlDisableInterrupt)
static void mdlEnableMagicPacketWakeUp(struct LayerPointers *);
/* PMR (Pattern Match RAM) */
static void mdlAddWakeUpPattern(struct LayerPointers *, unsigned char *,
unsigned char *, unsigned long, unsigned long, int *);
static void mdlRemoveWakeUpPattern(struct LayerPointers *, unsigned char *,
unsigned long, int *);
static int mdlMulticastBitMapping(struct LayerPointers *, unsigned char *, int);
static unsigned int mdlCalculateCRC(unsigned int, unsigned char *);
static void mdlChangeFilter(struct LayerPointers *, unsigned long *);
static void mdlReceiveBroadCast(struct LayerPointers *);
static void mdlDisableReceiveBroadCast(struct LayerPointers *);
static void mdlRequestResources(ULONG *);
/*
* Initialises the data used in Mdl.
*/
static void
{
/* Disable Rx and Tx. */
/* Set Interrupt Delay Parameters */
}
void
{
int iData = 0;
switch (type) {
case PHY_AUTO_NEGOTIATION: /* Auto Negotiation */
/* EN_PMGR: Disable the Port Manager */
drv_usecwait(100000);
/*
* Enable Autonegotiation the Phy now
* XPHYANE(eXternal PHY Auto Negotiation Enable)
*/
/* EN_PMGR: Enable the Port Manager */
drv_usecwait(500000);
break;
case PHY_FORCE_HD_100: /* 100Mbps HD */
/* Force 100 Mbps, half duplex */
drv_usecwait(500000);
break;
case PHY_FORCE_FD_100: /* 100Mbps FD */
/* Force 100 Mbps, full duplex */
drv_usecwait(500000);
break;
case PHY_FORCE_HD_10: /* 10 Mbps HD */
/* Disable the Port Manager */
drv_usecwait(500000);
break;
case PHY_FORCE_FD_10: /* 10Mbps FD */
drv_usecwait(500000);
break;
}
}
/*
* Clear HW configuration.
*/
static void
{
/*
* Before the network controller is ready for operation,
* several registers must be initialized.
*/
unsigned int data32;
int JumboFlag = JUMBO_DISABLED;
/* AUTOPOLL0 Register */
/* Clear RCV_RING_BASE_ADDR */
/* Clear XMT_RING_BASE_ADDR */
/* Clear CMD0 / CMD2 */
/* Enable Port Management */
/* Clear CMD7 */
/* Clear CTRL0/1 */
/* Clear DLY_INT_A/B */
/* Clear FLOW_CONTROL */
/* Clear INT0 */
/* Clear STVAL */
/* Clear INTEN0 */
/* Clear LADRF */
/* Clear LED0 */
/* Set RCV_RING_CFG */
/* SRAM_SIZE & SRAM_BOUNDARY register combined */
if (JumboFlag == JUMBO_ENABLED) {
0xc0010);
} else {
0x80010);
}
/* Clear XMT_RING0/1/2/3_LEN */
/* Clear XMT_RING_LIMIT */
}
unsigned int
{
unsigned int status;
unsigned int data;
do {
} while ((status & MIB_CMD_ACTIVE));
return (data);
}
/* Return 1 on success, return 0 on fail */
unsigned int
{
count = 0;
do {
count ++;
drv_usecwait(10);
if (count == PHY_MAX_RETRY) {
return (0);
}
do {
drv_usecwait(10);
count ++;
return (0);
}
return (1);
}
void
{
for (i = 1; i < 32; i++) {
continue;
continue;
return;
}
}
}
/* Return 1 on success, return 0 on fail */
unsigned int
{
count = 0;
do {
count ++;
drv_usecwait(10);
if (count == PHY_MAX_RETRY) {
return (0);
}
do {
drv_usecwait(10);
count ++;
return (0);
}
return (1);
}
/*
* To Send the packet.
*/
void
{
}
/*
* To Receive a packet.
*/
void
{
/*
* Receive Demand for ring 0, which when set causes the Descriptor
* Management Unit to access the Receive Descriptor Ring if it does
* not already own the next descriptor.
*/
}
/*
* Read the NIC interrupt.
*
* Returns:
* the value of interrupt causes register
*/
unsigned int
{
unsigned int nINT0;
/*
* INT0 identifies the source or sources of an interrupt. With the
* exception of INTR and INTPN, all bits in this register are "write
* 1 to clear" so that the CPU can clear the interrupt condition by
* reading the register and then writing back the same data that it
* read. Writing a 0 to a bit in this register has no effect.
*/
/* Read interrupt status */
/* Process all the INT event until INTR bit is clear. */
return (nINT0);
}
void
{
unsigned int ulData, i = 0;
int JumboFlag = JUMBO_DISABLED;
/*
* Stop the Card:
* First we make sure that the device is stopped and no
* more interrupts come out. Also some registers must be
* programmed with CSR0 STOP bit set.
*/
/*
* MAC Address Setup:
* MAC Physical Address register. All bits in this register are
* restored to default values when the RST pin is asserted.
*/
for (i = 0; i < ETH_LENGTH_OF_ADDRESS; i++) {
}
/* Set RCV_RING_CFG */
if (JumboFlag == JUMBO_ENABLED) {
} else {
/*
* APAD_XMT: Auto Pad Transmit. When set, APAD_XMT enables
* the automatic padding feature. Transmit frames are padded
* to extend them to 64 bytes including FCS.
*
* DXMTFCS: Disable Transmit CRC. When DXMTFCS is set to 1, no
* Transmit CRC is generated. DXMTFCS is overridden when
* ADD_FCS and ENP bits are set in the transmit descriptor.
*
* ASTRIP_RCV: Auto Strip Receive. When ASTRP_RCV is set to 1,
* the receiver automatically strips pad bytes from the
* received message by observing the value in the length field
* and by stripping excess bytes if this value is below the
* minimum data size (46 bytes).
*/
}
/* Transmit Start Point setting (csr80) */
ulData &= ~XMTSP_MASK;
/* Disable Prom */
/* Set the IPG value */
/* Disable Following Interrupts. */
TINTEN0 |
/* Enable Following Interrupt */
/* Base Address of Transmit Descriptor Ring 0. */
/* Base Address of Receive Descriptor Ring. */
/* The number of descriptors in Transmit Descriptor Ring 0 */
/*
* Receive Descriptor Ring Length. All bits in this register are
* restored to default values when the RST pin is asserted.
*/
}
/* Start the chip */
}
/*
* Perform the open oerations on the adapter.
*/
void
{
int i, sum;
/* Get Mac address */
sum = 0;
for (i = 0; i < 6; i++) {
}
if (sum == 0) {
for (i = 0; i < 6; i++) {
}
}
/* Initialize the hardware */
}
void
unsigned char *macAddress)
{
int i;
for (i = 0; i < 6; i++) {
}
}
void
unsigned char *macAddress)
{
int i;
/*
* MAC Address Setup:
* MAC Physical Address register. All bits in this register are
* restored to default values when the RST pin is asserted.
*/
for (i = 0; i < ETH_LENGTH_OF_ADDRESS; i++) {
}
}
/*
* This array is filled with the size of the memory required for
* allocating purposes.
*/
static void
{
/* 1) For mdl structure */
/* 2) For PMR PtrList array (PMR_ptrList) */
/* Size */
/* 3) For PMR Pattern List array (PatternList) */
/* Size */
/* 4) For pmr PatternLength array (PatternLength) */
/* Size */
/*
* 5) For the init_block (init_blk)
*/
*(++mem_req_array) = VIRTUAL;
*(++mem_req_array) = sizeof (struct init_block);
*(++mem_req_array) = 0;
}
/*
* Purpose :
* This array contains the details of the allocated memory. The
* pointers are taken from the respective locations in the array &
* assigned appropriately to the respective structures.
*
* Arguments :
* pLayerPointers
* Pointer to the adapter structure.
* pmem_set_array
* Pointer to the array that holds the data after required
* allocating memory.
*/
static void
{
/* 1) For mdl structure */
pmem_set_array++; /* Type */
pmem_set_array++; /* Size */
/*
* Default values that would be used if it does not enable
* enable dynamic ipg.
*/
/* 2) Set the pointers to the PMR Pointer List */
pmem_set_array++; /* Type */
pmem_set_array++; /* Size */
pmem_set_array++; /* Virtual Addr of PtrList */
/* 3) Set the pointers to the PMR Pattern List */
pmem_set_array++; /* Type */
pmem_set_array++; /* Size */
pmem_set_array++; /* Virtual Addr of PatternList */
/* 4) Set the pointers to the PMR Pattern Length */
pmem_set_array++; /* Type */
pmem_set_array++; /* Size */
pmem_set_array++; /* Virtual Addr of PatternLength */
/* 5) Set the pointers to the init block */
pmem_set_array++; /* Type */
pmem_set_array++; /* Size */
pmem_set_array++; /* Virtual Addr of init_block */
*pmem_set_array = 0;
}
/*
* Purpose:
* This array is filled with the size of the structure & its
* pointer for freeing purposes.
*
* Arguments:
* pLayerPointers
* Pointer to the adapter structure.
* mem_free_array
* Pointer to the array that holds the data required for
* freeing.
*/
static void
{
/* 1) For mdl structure */
/* 2) For ptr list */
*(++pmem_free_array) = sizeof (unsigned int)
/* 3) For pattern list */
/* Size */
/* 4) For pattern length */
*(++pmem_free_array) = sizeof (unsigned int)
/* 5) For init_blk structure */
/* Size */
*(++pmem_free_array) = sizeof (struct init_block);
*(++pmem_free_array) = 0;
}
void
{
/* Enable Receiver */
/* Enable Interrupt and Start processing descriptor, Rx and Tx */
}
/*
* Stops the chip.
*/
void
{
int nINT0;
/* Disable interrupt */
/* Clear interrupt status */
/*
* Setting the RUN bit enables the controller to start processing
* descriptors and transmitting and receiving packets. Clearing
* the RUN bit to 0 abruptly disables the transmitter, receiver, and
* descriptor processing logic, possibly while a frame is being
* transmitted or received.
* The act of changing the RUN bit from 1 to 0 causes the following
* bits to be reset to 0: TX_SPND, RX_SPND, TX_FAST_SPND, RX_FAST_SPND,
* RDMD, all TDMD bits, RINT, all TINT bits, MPINT, and SPNDINT.
*/
}
/*
* Enables the interrupt.
*/
void
{
/*
* Interrupt Enable Bit:
* This bit allows INTA to be asserted if any bit in the interrupt
* register is set. If INTREN is cleared to 0, INTA will not be
* asserted, regardless of the state of the interrupt register.
*/
}
#ifdef AMD8111S_DEBUG
static void
{
unsigned int nINT0;
/* Clear interrupt status */
}
#endif
/*
* Disables the interrupt.
*/
void
{
/* Disable interrupt */
}
/*
* Reads the link status
*/
int
{
unsigned int link_status = 0;
if ((link_status & LINK_STAT)) {
return (LINK_UP);
} else {
return (LINK_DOWN);
}
}
/*
* Purpose :
* Adds the wakeup pattern given by the upper layer.
*
* Arguments :
* pLayerPointers
* Pointer to the Adapter structure.
* PatternMask
* The mask for the pattern to be added.
* Pattern
* The Pattern to be added.
* InfoBuffer_MaskSize
* The mask size as specified in the Information Buffer.
* PatternSize
* The PatternSize as specified in the Information Buffer.
*/
static void
unsigned char *PatternMask, unsigned char *Pattern,
{
unsigned long MaskSize;
unsigned long ReqSize;
unsigned char Skip = 0;
unsigned int j;
*retval = -1;
return;
}
if (ReqSize >
*retval = -1;
return;
}
*retval = -1;
return;
}
i = pMdl->PatternList_FreeIndex;
if (flag) {
byteData = *PatternMask;
pMdl->PatternList[i++] =
flag = 0;
} else {
pMdl->PatternList[i++] = (unsigned int)
PatternMask++;
flag = 1;
}
count = 1;
while ((count < 5) && (i <
Pattern++;
count++;
}
}
/* Filling up the extra byte blocks in the row to 0. */
pMdl->PatternList[i] = 0;
/* Set the EOP bit for the last mask!!! */
for (j = 0; j < 8; j++) {
pMdl->tmpPtrArray[j] = 0;
}
/* Zeroing the skip value of all the pattern masks */
j = 0;
j += 5;
}
/*
* Scan the whole array & update the start offset of the pattern in the
* PMR and update the skip value.
*/
j = 0;
i = 0;
PatternOffset = 1;
Skip = 0;
PatternOffset ++;
if (SearchForStartOfPattern == 1) {
}
Skip = 0;
} else {
Skip++;
}
j += 5;
}
/* valid pattern.. so update the house keeping info. */
pMdl->TotalPatterns++;
*retval = 0;
}
/*
* Purpose:
* Removes the specified wakeup pattern.
*
* Arguments :
* pLayerPointers
* Pointer to the Adapter structure.
* Pattern
* The Pattern to be added.
* PatternSize
* The PatternSize as specified in the Information Buffer.
*/
static void
{
unsigned char tmpData;
unsigned long Data;
int PatternMismatch = 0;
unsigned int i, j;
unsigned char Skip = 0;
unsigned long tmpPtrArray[8];
int offset;
/* Find the pattern to be removed. */
if (pMdl->TotalPatterns == 0) {
*retval = -1;
return;
}
while (count--) {
PatternMismatch = 0;
index++;
PatternMismatch = 1;
continue;
}
if (!(i%5))
i++;
PatternMismatch = 1;
break;
}
Pattern++;
}
if (PatternMismatch == 0) {
i = StartIndex + ReqSize;
/* Pattern found remove it from the arrays */
while (i < pMdl->PatternList_FreeIndex) {
pMdl->PatternList[i];
i++;
StartIndex++;
}
(unsigned short)(StartIndex);
while (StartIndex < MAX_PATTERNS)
index ++;
}
index--;
while (index < MAX_ALLOWED_PATTERNS) {
index++;
}
break;
}
index++;
}
if (PatternMismatch) {
*retval = -1;
return;
}
for (j = 0; j < 8; j++) {
tmpPtrArray[j] = 0;
}
/* Zeroing the skip value of all the pattern masks */
j = 0;
while (j < (pMdl->PatternList_FreeIndex)) {
j += 5;
}
/*
* Scan the whole array & update the start offset of the pattern in the
* PMR and update the skip value.
*/
j = 0;
i = 0;
Skip = 0;
PatternOffset = 1;
while (j < (pMdl->PatternList_FreeIndex)) {
if (SearchForStartOfPattern == 1) {
tmpPtrArray[i++] = PatternOffset;
}
Skip = 0;
} else {
Skip++;
}
j += 5;
}
/* Write back the arrays to the PMR & lock the pmr */
/* Write the data & ctrl patterns from the array to the PMR */
i = 0;
offset = 2;
while (i < MAX_PATTERNS) {
if (pMdl->PatternList[i] != 0) {
pMdl->PatternList[i];
offset++;
if (offset >= 64) {
/* PMR is full !!!! */
*retval = -1;
return;
}
}
i += 5;
}
/* Valid pattern.. so update the house keeping info. */
pMdl->TotalPatterns--;
/* Update the pointer in the PMR */
pMdl->PatternEnableBit = 0;
for (i = 0; i < pMdl->TotalPatterns; i++) {
}
switch (pMdl->TotalPatterns) {
case 8 :
/* FALLTHROUGH */
case 7 :
/* FALLTHROUGH */
case 6 :
/* FALLTHROUGH */
case 5 :
/* FALLTHROUGH */
case 4 :
/* FALLTHROUGH */
case 3 :
/* FALLTHROUGH */
case 2 :
/* FALLTHROUGH */
case 1 :
Data1 = (unsigned short)tmpPtrArray[0];
break;
}
/* Updating the pointers 1,2,3 & 4 */
/* Updating the pointers 4,5,6 & 7 */
/* Unlock the PMR */
*retval = 0;
}
/*
* Checks the control register for the speed and the type of the
* network connection.
*/
void
{
unsigned long ulData;
switch (ulData & SPEED_MASK) {
case SPEED_100Mbps:
break;
case SPEED_10Mbps:
break;
default:
break;
}
} else {
}
}
void
{
unsigned long *Ptr;
unsigned char *MulticastArray;
unsigned char *Pattern, *PatternMask;
unsigned int InfoBuffer_MaskSize, PatternSize;
int *retval;
int NumberOfAddress, i;
unsigned int j, CRCValue = 0;
unsigned char HashCode = 0, FilterByte = 0;
int BitMapIndex = 0;
while (*Ptr) {
switch (*Ptr) {
case DISABLE_BROADCAST:
break;
case ENABLE_BROADCAST:
break;
case ENABLE_ALL_MULTICAST:
for (i = 0; i < 8; i++) {
}
(unsigned long)pLayerPointers->pMdl
->Mem_Address + LADRF1,
break;
case DISABLE_ALL_MULTICAST:
for (i = 0; i < 8; i++) {
->LADRF[i] =
}
}
+ LADRF1,
break;
case ADD_MULTICAST:
NumberOfAddress = *(++Ptr);
MulticastArray = (unsigned char *)(*(++Ptr));
break;
case ENABLE_MULTICAST:
for (i = 0; i < 8; i++) {
}
+ LADRF1,
break;
case DISABLE_MULTICAST:
for (i = 0; i < 8; i++) {
}
for (BitMapIndex = 0; BitMapIndex <
[BitMapIndex] = 0;
+ LADRF1,
break;
case ADD_WAKE_UP_PATTERN:
PatternMask = (unsigned char *)(*(++Ptr));
InfoBuffer_MaskSize = (*(++Ptr));
PatternSize = (*(++Ptr));
retval);
break;
case REMOVE_WAKE_UP_PATTERN:
PatternSize = *(++Ptr);
retval);
break;
break;
case SET_SINGLE_MULTICAST:
NumberOfAddress = *(++Ptr);
MulticastArray = (unsigned char *)(*(++Ptr));
for (i = 0; i < 8; i++) {
}
for (j = 0; j < 6; j++) {
(((unsigned char)CRCValue >> j) & 0x01);
}
/*
* Bits 3-5 of HashCode point to byte in address
* filter.
* Bits 0-2 point to bit within that byte.
*/
break;
case UNSET_SINGLE_MULTICAST:
NumberOfAddress = *(++Ptr);
MulticastArray = (unsigned char *)(*(++Ptr));
for (i = 0; i < 8; i++) {
}
for (j = 0; j < 6; j++) {
(((unsigned char)CRCValue >> j) & 0x01));
}
/*
* Bits 3-5 of HashCode point to byte in address
* filter.
* Bits 0-2 point to bit within that byte.
*/
break;
default:
break;
}
Ptr++;
}
}
void
int NumberOfAddress, unsigned char *MulticastAddresses)
{
unsigned int j, CRCValue;
unsigned char HashCode, FilterByte;
int i;
for (i = 0; i < 8; i++) {
}
for (i = 0; i < NumberOfAddress; i++) {
HashCode = 0;
/* Calculate CRC value */
for (j = 0; j < 6; j++) {
(((unsigned char)CRCValue >> j) & 0x01);
}
/* Bits 3-5 of HashCode point to byte in address filter. */
/* Bits 0-2 point to bit within that byte. */
}
}
/* Receive all packets */
void
{
/*
* Writable N == Can Be Written only when device is not running
* (RUN == 0)
*/
}
/* Stop Receiving all packets */
void
{
/*
* Writable N == Can Be Written only when device is not running
* (RUN == 0)
*/
PROM);
}
/*
* Disable Receive Broadcast. When set, disables the controller from receiving
* broadcast messages. Used for protocols that do not support broadcast
* addressing, except as a function of multicast.
* DRCVBC is cleared by activation of H_RESET (broadcast messages will be
* received) and is unaffected by the clearing of the RUN bit.
*/
static void
{
}
static void
{
}
static void
{
}
/*
* can map to same bit in the filter matrix, we should maintain the count for
* # of M/C addresses associated with each bit. Only when the bit<->count
* reduce the count associated with each bit and return.
*/
static int
unsigned char *MulticastAddress, int FLAG)
{
unsigned char HashCode, FilterByte;
int j = 0, BitMapIndex = 0;
unsigned int CRCValue = 0;
HashCode = 0;
/* Calculate the Bit Map location for the given Address */
for (j = 0; j < 6; j++) {
(((unsigned char)CRCValue >> j) & 0x01);
}
/*
* Bits 3-5 of HashCode point to byte in address filter.
* Bits 0-2 point to bit within that byte.
*/
if (FLAG == DELETE_MULTICAST) {
[BitMapIndex] == 0)) {
return (0);
} else {
return (-1);
}
}
if (FLAG == ADD_MULTICAST) {
if (pLayerPointers->pMdl
->MulticastBitMapArray[BitMapIndex] > 0) {
return (-1);
} else if (pLayerPointers->pMdl
->MulticastBitMapArray[BitMapIndex] == 0) {
return (0);
}
}
return (0);
}
/*
* Set Interrupt Coalescing registers:
* To reduce the host CPU interrupt service overhead the network
* controller can be programmed to postpone the interrupt to the host
* CPU until either a programmable number of receive or transmit
* interrupt events have occurred or a programmable amount of time has
* elapsed since the first interrupt event occurred.
*/
void
{
unsigned int timeout, event_count;
if (on) {
/* Set Rx Interrupt Coalescing */
event_count = 0;
if (timeout > 0x7ff) {
timeout = 0x7ff;
}
if (event_count > 0x1f) {
event_count = 0x1f;
}
} else {
/* Disable Software Timer Interrupt */
STINTEN);
}
}
void
{
}
/* Reset all Tx descriptors and Tx buffers */
void
{
int i;
/* Clean all Tx descriptors */
for (i = 0; i < TX_RING_SIZE; i++) {
}
/* Re-init Tx Buffers */
}
/*
* Initialises the data used in Mil.
*/
void
{
}
/*
* Purpose :
* Initialises the RxBufDescQ with the packet pointer and physical
* address filled in the FreeQ.
*
* Arguments :
* pLayerPointers
* Pointer to the Adapter structure.
*/
void
{
int i;
/* Initialize the adapter rx descriptor Q and rx buffer Q */
for (i = 0; i < pMil->RxRingSize; i++) {
}
}
/*
* Purpose :
* This array is filled with the size of the structure & its
* pointer for freeing purposes.
*
* Arguments :
* pLayerPointers
* Pointer to the adapter structure.
* mem_free_array
* Pointer to the array that holds the data required
* for freeing.
*/
void
{
/* 1) For mil structure (pLayerPointers->pMil) */
/* Type */
*(mem_free_array) = VIRTUAL;
/* Size */
*(++mem_free_array) = sizeof (struct mil);
/* VA */
/* 2) For USpaceMapArray queue */
/* Type */
*(++mem_free_array) = VIRTUAL;
/* Size */
sizeof (unsigned long);
/* VA */
/* 3) For non_physical structure */
/* Type */
*(++mem_free_array) = VIRTUAL;
/* Size */
*(++mem_free_array) = sizeof (struct nonphysical);
/* VA */
/*
* 4~6) For four allocation are for abstracting the Rx_Descritor ring
*/
/* 4) Type */
*(++mem_free_array) = VIRTUAL;
/* Size */
*(++mem_free_array) = sizeof (struct Rx_Buf_Desc);
/* VA */
*(++mem_free_array) =
/* 5) Type */
*(++mem_free_array) = VIRTUAL;
/* Size */
*(++mem_free_array) = sizeof (struct Rx_Buf_Desc);
/* VA */
*(++mem_free_array) =
/* 6) Type */
*(++mem_free_array) = VIRTUAL;
/* Size */
*(++mem_free_array) = sizeof (struct Rx_Buf_Desc);
/* VA */
*(++mem_free_array) =
*(++mem_free_array) = 0;
}
/*
* Purpose :
* This array is filled with the size of the memory required for
* allocating purposes.
*
* Arguments :
* pLayerPointers
* Pointer to the adapter structure.
* mem_req_array
* Pointer to the array that holds the data required for
* allocating memory.
*/
void
{
int RxRingSize;
/* 1) For mil structure (pLayerPointers->pMil) */
/* Type */
*mem_req_array = VIRTUAL;
/* Size */
*(++mem_req_array) = sizeof (struct mil);
/* 2) For USpaceMapArray queue (pLayerPointers->pMil->USpaceMapArray) */
/* Type */
*(++mem_req_array) = VIRTUAL;
/* Size */
*(++mem_req_array) = RxRingSize * sizeof (unsigned long);
/* 3) For pNonphysical structure */
/* Type */
*(++mem_req_array) = VIRTUAL;
/* Size */
*(++mem_req_array) = sizeof (struct nonphysical);
/*
* 4~6) For four allocation are for abstracting the Rx_Descritor ring
*/
/* 4) Type */
*(++mem_req_array) = VIRTUAL;
/* Size */
*(++mem_req_array) = sizeof (struct Rx_Buf_Desc);
/* 5) Type */
*(++mem_req_array) = VIRTUAL;
/* Size */
*(++mem_req_array) = sizeof (struct Rx_Buf_Desc);
/* 6) Type */
*(++mem_req_array) = VIRTUAL;
/* Size */
*(++mem_req_array) = sizeof (struct Rx_Buf_Desc);
*(++mem_req_array) = 0;
}
/*
* Purpose :
* This array contains the details of the allocated memory. The
* pointers are taken from the respective locations in the array
* & assigne appropriately to the respective structures.
*
* Arguments :
* pLayerPointers
* Pointer to the adapter structure.
* pmem_set_array
* Pointer to the array that holds the data after required
* allocating memory.
*/
void
{
int RxRingSize, TxRingSize;
int RxBufSize;
/* 1) Set the pointers to the mil pointers */
/* Type */
/* Size */
/* 2) Type */
/* Size */
/* 3) Set the pointers to the NonPhysical part */
/* Type */
/* Size */
/* Virtual Addr of NonPhysical */
pMil->pNonphysical =
(struct nonphysical *)(*pmem_set_array);
/*
* 4~6) Following four allocation are for abstracting the Rx_Descritor
* Ring.
*/
/* 4) Type */
/* Size */
/* Virtual Addr of Abstracted RxDesc */
(struct Rx_Buf_Desc *)(*pmem_set_array);
/* 5) Type */
/* Size */
/* Virtual Addr of Abstracted RxDesc */
(struct Rx_Buf_Desc *)(*pmem_set_array);
/* 6) Type */
/* Size */
/* Virtual Addr of Abstracted RxDesc */
(struct Rx_Buf_Desc *)(*pmem_set_array);
}
/*
* Purpose :
* This routine adds the Multicast addresses to the filter
*
* Arguments :
* pLayerPointers
* Pointer to Layer pointers structure.
* pucMulticastAddress
* Pointer to the array of multicast addresses
*/
void
{
unsigned long MODE[10];
unsigned long tmp1;
unsigned long tmp2;
ADD_MULTICAST) != 0)
return;
tmp1 = (unsigned long)pucMulticastAddress;
MODE[4] = 0;
}
/*
* Purpose :
* This routine deletes the Multicast addresses requested by OS.
*
* Arguments :
* pLayerPointers
* Pointer to Layer pointers structure.
* pucMulticastAddress
* Pointer to the array of multicast addresses
*/
void
{
unsigned long MODE[10];
unsigned long tmp;
DELETE_MULTICAST) != 0)
return;
MODE[0] = UNSET_SINGLE_MULTICAST;
tmp = (unsigned long)pucMulticastAddress;
MODE[4] = 0;
}
/*
* Purpose :
* Calculates the CRC value over the input number of bytes.
*
* Arguments :
* NumberOfBytes
* The number of bytes in the input.
* Input
* An input "string" to calculate a CRC over.
*/
static unsigned int
{
const unsigned int POLY = 0x04c11db7;
unsigned int CRCValue = 0xffffffff;
unsigned int CurrentBit, CurrentCRCHigh;
unsigned char CurrentByte;
for (; NumberOfBytes; NumberOfBytes--) {
CurrentByte = *Input;
Input++;
CRCValue <<= 1;
CRCValue |= 0x00000001;
}
CurrentByte >>= 1;
}
}
return (CRCValue);
}
void
{
VAL0 | RX_FAST_SPND);
}
void
{
}