75ab5f91d942eea4138efe4799ca0589870c3899lh * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Use is subject to license terms.
75ab5f91d942eea4138efe4799ca0589870c3899lh#pragma ident "%Z%%M% %I% %E% SMI"
75ab5f91d942eea4138efe4799ca0589870c3899lh * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Redistribution and use in source and binary forms, with or without
75ab5f91d942eea4138efe4799ca0589870c3899lh * modification, are permitted provided that the following conditions are met:
75ab5f91d942eea4138efe4799ca0589870c3899lh * + Redistributions of source code must retain the above copyright notice,
75ab5f91d942eea4138efe4799ca0589870c3899lh * + this list of conditions and the following disclaimer.
75ab5f91d942eea4138efe4799ca0589870c3899lh * + Redistributions in binary form must reproduce the above copyright
75ab5f91d942eea4138efe4799ca0589870c3899lh * + notice, this list of conditions and the following disclaimer in the
75ab5f91d942eea4138efe4799ca0589870c3899lh * + documentation and/or other materials provided with the distribution.
75ab5f91d942eea4138efe4799ca0589870c3899lh * + Neither the name of Advanced Micro Devices, Inc. nor the names of its
75ab5f91d942eea4138efe4799ca0589870c3899lh * + contributors may be used to endorse or promote products derived from
75ab5f91d942eea4138efe4799ca0589870c3899lh * + this software without specific prior written permission.
75ab5f91d942eea4138efe4799ca0589870c3899lh * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
75ab5f91d942eea4138efe4799ca0589870c3899lh * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
75ab5f91d942eea4138efe4799ca0589870c3899lh * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
75ab5f91d942eea4138efe4799ca0589870c3899lh * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
75ab5f91d942eea4138efe4799ca0589870c3899lh * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR
75ab5f91d942eea4138efe4799ca0589870c3899lh * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
75ab5f91d942eea4138efe4799ca0589870c3899lh * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75ab5f91d942eea4138efe4799ca0589870c3899lh * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
75ab5f91d942eea4138efe4799ca0589870c3899lh * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
75ab5f91d942eea4138efe4799ca0589870c3899lh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75ab5f91d942eea4138efe4799ca0589870c3899lh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
75ab5f91d942eea4138efe4799ca0589870c3899lh * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
75ab5f91d942eea4138efe4799ca0589870c3899lh * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Import/Export/Re-Export/Use/Release/Transfer Restrictions and
75ab5f91d942eea4138efe4799ca0589870c3899lh * Compliance with Applicable Laws. Notice is hereby given that
75ab5f91d942eea4138efe4799ca0589870c3899lh * the software may be subject to restrictions on use, release,
75ab5f91d942eea4138efe4799ca0589870c3899lh * transfer, importation, exportation and/or re-exportation under
75ab5f91d942eea4138efe4799ca0589870c3899lh * the laws and regulations of the United States or other
75ab5f91d942eea4138efe4799ca0589870c3899lh * countries ("Applicable Laws"), which include but are not
75ab5f91d942eea4138efe4799ca0589870c3899lh * limited to U.S. export control laws such as the Export
75ab5f91d942eea4138efe4799ca0589870c3899lh * Administration Regulations and national security controls as
75ab5f91d942eea4138efe4799ca0589870c3899lh * defined thereunder, as well as State Department controls under
75ab5f91d942eea4138efe4799ca0589870c3899lh * the U.S. Munitions List. Permission to use and/or
75ab5f91d942eea4138efe4799ca0589870c3899lh * redistribute the software is conditioned upon compliance with
75ab5f91d942eea4138efe4799ca0589870c3899lh * all Applicable Laws, including U.S. export control laws
75ab5f91d942eea4138efe4799ca0589870c3899lh * regarding specifically designated persons, countries and
75ab5f91d942eea4138efe4799ca0589870c3899lh * nationals of countries subject to national security controls.
75ab5f91d942eea4138efe4799ca0589870c3899lh#pragma inline(mdlTransmit)
75ab5f91d942eea4138efe4799ca0589870c3899lh#pragma inline(mdlReceive)
75ab5f91d942eea4138efe4799ca0589870c3899lh#pragma inline(mdlReadInterrupt)
75ab5f91d942eea4138efe4799ca0589870c3899lh#pragma inline(mdlEnableInterrupt)
75ab5f91d942eea4138efe4799ca0589870c3899lh#pragma inline(mdlDisableInterrupt)
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void mdlEnableMagicPacketWakeUp(struct LayerPointers *);
75ab5f91d942eea4138efe4799ca0589870c3899lh/* PMR (Pattern Match RAM) */
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void mdlAddWakeUpPattern(struct LayerPointers *, unsigned char *,
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned char *, unsigned long, unsigned long, int *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void mdlRemoveWakeUpPattern(struct LayerPointers *, unsigned char *,
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned long, int *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic int mdlMulticastBitMapping(struct LayerPointers *, unsigned char *, int);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic unsigned int mdlCalculateCRC(unsigned int, unsigned char *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void mdlChangeFilter(struct LayerPointers *, unsigned long *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void mdlDisableReceiveBroadCast(struct LayerPointers *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void mdlSetResources(struct LayerPointers *, ULONG *);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void mdlFreeResources(struct LayerPointers *, ULONG *);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Initialises the data used in Mdl.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable Rx and Tx. */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Set Interrupt Delay Parameters */
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlPHYAutoNegotiation(struct LayerPointers *pLayerPointers, unsigned int type)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* PHY auto negotiation or force speed/duplex */
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (type) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* EN_PMGR: Disable the Port Manager */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD3, EN_PMGR);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Enable Autonegotiation the Phy now
75ab5f91d942eea4138efe4799ca0589870c3899lh * XPHYANE(eXternal PHY Auto Negotiation Enable)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* EN_PMGR: Enable the Port Manager */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD3, EN_PMGR);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Force 100 Mbps, half duplex */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CTRL2, iData);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD3, EN_PMGR);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Force 100 Mbps, full duplex */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CTRL2, iData);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable the Port Manager */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD3, EN_PMGR);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CTRL2, iData);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD3, EN_PMGR);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CTRL2, iData);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Clear HW configuration.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh * Before the network controller is ready for operation,
75ab5f91d942eea4138efe4799ca0589870c3899lh * several registers must be initialized.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* AUTOPOLL0 Register */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG16(pLayerPointers, MemBaseAddress + AUTOPOLL0, 0x8101);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear RCV_RING_BASE_ADDR */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + RCV_RING_BASE_ADDR0, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + RCV_RING_BASE_ADDR1, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + RCV_RING_BASE_ADDR0, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + RCV_RING_BASE_ADDR2, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + RCV_RING_BASE_ADDR3, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear XMT_RING_BASE_ADDR */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_BASE_ADDR0, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_BASE_ADDR1, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_BASE_ADDR2, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_BASE_ADDR3, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear CMD0 / CMD2 */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + CMD0, 0x000F0F7F);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + CMD2, 0x3F7F3F7F);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Enable Port Management */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + CMD3, VAL1 | EN_PMGR);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear CMD7 */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + CMD7, 0x1B);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear CTRL0/1 */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + CTRL1, XMTSP_MASK);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear DLY_INT_A/B */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + DLY_INT_A, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + DLY_INT_B, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear FLOW_CONTROL */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + FLOW_CONTROL, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear INT0 */
75ab5f91d942eea4138efe4799ca0589870c3899lh data32 = READ_REG32(pLayerPointers, MemBaseAddress + INT0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + INT0, data32);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear STVAL */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear INTEN0 */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + INTEN0, 0x1F7F7F1F);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear LADRF */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + LADRF1 + 4, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear LED0 */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Set RCV_RING_CFG */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG16(pLayerPointers, MemBaseAddress + RCV_RING_CFG, 1);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* SRAM_SIZE & SRAM_BOUNDARY register combined */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear XMT_RING0/1/2/3_LEN */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_LEN0, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_LEN1, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_LEN2, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_LEN3, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear XMT_RING_LIMIT */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + XMT_RING_LIMIT, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG16(pLayerPointers, MemBaseAddress + MIB_ADDR, MIB_CLEAR);
75ab5f91d942eea4138efe4799ca0589870c3899lhunsigned int
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlReadMib(struct LayerPointers *pLayerPointers, char MIB_COUNTER)
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG16(pLayerPointers, mmio + MIB_ADDR, MIB_RD_CMD | MIB_COUNTER);
75ab5f91d942eea4138efe4799ca0589870c3899lh/* Return 1 on success, return 0 on fail */
75ab5f91d942eea4138efe4799ca0589870c3899lhunsigned int
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlReadPHY(struct LayerPointers *pLayerPointers, unsigned char phyid,
75ab5f91d942eea4138efe4799ca0589870c3899lh } while ((status & PHY_CMD_ACTIVE) & (count < PHY_MAX_RETRY));
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh data = ((regaddr & 0x1f) << 16) | ((phyid & 0x1f) << 21) | PHY_RD_CMD;
75ab5f91d942eea4138efe4799ca0589870c3899lh } while ((status & PHY_CMD_ACTIVE) & (count < PHY_MAX_RETRY));
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (1);
75ab5f91d942eea4138efe4799ca0589870c3899lh if (mdlReadPHY(pLayerPointers, i, MII_PHYSID1, &id1) == 0)
75ab5f91d942eea4138efe4799ca0589870c3899lh if (mdlReadPHY(pLayerPointers, i, MII_PHYSID2, &id2) == 0)
75ab5f91d942eea4138efe4799ca0589870c3899lh/* Return 1 on success, return 0 on fail */
75ab5f91d942eea4138efe4799ca0589870c3899lhunsigned int
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlWritePHY(struct LayerPointers *pLayerPointers, unsigned char phyid,
75ab5f91d942eea4138efe4799ca0589870c3899lh } while ((status & PHY_CMD_ACTIVE) & (count < PHY_MAX_RETRY));
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh data = ((regaddr & 0x1f) << 16) | ((phyid & 0x1f) << 21) |
75ab5f91d942eea4138efe4799ca0589870c3899lh } while ((status & PHY_CMD_ACTIVE) & (count < PHY_MAX_RETRY));
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (1);
75ab5f91d942eea4138efe4799ca0589870c3899lh * To Send the packet.
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD0,
75ab5f91d942eea4138efe4799ca0589870c3899lh * To Receive a packet.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Receive Demand for ring 0, which when set causes the Descriptor
75ab5f91d942eea4138efe4799ca0589870c3899lh * Management Unit to access the Receive Descriptor Ring if it does
75ab5f91d942eea4138efe4799ca0589870c3899lh * not already own the next descriptor.
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD0,
75ab5f91d942eea4138efe4799ca0589870c3899lh * Read the NIC interrupt.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Returns:
75ab5f91d942eea4138efe4799ca0589870c3899lh * the value of interrupt causes register
75ab5f91d942eea4138efe4799ca0589870c3899lhunsigned int
75ab5f91d942eea4138efe4799ca0589870c3899lh * INT0 identifies the source or sources of an interrupt. With the
75ab5f91d942eea4138efe4799ca0589870c3899lh * exception of INTR and INTPN, all bits in this register are "write
75ab5f91d942eea4138efe4799ca0589870c3899lh * 1 to clear" so that the CPU can clear the interrupt condition by
75ab5f91d942eea4138efe4799ca0589870c3899lh * reading the register and then writing back the same data that it
75ab5f91d942eea4138efe4799ca0589870c3899lh * read. Writing a 0 to a bit in this register has no effect.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Read interrupt status */
75ab5f91d942eea4138efe4799ca0589870c3899lh nINT0 = READ_REG32(pLayerPointers, pMdl->Mem_Address + INT0);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Process all the INT event until INTR bit is clear. */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INT0, nINT0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Stop the Card:
75ab5f91d942eea4138efe4799ca0589870c3899lh * First we make sure that the device is stopped and no
75ab5f91d942eea4138efe4799ca0589870c3899lh * more interrupts come out. Also some registers must be
75ab5f91d942eea4138efe4799ca0589870c3899lh * programmed with CSR0 STOP bit set.
75ab5f91d942eea4138efe4799ca0589870c3899lh * MAC Address Setup:
75ab5f91d942eea4138efe4799ca0589870c3899lh * MAC Physical Address register. All bits in this register are
75ab5f91d942eea4138efe4799ca0589870c3899lh * restored to default values when the RST pin is asserted.
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < ETH_LENGTH_OF_ADDRESS; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Set RCV_RING_CFG */
75ab5f91d942eea4138efe4799ca0589870c3899lh VAL0 | APAD_XMT | REX_RTRY | VAL1 | DXMTFCS | RPA | VAL2);
75ab5f91d942eea4138efe4799ca0589870c3899lh * APAD_XMT: Auto Pad Transmit. When set, APAD_XMT enables
75ab5f91d942eea4138efe4799ca0589870c3899lh * the automatic padding feature. Transmit frames are padded
75ab5f91d942eea4138efe4799ca0589870c3899lh * to extend them to 64 bytes including FCS.
75ab5f91d942eea4138efe4799ca0589870c3899lh * DXMTFCS: Disable Transmit CRC. When DXMTFCS is set to 1, no
75ab5f91d942eea4138efe4799ca0589870c3899lh * Transmit CRC is generated. DXMTFCS is overridden when
75ab5f91d942eea4138efe4799ca0589870c3899lh * ADD_FCS and ENP bits are set in the transmit descriptor.
75ab5f91d942eea4138efe4799ca0589870c3899lh * ASTRIP_RCV: Auto Strip Receive. When ASTRP_RCV is set to 1,
75ab5f91d942eea4138efe4799ca0589870c3899lh * the receiver automatically strips pad bytes from the
75ab5f91d942eea4138efe4799ca0589870c3899lh * received message by observing the value in the length field
75ab5f91d942eea4138efe4799ca0589870c3899lh * and by stripping excess bytes if this value is below the
75ab5f91d942eea4138efe4799ca0589870c3899lh * minimum data size (46 bytes).
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Transmit Start Point setting (csr80) */
75ab5f91d942eea4138efe4799ca0589870c3899lh ulData = READ_REG32(pLayerPointers, Mem_Address + CTRL1);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable Prom */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD2, PROM);
75ab5f91d942eea4138efe4799ca0589870c3899lh mdlPHYAutoNegotiation(pLayerPointers, pMdl->External_Phy);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Set the IPG value */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable Following Interrupts. */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Enable Following Interrupt */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Base Address of Transmit Descriptor Ring 0. */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + XMT_RING_BASE_ADDR0,
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Base Address of Receive Descriptor Ring. */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + RCV_RING_BASE_ADDR0,
75ab5f91d942eea4138efe4799ca0589870c3899lh /* The number of descriptors in Transmit Descriptor Ring 0 */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG16(pLayerPointers, pMdl->Mem_Address + XMT_RING_LEN0,
75ab5f91d942eea4138efe4799ca0589870c3899lh * Receive Descriptor Ring Length. All bits in this register are
75ab5f91d942eea4138efe4799ca0589870c3899lh * restored to default values when the RST pin is asserted.
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG16(pLayerPointers, pMdl->Mem_Address + RCV_RING_LEN0,
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Start the chip */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Perform the open oerations on the adapter.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Get Mac address */
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 6; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh if (sum == 0) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 6; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Initialize the hardware */
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned char *macAddress)
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 6; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned char *macAddress)
75ab5f91d942eea4138efe4799ca0589870c3899lh * MAC Address Setup:
75ab5f91d942eea4138efe4799ca0589870c3899lh * MAC Physical Address register. All bits in this register are
75ab5f91d942eea4138efe4799ca0589870c3899lh * restored to default values when the RST pin is asserted.
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < ETH_LENGTH_OF_ADDRESS; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * This array is filled with the size of the memory required for
75ab5f91d942eea4138efe4799ca0589870c3899lh * allocating purposes.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 1) For mdl structure */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 2) For PMR PtrList array (PMR_ptrList) */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++mem_req_array) = sizeof (unsigned int) * (MAX_ALLOWED_PATTERNS + 2);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 3) For PMR Pattern List array (PatternList) */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++mem_req_array) = sizeof (unsigned char) * (MAX_PATTERNS + 2);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 4) For pmr PatternLength array (PatternLength) */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++mem_req_array) = sizeof (unsigned int) * (MAX_ALLOWED_PATTERNS + 2);
75ab5f91d942eea4138efe4799ca0589870c3899lh * 5) For the init_block (init_blk)
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * This array contains the details of the allocated memory. The
75ab5f91d942eea4138efe4799ca0589870c3899lh * pointers are taken from the respective locations in the array &
75ab5f91d942eea4138efe4799ca0589870c3899lh * assigned appropriately to the respective structures.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * pmem_set_array
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the array that holds the data after required
75ab5f91d942eea4138efe4799ca0589870c3899lh * allocating memory.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlSetResources(struct LayerPointers *pLayerPointers, ULONG *pmem_set_array)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 1) For mdl structure */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Default values that would be used if it does not enable
75ab5f91d942eea4138efe4799ca0589870c3899lh * enable dynamic ipg.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 2) Set the pointers to the PMR Pointer List */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 3) Set the pointers to the PMR Pattern List */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 4) Set the pointers to the PMR Pattern Length */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 5) Set the pointers to the init block */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose:
75ab5f91d942eea4138efe4799ca0589870c3899lh * This array is filled with the size of the structure & its
75ab5f91d942eea4138efe4799ca0589870c3899lh * pointer for freeing purposes.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments:
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * mem_free_array
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the array that holds the data required for
75ab5f91d942eea4138efe4799ca0589870c3899lh * freeing.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlFreeResources(struct LayerPointers *pLayerPointers, ULONG *pmem_free_array)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 1) For mdl structure */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 2) For ptr list */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++pmem_free_array) = sizeof (unsigned int)
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++pmem_free_array) = (ULONG)pMdl->PMR_PtrList; /* VA */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 3) For pattern list */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++pmem_free_array) = sizeof (unsigned char) * (MAX_PATTERNS + 2);
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++pmem_free_array) = (ULONG)pMdl->PatternList; /* VA */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 4) For pattern length */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++pmem_free_array) = sizeof (unsigned int)
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++pmem_free_array) = (ULONG)pMdl->PatternLength; /* VA */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 5) For init_blk structure */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Enable Receiver */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD0,
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Enable Interrupt and Start processing descriptor, Rx and Tx */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD0,
75ab5f91d942eea4138efe4799ca0589870c3899lh * Stops the chip.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable interrupt */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD0, INTREN);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear interrupt status */
75ab5f91d942eea4138efe4799ca0589870c3899lh nINT0 = READ_REG32(pLayerPointers, pMdl->Mem_Address + INT0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INT0, nINT0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Setting the RUN bit enables the controller to start processing
75ab5f91d942eea4138efe4799ca0589870c3899lh * descriptors and transmitting and receiving packets. Clearing
75ab5f91d942eea4138efe4799ca0589870c3899lh * the RUN bit to 0 abruptly disables the transmitter, receiver, and
75ab5f91d942eea4138efe4799ca0589870c3899lh * descriptor processing logic, possibly while a frame is being
75ab5f91d942eea4138efe4799ca0589870c3899lh * transmitted or received.
75ab5f91d942eea4138efe4799ca0589870c3899lh * The act of changing the RUN bit from 1 to 0 causes the following
75ab5f91d942eea4138efe4799ca0589870c3899lh * bits to be reset to 0: TX_SPND, RX_SPND, TX_FAST_SPND, RX_FAST_SPND,
75ab5f91d942eea4138efe4799ca0589870c3899lh * RDMD, all TDMD bits, RINT, all TINT bits, MPINT, and SPNDINT.
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD0, RUN);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Enables the interrupt.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Interrupt Enable Bit:
75ab5f91d942eea4138efe4799ca0589870c3899lh * This bit allows INTA to be asserted if any bit in the interrupt
75ab5f91d942eea4138efe4799ca0589870c3899lh * register is set. If INTREN is cleared to 0, INTA will not be
75ab5f91d942eea4138efe4799ca0589870c3899lh * asserted, regardless of the state of the interrupt register.
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD0,
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clear interrupt status */
75ab5f91d942eea4138efe4799ca0589870c3899lh nINT0 = READ_REG32(pLayerPointers, pMdl->Mem_Address + INT0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + INT0, nINT0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Disables the interrupt.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable interrupt */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Reads the link status
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * Adds the wakeup pattern given by the upper layer.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the Adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * PatternMask
75ab5f91d942eea4138efe4799ca0589870c3899lh * The mask for the pattern to be added.
75ab5f91d942eea4138efe4799ca0589870c3899lh * The Pattern to be added.
75ab5f91d942eea4138efe4799ca0589870c3899lh * InfoBuffer_MaskSize
75ab5f91d942eea4138efe4799ca0589870c3899lh * The mask size as specified in the Information Buffer.
75ab5f91d942eea4138efe4799ca0589870c3899lh * PatternSize
75ab5f91d942eea4138efe4799ca0589870c3899lh * The PatternSize as specified in the Information Buffer.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned long InfoBuffer_MaskSize, unsigned long PatternSize, int *retval)
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned int j;
75ab5f91d942eea4138efe4799ca0589870c3899lh (unsigned long)(MAX_PATTERNS - pMdl->PatternList_FreeIndex)) {
75ab5f91d942eea4138efe4799ca0589870c3899lh if (InfoBuffer_MaskSize != PatternSize/8 + (PatternSize%8 ? 1 : 0)) {
75ab5f91d942eea4138efe4799ca0589870c3899lh pMdl->PatternLength[pMdl->TotalPatterns] = (unsigned int)PatternSize;
75ab5f91d942eea4138efe4799ca0589870c3899lh while (i < (pMdl->PatternList_FreeIndex + PatternSize + MaskSize)) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Filling up the extra byte blocks in the row to 0. */
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = (pMdl->PatternList_FreeIndex + PatternSize + MaskSize);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Set the EOP bit for the last mask!!! */
75ab5f91d942eea4138efe4799ca0589870c3899lh pMdl->PatternList[pMdl->PatternList_FreeIndex + ReqSize - 5] |= 0x80;
75ab5f91d942eea4138efe4799ca0589870c3899lh for (j = 0; j < 8; j++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Zeroing the skip value of all the pattern masks */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Scan the whole array & update the start offset of the pattern in the
75ab5f91d942eea4138efe4799ca0589870c3899lh * PMR and update the skip value.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* valid pattern.. so update the house keeping info. */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose:
75ab5f91d942eea4138efe4799ca0589870c3899lh * Removes the specified wakeup pattern.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the Adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * The Pattern to be added.
75ab5f91d942eea4138efe4799ca0589870c3899lh * PatternSize
75ab5f91d942eea4138efe4799ca0589870c3899lh * The PatternSize as specified in the Information Buffer.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlRemoveWakeUpPattern(struct LayerPointers *pLayerPointers,
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned char *Pattern, unsigned long PatternSize, int *retval)
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned short Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8;
75ab5f91d942eea4138efe4799ca0589870c3899lh unsigned int i, j;
75ab5f91d942eea4138efe4799ca0589870c3899lh Data1 = Data2 = Data3 = Data4 = Data5 = Data6 = Data7 = Data8 = 0;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Find the pattern to be removed. */
75ab5f91d942eea4138efe4799ca0589870c3899lh while (count--) {
75ab5f91d942eea4138efe4799ca0589870c3899lh if (!(i%5))
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Pattern found remove it from the arrays */
75ab5f91d942eea4138efe4799ca0589870c3899lh (unsigned short)(StartIndex);
75ab5f91d942eea4138efe4799ca0589870c3899lh for (j = 0; j < 8; j++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Zeroing the skip value of all the pattern masks */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Scan the whole array & update the start offset of the pattern in the
75ab5f91d942eea4138efe4799ca0589870c3899lh * PMR and update the skip value.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Write back the arrays to the PMR & lock the pmr */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address+CMD7, PMAT_MODE);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Write the data & ctrl patterns from the array to the PMR */
75ab5f91d942eea4138efe4799ca0589870c3899lh while (i < MAX_PATTERNS) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* PMR is full !!!! */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Valid pattern.. so update the house keeping info. */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Update the pointer in the PMR */
75ab5f91d942eea4138efe4799ca0589870c3899lh Data1 = Data2 = Data3 = Data4 = Data5 = Data6 = Data7 = Data8 = 0;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* FALLTHROUGH */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* FALLTHROUGH */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* FALLTHROUGH */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* FALLTHROUGH */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* FALLTHROUGH */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* FALLTHROUGH */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* FALLTHROUGH */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Updating the pointers 1,2,3 & 4 */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + PMAT1, Data);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + PMAT0, Data);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Updating the pointers 4,5,6 & 7 */
75ab5f91d942eea4138efe4799ca0589870c3899lh Data = (unsigned short)((unsigned)(pMdl->PatternEnableBit & 0xf0) >> 4);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + PMAT1, Data);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + PMAT0, Data);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Unlock the PMR */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pMdl->Mem_Address + CMD7, VAL0 | PMAT_MODE);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Checks the control register for the speed and the type of the
75ab5f91d942eea4138efe4799ca0589870c3899lh * network connection.
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlGetActiveMediaInfo(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh ulData = READ_REG32(pLayerPointers, pMdl->Mem_Address + STAT0);
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlChangeFilter(struct LayerPointers *pLayerPointers, unsigned long *ArrayPtr)
75ab5f91d942eea4138efe4799ca0589870c3899lh while (*Ptr) {
75ab5f91d942eea4138efe4799ca0589870c3899lh switch (*Ptr) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (j = 0; j < 6; j++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Bits 3-5 of HashCode point to byte in address
75ab5f91d942eea4138efe4799ca0589870c3899lh * Bits 0-2 point to bit within that byte.
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (j = 0; j < 6; j++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Bits 3-5 of HashCode point to byte in address
75ab5f91d942eea4138efe4799ca0589870c3899lh * Bits 0-2 point to bit within that byte.
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlAddMulticastAddresses(struct LayerPointers *pLayerPointers,
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < 8; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < NumberOfAddress; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Calculate CRC value */
75ab5f91d942eea4138efe4799ca0589870c3899lh for (j = 0; j < 6; j++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Bits 3-5 of HashCode point to byte in address filter. */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Bits 0-2 point to bit within that byte. */
75ab5f91d942eea4138efe4799ca0589870c3899lh/* Receive all packets */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Writable N == Can Be Written only when device is not running
75ab5f91d942eea4138efe4799ca0589870c3899lh * (RUN == 0)
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD2,
75ab5f91d942eea4138efe4799ca0589870c3899lh/* Stop Receiving all packets */
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlDisablePromiscuous(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh * Writable N == Can Be Written only when device is not running
75ab5f91d942eea4138efe4799ca0589870c3899lh * (RUN == 0)
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD2,
75ab5f91d942eea4138efe4799ca0589870c3899lh * Disable Receive Broadcast. When set, disables the controller from receiving
75ab5f91d942eea4138efe4799ca0589870c3899lh * broadcast messages. Used for protocols that do not support broadcast
75ab5f91d942eea4138efe4799ca0589870c3899lh * addressing, except as a function of multicast.
75ab5f91d942eea4138efe4799ca0589870c3899lh * DRCVBC is cleared by activation of H_RESET (broadcast messages will be
75ab5f91d942eea4138efe4799ca0589870c3899lh * received) and is unaffected by the clearing of the RUN bit.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lh MappedMemBaseAddress = pLayerPointers->pMdl->Mem_Address;
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MappedMemBaseAddress + CMD2, DRCVBC);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlDisableReceiveBroadCast(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh MappedMemBaseAddress = pLayerPointers->pMdl->Mem_Address;
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MappedMemBaseAddress + CMD2, VAL2 | DRCVBC);
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic void
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlEnableMagicPacketWakeUp(struct LayerPointers *pLayerPointers)
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD3,
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD7,
75ab5f91d942eea4138efe4799ca0589870c3899lh * BitMap for add/del the Multicast address Since more than one M/C address
75ab5f91d942eea4138efe4799ca0589870c3899lh * can map to same bit in the filter matrix, we should maintain the count for
75ab5f91d942eea4138efe4799ca0589870c3899lh * # of M/C addresses associated with each bit. Only when the bit<->count
75ab5f91d942eea4138efe4799ca0589870c3899lh * becomes zero, we should go ahead with changing/reseting the bit, else just
75ab5f91d942eea4138efe4799ca0589870c3899lh * reduce the count associated with each bit and return.
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlMulticastBitMapping(struct LayerPointers *pLayerPointers,
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Calculate the Bit Map location for the given Address */
75ab5f91d942eea4138efe4799ca0589870c3899lh CRCValue = mdlCalculateCRC(ETH_LENGTH_OF_ADDRESS, MulticastAddress);
75ab5f91d942eea4138efe4799ca0589870c3899lh for (j = 0; j < 6; j++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh * Bits 3-5 of HashCode point to byte in address filter.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Bits 0-2 point to bit within that byte.
75ab5f91d942eea4138efe4799ca0589870c3899lh if ((pLayerPointers->pMdl->MulticastBitMapArray[BitMapIndex]
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (-1);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (-1);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh return (0);
75ab5f91d942eea4138efe4799ca0589870c3899lh * Set Interrupt Coalescing registers:
75ab5f91d942eea4138efe4799ca0589870c3899lh * To reduce the host CPU interrupt service overhead the network
75ab5f91d942eea4138efe4799ca0589870c3899lh * controller can be programmed to postpone the interrupt to the host
75ab5f91d942eea4138efe4799ca0589870c3899lh * CPU until either a programmable number of receive or transmit
75ab5f91d942eea4138efe4799ca0589870c3899lh * interrupt events have occurred or a programmable amount of time has
75ab5f91d942eea4138efe4799ca0589870c3899lh * elapsed since the first interrupt event occurred.
75ab5f91d942eea4138efe4799ca0589870c3899lhSetIntrCoalesc(struct LayerPointers *pLayerPointers, boolean_t on)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Set Rx Interrupt Coalescing */
75ab5f91d942eea4138efe4799ca0589870c3899lh event_count |= pLayerPointers->pMdl->rx_intrcoalesc_events;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Disable Software Timer Interrupt */
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + DLY_INT_A, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, MemBaseAddress + DLY_INT_B, 0);
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address
75ab5f91d942eea4138efe4799ca0589870c3899lh/* Reset all Tx descriptors and Tx buffers */
75ab5f91d942eea4138efe4799ca0589870c3899lh struct nonphysical *pNonphysical = pLayerPointers->pMil->pNonphysical;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Clean all Tx descriptors */
75ab5f91d942eea4138efe4799ca0589870c3899lh for (i = 0; i < TX_RING_SIZE; i++) {
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Re-init Tx Buffers */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Initialises the data used in Mil.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * Initialises the RxBufDescQ with the packet pointer and physical
75ab5f91d942eea4138efe4799ca0589870c3899lh * address filled in the FreeQ.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the Adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh pNonphysical->RxBufDescQRead->descriptor = pMil->Rx_desc;
75ab5f91d942eea4138efe4799ca0589870c3899lh pNonphysical->RxBufDescQStart->descriptor = pMil->Rx_desc;
75ab5f91d942eea4138efe4799ca0589870c3899lh pNonphysical->RxBufDescQRead->USpaceMap = pMil->USpaceMapArray;
75ab5f91d942eea4138efe4799ca0589870c3899lh pNonphysical->RxBufDescQStart->USpaceMap = pMil->USpaceMapArray;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Initialize the adapter rx descriptor Q and rx buffer Q */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * This array is filled with the size of the structure & its
75ab5f91d942eea4138efe4799ca0589870c3899lh * pointer for freeing purposes.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * mem_free_array
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the array that holds the data required
75ab5f91d942eea4138efe4799ca0589870c3899lh * for freeing.
75ab5f91d942eea4138efe4799ca0589870c3899lhmilFreeResources(struct LayerPointers *pLayerPointers, ULONG *mem_free_array)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 1) For mil structure (pLayerPointers->pMil) */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 2) For USpaceMapArray queue */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh sizeof (unsigned long);
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++mem_free_array) = (ULONG)pLayerPointers->pMil->USpaceMapArray;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 3) For non_physical structure */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++mem_free_array) = (ULONG)pLayerPointers->pMil->pNonphysical;
75ab5f91d942eea4138efe4799ca0589870c3899lh * 4~6) For four allocation are for abstracting the Rx_Descritor ring
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 4) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh (ULONG)pLayerPointers->pMil->pNonphysical->RxBufDescQRead;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 5) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh (ULONG)pLayerPointers->pMil->pNonphysical->RxBufDescQStart;
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 6) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh (ULONG)pLayerPointers->pMil->pNonphysical->RxBufDescQEnd;
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * This array is filled with the size of the memory required for
75ab5f91d942eea4138efe4799ca0589870c3899lh * allocating purposes.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * mem_req_array
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the array that holds the data required for
75ab5f91d942eea4138efe4799ca0589870c3899lh * allocating memory.
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 1) For mil structure (pLayerPointers->pMil) */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 2) For USpaceMapArray queue (pLayerPointers->pMil->USpaceMapArray) */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh *(++mem_req_array) = RxRingSize * sizeof (unsigned long);
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 3) For pNonphysical structure */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh * 4~6) For four allocation are for abstracting the Rx_Descritor ring
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 4) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 5) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 6) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * This array contains the details of the allocated memory. The
75ab5f91d942eea4138efe4799ca0589870c3899lh * pointers are taken from the respective locations in the array
75ab5f91d942eea4138efe4799ca0589870c3899lh * & assigne appropriately to the respective structures.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the adapter structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * pmem_set_array
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the array that holds the data after required
75ab5f91d942eea4138efe4799ca0589870c3899lh * allocating memory.
75ab5f91d942eea4138efe4799ca0589870c3899lhmilSetResources(struct LayerPointers *pLayerPointers, ULONG *pmem_set_array)
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 1) Set the pointers to the mil pointers */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 2) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 3) Set the pointers to the NonPhysical part */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Virtual Addr of NonPhysical */
75ab5f91d942eea4138efe4799ca0589870c3899lh * 4~6) Following four allocation are for abstracting the Rx_Descritor
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 4) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Virtual Addr of Abstracted RxDesc */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 5) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Virtual Addr of Abstracted RxDesc */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* 6) Type */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Size */
75ab5f91d942eea4138efe4799ca0589870c3899lh /* Virtual Addr of Abstracted RxDesc */
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * This routine adds the Multicast addresses to the filter
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to Layer pointers structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * pucMulticastAddress
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the array of multicast addresses
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlAddMulticastAddress(struct LayerPointers *pLayerPointers,
75ab5f91d942eea4138efe4799ca0589870c3899lh if (mdlMulticastBitMapping(pLayerPointers, pucMulticastAddress,
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * This routine deletes the Multicast addresses requested by OS.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * pLayerPointers
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to Layer pointers structure.
75ab5f91d942eea4138efe4799ca0589870c3899lh * pucMulticastAddress
75ab5f91d942eea4138efe4799ca0589870c3899lh * Pointer to the array of multicast addresses
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlDeleteMulticastAddress(struct LayerPointers *pLayerPointers,
75ab5f91d942eea4138efe4799ca0589870c3899lh if (mdlMulticastBitMapping(pLayerPointers, pucMulticastAddress,
75ab5f91d942eea4138efe4799ca0589870c3899lh * Purpose :
75ab5f91d942eea4138efe4799ca0589870c3899lh * Calculates the CRC value over the input number of bytes.
75ab5f91d942eea4138efe4799ca0589870c3899lh * Arguments :
75ab5f91d942eea4138efe4799ca0589870c3899lh * NumberOfBytes
75ab5f91d942eea4138efe4799ca0589870c3899lh * The number of bytes in the input.
75ab5f91d942eea4138efe4799ca0589870c3899lh * An input "string" to calculate a CRC over.
75ab5f91d942eea4138efe4799ca0589870c3899lhstatic unsigned int
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlCalculateCRC(unsigned int NumberOfBytes, unsigned char *Input)
75ab5f91d942eea4138efe4799ca0589870c3899lh WRITE_REG32(pLayerPointers, pLayerPointers->pMdl->Mem_Address + CMD0,
75ab5f91d942eea4138efe4799ca0589870c3899lhmdlRxFastSuspendClear(struct LayerPointers *pLayerPointers)