agptarget.c revision 193974072f41a843678abf5f61979c748687e66b
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
int agptarget_debug_var = 0;
typedef struct agp_target_softstate {
/* The offset of the ACAPID register */
int tsoft_gms_off; /* GMS offset in config */
/*
* To get the pre-allocated graphics mem size using Graphics Mode Select
* (GMS) value.
*/
typedef struct gms_mode {
int *gm_vec; /* modes array */
} gms_mode_t;
static void *agptarget_glob_soft_handle;
/*
* The AMD8151 bridge is the only supported 64 bit hardware
*/
static int
{
}
/*
* Check if it is an intel bridge
*/
static int
{
}
/*
* agp_target_cap_find()
*
* Description:
* This function searches the linked capability list to find the offset
* of the AGP capability register. When it was not found, return 0.
* This works for standard AGP chipsets, but not for some Intel chipsets,
* these chipsets even if AGP is supported. So the offset of acapid
* should be set manually in thoses cases.
*
* Arguments:
* pci_handle ddi acc handle of pci config
*
* Returns:
* 0 No capability pointer register found
* nexcap The AGP capability pointer register offset
*/
static off_t
{
/* Check if this device supports the capability pointer */
if (!value)
return (0);
/* Get the offset of the first capability pointer from CAPPTR */
/* Check the AGP capability from the first capability pointer */
while (nextcap) {
/*
* AGP3.0 rev1.0 127 the capid was assigned by the PCI SIG,
* 845 data sheet page 69
*/
if ((ncapid & PCI_CONF_CAPID_MASK) ==
AGP_CAP_ID) /* The AGP cap was found */
break;
}
return (nextcap);
}
/*
* agp_target_get_aperbase()
*
* Description:
* This function gets the AGP aperture base address from the AGP target
* register, the AGP aperture base register was programmed by the BIOS.
*
* Arguments:
* softstate driver soft state pointer
*
* Returns:
* aper_base AGP aperture base address
*
* Notes:
* If a 64bit bridge device is available, the AGP aperture base address
* can be 64 bit.
*/
static uint64_t
{
if (is_intel_br(softstate)) {
} else if (is_64bit_aper(softstate)) {
/* 32-bit or 64-bit aperbase base pointer */
if ((aper_base & AGP_APER_TYPE_MASK) == 0)
else
}
return (aper_base);
}
/*
* agp_target_get_apsize()
*
* Description:
* This function gets the AGP aperture size by reading the AGP aperture
* size register.
* Arguments:
* softstate driver soft state pointer
*
* Return:
* size The AGP aperture size in megabytes
* 0 an unexpected error
*/
static size_t
{
if (is_intel_br(softstate)) {
/* extend this value to 16 bit for later tests */
} else if (is_64bit_aper(softstate)) {
cap + AGP_CONF_APERSIZE);
}
if (value & AGP_APER_128M_MASK) {
switch (value & AGP_APER_128M_MASK) {
case AGP_APER_4M:
break;
case AGP_APER_8M:
break;
case AGP_APER_16M:
break;
case AGP_APER_32M:
break;
case AGP_APER_64M:
break;
case AGP_APER_128M:
break;
default:
size = 0; /* not true */
}
} else {
switch (value & AGP_APER_4G_MASK) {
case AGP_APER_256M:
break;
case AGP_APER_512M:
break;
case AGP_APER_1024M:
break;
case AGP_APER_2048M:
break;
case AGP_APER_4G:
break;
default:
size = 0; /* not true */
}
}
/*
* In some cases, there is no APSIZE register, so the size value
* of 256M could be wrong. Check the value by reading the size of
* the first register which was set in the PCI configuration space.
*/
if (size == 256) {
return (0);
"APSIZE 256M doesn't match regsize %lx",
regsize));
}
}
return (size);
}
static void
{
/* Disable the GTLB for Intel chipsets */
}
/*
* Pre-allocated graphics memory for every type of Intel north bridge, mem size
* are specified in kbytes.
*/
#define GMS_MB(n) ((n) * 1024)
#define GMS_SHIFT 4
#define GMS_SIZE(a) (sizeof (a) / sizeof (int))
/*
* Since value zero always means "No memory pre-allocated", value of (GMS - 1)
* is used to index these arrays, i.e. gms_xxx[1] contains the mem size (in kb)
* that GMS value 0x1 corresponding to.
*
* Assuming all "reserved" GMS value as zero bytes of pre-allocated graphics
* memory, unless some special BIOS settings exist.
*/
GMS_MB(32)};
/* There is no modes for 16M in datasheet, but some BIOS add it. */
static gms_mode_t gms_modes[] = {
};
static int
{
int num_modes;
int i;
for (i = 0; i < num_modes; i++) {
break;
}
return ((i == num_modes) ? -1 : i);
}
/* Returns the size (kbytes) of pre-allocated graphics memory */
static size_t
{
int gms_off;
kbytes = 0;
/* fetch the GMS value from DRAM controller */
/* assuming zero byte for 0 or "reserved" GMS values */
"devid = %x, GMS = %x. assuming zero byte of "
"pre-allocated memory",
goto done;
}
memval--; /* use (GMS_value - 1) as index */
done:
"i8xx_biosmem_detect: %ldKB BIOS pre-allocated memory detected",
kbytes));
return (kbytes);
}
/*ARGSUSED*/
{
switch (cmd) {
case DDI_INFO_DEVT2DEVINFO:
rval = DDI_SUCCESS;
} else
break;
case DDI_INFO_DEVT2INSTANCE:
rval = DDI_SUCCESS;
default:
break;
}
return (rval);
}
static int
{
int gms_off;
/*
* We recover the gmch graphics control register here
*/
return (DDI_SUCCESS);
}
static int
{
int gms_off;
return (DDI_SUCCESS);
}
static int
{
int instance;
int status;
switch (cmd) {
case DDI_ATTACH:
break;
case DDI_RESUME:
return (intel_br_resume(softstate));
default:
"only attach and resume ops are supported"));
return (DDI_FAILURE);
}
instance) != DDI_SUCCESS) {
"soft state zalloc failed"));
return (DDI_FAILURE);
}
if (status != DDI_SUCCESS) {
"pci config setup failed"));
instance);
return (DDI_FAILURE);
}
if (softstate->tsoft_gms_off < 0) {
"read gms offset failed"));
instance);
return (DDI_FAILURE);
}
if (softstate->tsoft_acaptr == 0) {
/* Make a correction for some Intel chipsets */
if (is_intel_br(softstate))
else {
"Not a supposed corretion"));
instance);
return (DDI_FAILURE);
}
}
if (status != DDI_SUCCESS) {
"Create minor node failed"));
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
static int
{
int instance;
if (cmd == DDI_SUSPEND) {
/* get GMS modes list entry */
return (intel_br_suspend(softstate));
}
if (cmd != DDI_DETACH) {
"only detach and suspend ops are supported"));
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
static int
{
static char kernel_only[] =
"amd64_gart_ioctl: is a kernel only ioctl";
return (ENXIO);
}
return (ENXIO);
switch (cmd) {
case CHIP_DETECT:
{
int type = 0;
if (is_intel_br(st))
else if (is_64bit_aper(st))
type = CHIP_IS_AMD;
else {
type = 0;
}
return (EFAULT);
}
break;
}
case I8XX_GET_PREALLOC_SIZE:
{
if (!is_intel_br(st)) {
return (EINVAL);
}
return (EFAULT);
}
break;
}
case AGP_TARGET_GETINFO:
{
cap + AGP_CONF_STATUS);
sizeof (i_agp_info_t), mode)) {
return (EFAULT);
}
break;
}
/*
* This ioctl is only for Intel AGP chipsets.
* It is not necessary for the AMD8151 AGP bridge, because
* this register in the AMD8151 does not control any hardware.
* It is only provided for compatibility with an Intel AGP bridge.
* Please refer to the <<AMD8151 data sheet>> page 24,
* AGP device GART pointer.
*/
case AGP_TARGET_SET_GATTADDR:
{
return (EFAULT);
}
break;
}
case AGP_TARGET_SETCMD:
{
return (EFAULT);
}
command);
break;
}
case AGP_TARGET_FLUSH_GTLB:
{
value &= ~AGPCTRL_GTLBEN;
value |= AGPCTRL_GTLBEN;
break;
}
case AGP_TARGET_CONFIGURE:
{
/*
* In Intel agp bridges, agp misc register offset
* is indexed from 0 instead of capability register.
* AMD agp bridges have no such misc register
* to control the aperture access, and they have
* similar regsiters in CPU gart devices instead.
*/
if (is_intel_br(st)) {
value |= AGP_MISC_APEN;
}
break;
}
case AGP_TARGET_UNCONFIG:
{
if (is_intel_br(st)) {
value2 &= ~AGP_MISC_APEN;
}
value1 &= ~AGPCMD_AGPEN;
value1);
break;
}
default:
return (ENXIO);
} /* end switch */
return (0);
}
/*ARGSUSED*/
static int
{
return (ENXIO);
return (ENXIO);
return (0);
}
/*ARGSUSED*/
static int
{
return (ENXIO);
return (0);
}
static struct cb_ops agp_target_cb_ops = {
agp_target_open, /* cb_open */
agp_target_close, /* cb_close */
nodev, /* cb_strategy */
nodev, /* cb_print */
nodev, /* cb_dump */
nodev, /* cb_read() */
nodev, /* cb_write() */
agp_target_ioctl, /* cb_ioctl */
nodev, /* cb_devmap */
nodev, /* cb_mmap */
nodev, /* cb_segmap */
nochpoll, /* cb_chpoll */
ddi_prop_op, /* cb_prop_op */
0, /* cb_stream */
CB_REV, /* cb_ops version? */
nodev, /* cb_aread() */
nodev, /* cb_awrite() */
};
/* device operations */
static struct dev_ops agp_target_ops = {
DEVO_REV, /* devo_rev */
0, /* devo_refcnt */
agptarget_getinfo, /* devo_getinfo */
nulldev, /* devo_identify */
nulldev, /* devo_probe */
agp_target_attach, /* devo_attach */
agp_target_detach, /* devo_detach */
nodev, /* devo_reset */
&agp_target_cb_ops, /* devo_cb_ops */
0, /* devo_bus_ops */
0, /* devo_power */
ddi_quiesce_not_supported, /* devo_quiesce */
};
"AGP target driver",
};
static struct modlinkage modlinkage = {
MODREV_1, /* MODREV_1 is indicated by manual */
};
int
_init(void)
{
int ret;
sizeof (agp_target_softstate_t), 1);
if (ret)
goto err1;
goto err2;
}
return (DDI_SUCCESS);
err2:
err1:
return (ret);
}
int
{
}
int
_fini(void)
{
int ret;
}
return (ret);
}