ia32.il revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
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/ return caller
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/*
* Put a new value into cr3 (page table base register
* void setcr3(void *value)
*/
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/*
* multiply two long numbers and yield a u_lonlong_t result
* Provided to manipulate hrtime_t values.
*/
.end
/*
* Unlock hres_lock and increment the count value. (See clock.h)
*/
.end
.end
.end
/*
* void atomic_inc16(uint16_t *addr) { ++*addr; }
* void atomic_dec16(uint16_t *addr) { --*addr; }
*/
.end
.end
/*
* Invalidate TLB translation to 1 page.
* void mmu_tlbflush_entry(void *addr)
*/
.end
/*
* Read Time Stamp Counter
* uint64_t tsc_read();
*
* usage:
* uint64_t cycles = tsc_read();
*
* PPro & PII take no less than 34 cycles to execute rdtsc + stores.
* Pentium takes about 16 cycles.
*/
.end
/*
* void tsc_clear(register)
* Clear the local Time Stamp Counter via write-MSR instruction.
* Note that while this is a 64-bit write, the top 32-bits are
* ignored, so it isn't massively useful to write anything other
* than zero.
*/
.end
/*
* Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
* a hint that the code sequence is a busy spin-wait loop. Without a pause
* instruction in these loops, the P4 Xeon processor may suffer a severe
* penalty when exiting the loop because the processor detects a possible
* memory violation. Inserting the pause instruction significantly reduces
* the likelihood of a memory order violation, improving performance.
* The pause instruction is a NOP on all other IA-32 processors.
*/
.end
/*
* Call the halt instruction. This will put the CPU to sleep until
* it is again awoken via an interrupt.
* This function should be called with interrupts already disabled
* for the CPU.
* Note that "sti" will only enable interrupts at the end of the
* subsequent instruction...in this case: "hlt".
*/
.end