ia32.il revision 26a04d6751d8dbdcf709884101e1cb3d48723af2
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/
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.end
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.end
/
/ return caller
/
.end
/
/
.end
/
/
.end
/
/
.end
/
/
.end
.end
.end
.end
.end
.end
/*
* multiply two long numbers and yield a u_longlong_t result
* Provided to manipulate hrtime_t values.
*/
.end
/*
* Unlock hres_lock and increment the count value. (See clock.h)
*/
.end
.end
.end
/*
* void atomic_inc16(uint16_t *addr) { ++*addr; }
* void atomic_dec16(uint16_t *addr) { --*addr; }
*/
.end
.end
/*
* Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
* a hint that the code sequence is a busy spin-wait loop. Without a pause
* instruction in these loops, the P4 Xeon processor may suffer a severe
* penalty when exiting the loop because the processor detects a possible
* memory violation. Inserting the pause instruction significantly reduces
* the likelihood of a memory order violation, improving performance.
* The pause instruction is a NOP on all other IA-32 processors.
*/
.end
/
/
/ prefetcht0 (%eax)
.end