mp_platform_xpv.c revision 7ff178cd8db129d385d3177eb20744d3b6efc59b
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* PSMI 1.1 extensions are supported only in 2.6 and later versions.
* PSMI 1.2 extensions are supported only in 2.7 and later versions.
* PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
* PSMI 1.5 extensions are supported in Solaris Nevada.
* PSMI 1.6 extensions are supported in Solaris Nevada.
* PSMI 1.7 extensions are supported in Solaris Nevada.
*/
#define PSMI_1_7
#include <sys/processor.h>
#include <sys/smp_impldefs.h>
#include <sys/psm_common.h>
#include <sys/apic_common.h>
#include <sys/ddi_impldefs.h>
#include <sys/x86_archext.h>
#include <sys/cpc_impl.h>
#include <sys/archsystm.h>
#include <sys/machsystm.h>
#include <sys/rm_platter.h>
#include <sys/privregs.h>
#include <sys/pci_intr_lib.h>
/*
* Local Function Prototypes
*/
static void apic_xlate_vector_free_timeout_handler(void *arg);
struct ioapic_reprogram_data *drep);
int type);
static void delete_defer_repro_ent(int which_irq);
static void apic_ioapic_wait_pending_clear(int ioapicindex,
int intin_no);
extern int apic_find_bus_id(int bustype);
extern int apic_sci_vect;
extern iflag_t apic_sci_flags;
extern int apic_intr_policy;
extern char *psm_name;
/*
*/
/* Max wait time (in repetitions) for flags to clear in an RDT entry. */
extern int apic_max_reps_clear_pending;
/* The irq # is implicit in the array index: */
/*
* APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. ioapic_reprogram_info
* is indexed by IRQ number, NOT by vector number.
*/
extern int apic_int_busy_mark;
extern int apic_int_free_mark;
extern int apic_diff_for_redistribution;
extern int apic_sample_factor_redistribution;
extern int apic_redist_cpu_skip;
extern int apic_num_imbalance;
extern int apic_num_rebind;
/* timeout for xlate_vector, mark_vector */
extern int apic_defconf;
extern int apic_irq_translate;
extern int apic_use_acpi_madt_only; /* 1=ONLY use MADT from ACPI */
/*
* First available slot to be used as IRQ index into the apic_irq_table
* for those interrupts (like MSI/X) that don't have a physical IRQ.
*/
extern int apic_first_avail_irq;
/*
* apic_defer_reprogram_lock ensures that only one processor is handling
* deferred interrupt programming at *_intr_exit time.
*/
static lock_t apic_defer_reprogram_lock;
/*
* The current number of deferred reprogrammings outstanding
*/
#ifdef DEBUG
/*
* Counters that keep track of deferred reprogramming stats
*/
#endif
extern int apic_io_max;
extern struct apic_io_intr *apic_io_intrp;
extern uint32_t eisa_level_intr_mask;
/* At least MSB will be set if EISA bus */
extern int apic_pci_bus_total;
extern uchar_t apic_single_pci_busid;
/*
* Following declarations are for revectoring; used when ISRs at different
* IPLs share an irq.
*/
static lock_t apic_revector_lock;
int apic_revector_pending = 0;
static uchar_t *apic_oldvec_to_newvec;
static uchar_t *apic_newvec_to_oldvec;
/* ACPI Interrupt Source Override Structure ptr */
extern int acpi_iso_cnt;
/*
* Auto-configuration routines
*/
/*
* Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable
* are also set to NULL. vector->irq is set to a value which cannot map
* to a real irq to show that it is free.
*/
void
apic_init_common(void)
{
int i, j, indx;
int *iptr;
/*
* Initialize apic_ipls from apic_vectortoipl. This array is
* used in apic_intr_enter to determine the IPL to use for the
* corresponding vector. On some systems, due to hardware errata
* and interrupt sharing, the IPL may not correspond to the IPL listed
* in apic_vectortoipl (see apic_addspl and apic_delspl).
*/
for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
indx = i * APIC_VECTOR_PER_IPL;
for (j = 0; j < APIC_VECTOR_PER_IPL; j++, indx++)
}
/* cpu 0 is always up (for now) */
iptr = (int *)&apic_irq_table[0];
for (i = 0; i <= APIC_MAX_VECTOR; i++) {
apic_level_intr[i] = 0;
/* These *must* be initted to B_TRUE! */
apic_reprogram_info[i].tries = 0;
apic_reprogram_info[i].bindcpu = 0;
}
/*
* Allocate a dummy irq table entry for the reserved entry.
* This takes care of the race between removing an irq and
* clock detecting a CPU in that irq during interrupt load
* sampling.
*/
}
void
{
int ioapic_ix;
int i, j;
/* mask interrupt vectors */
for (j = 0; j < apic_io_max && mask_apic; j++) {
int intin_max;
ioapic_ix = j;
/* Bits 23-16 define the maximum redirection entries */
& 0xff;
for (i = 0; i <= intin_max; i++)
}
/*
*/
if (apic_sci_vect > 0) {
/*
* acpica has already done add_avintr(); we just
* to finish the job by mimicing translate_irq()
*
* Fake up an intrspec and setup the tables
*/
return;
}
iflag = intr_clear();
/* Program I/O APIC */
irqptr->airq_share++;
}
}
/*
* Add mask bits to disable interrupt vector from happening
* at or above IPL. In addition, it should remove mask bits
* to enable interrupt vectors below the given IPL.
*
* Both add and delspl are complicated by the fact that different interrupts
* may share IRQs. This can happen in two ways.
* 1. The same H/W line is shared by more than 1 device
* 1a. with interrupts at different IPLs
* 1b. with interrupts at same IPL
* 2. We ran out of vectors at a given IPL and started sharing vectors.
* 1b and 2 should be handled gracefully, except for the fact some ISRs
* will get called often when no interrupt is pending for the device.
* For 1a, we handle it at the higher IPL.
*/
/*ARGSUSED*/
int
{
int irqindex;
return (PSM_FAILURE);
while (irqptr) {
break;
}
irqptr->airq_share++;
/* return if it is not hardware interrupt */
return (PSM_SUCCESS);
/* Or if there are more interupts at a higher IPL */
return (PSM_SUCCESS);
/*
* if apic_picinit() has not been called yet, just return.
* At the end of apic_picinit(), we will call setup_io_intr().
*/
if (!apic_picinit_called)
return (PSM_SUCCESS);
/*
* Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate,
* return failure.
*/
if (vector == 0) {
irqptr->airq_share--;
return (PSM_FAILURE);
}
irqptr = irqheadptr;
while (irqptr) {
/*
* reprogram irq being added and every one else
* who is not in the UNINIT state
*/
iflag = intr_clear();
B_FALSE);
}
}
return (PSM_SUCCESS);
/*
* We cannot upgrade the vector, but we can change
* the IPL that this vector induces.
*
* Note that we subtract APIC_BASE_VECT from the vector
* here because this array is used in apic_intr_enter
* (no need to add APIC_BASE_VECT in that hot code
* path since we can do it in the rarely-executed path
* here).
*/
irqptr = irqheadptr;
while (irqptr) {
}
return (PSM_SUCCESS);
}
iflag = intr_clear();
return (PSM_SUCCESS);
}
/*
* Recompute mask bits for the given interrupt vector.
* If there is no interrupt servicing routine for this
* vector, this function should disable interrupt vector
* from happening at all IPLs. If there are still
* handlers using the given vector, this function should
* disable the given vector from happening below the lowest
* IPL of the remaining hadlers.
*/
/*ARGSUSED*/
int
{
int ioapic_ix;
while (irqptr) {
break;
}
irqptr->airq_share--;
/*
* If there are more interrupts at a higher IPL, we don't need
* to disable anything.
*/
return (PSM_SUCCESS);
/* return if it is not hardware interrupt */
return (PSM_SUCCESS);
if (!apic_picinit_called) {
/*
* Clear irq_struct. If two devices shared an intpt
* line & 1 unloaded before picinit, we are hosed. But, then
* we hope the machine survive.
*/
return (PSM_SUCCESS);
}
/*
* Downgrade vector to new max_ipl if needed. If we cannot allocate,
* use old IPL. Not very elegant, but it should work.
*/
irqp = irqheadptr;
while (irqp) {
iflag = intr_clear();
(void) apic_setup_io_intr(irqp,
}
}
}
max_ipl != PSM_INVALID_IPL &&
/*
* We cannot downgrade the IPL of the vector below the vector's
* hardware priority. If we did, it would be possible for a
* higher-priority hardware vector to interrupt a CPU running at an IPL
* lower than the hardware priority of the interrupting vector (but
* higher than the soft IPL of this IRQ). When this happens, we would
* then try to drop the IPL BELOW what it was (effectively dropping
* below base_spl) which would be potentially catastrophic.
*
* (e.g. Suppose the hardware vector associated with this IRQ is 0x40
* (hardware IPL of 4). Further assume that the old IPL of this IRQ
* was 4, but the new IPL is 1. If we forced vector 0x40 to result in
* an IPL of 1, it would be possible for the processor to be executing
* at IPL 3 and for an interrupt to come in on vector 0x40, interrupting
* the currently-executing ISR. When apic_intr_enter consults
* apic_irqs[], it will return 1, bringing the IPL of the CPU down to 1
* so even though the processor was running at IPL 4, an IPL 1
* interrupt will have interrupted it, which must not happen)).
*
* Effectively, this means that the hardware priority corresponding to
* the IRQ's IPL (in apic_ipls[]) cannot be lower than the vector's
* hardware priority.
*
* (In the above example, then, after removal of the IPL 4 device's
* interrupt handler, the new IPL will continue to be 4 because the
* hardware priority that IPL 1 implies is lower than the hardware
* priority of the vector used.)
*/
/* apic_ipls is indexed by vector, starting at APIC_BASE_VECT */
/*
* If there are still devices using this IRQ, determine the
* new ipl to use.
*/
if (irqptr->airq_share) {
int vect_desired_hwpri, hwpri;
/*
* If the desired IPL's hardware priority is lower
* than that of the vector, use the hardware priority
* of the vector to determine the new IPL.
*/
/*
* Now, to get the right index for apic_vectortoipl,
* we need to subtract APIC_BASE_VECT from the
* hardware-vector-equivalent (in hwpri). Since hwpri
* is already shifted, we shift APIC_BASE_VECT before
* doing the subtraction.
*/
irqp = irqheadptr;
while (irqp) {
}
} else {
/*
* No more devices on this IRQ, so reset this vector's
* element in apic_ipls to the original IPL for this
* vector
*/
}
}
/*
* If there are still active interrupts, we are done.
*/
if (irqptr->airq_share)
return (PSM_SUCCESS);
iflag = intr_clear();
/*
* Disable the MSI vector
* Make sure we only disable on the last
* of the multi-MSI support
*/
}
/*
* Disable the MSI-X vector
*/
/*
* Make sure we only disable on the last MSI-X
*/
}
} else {
/*
* The assumption here is that this is safe, even for
* systems with IOAPICs that suffer from the hardware
* erratum because all devices have been quiesced before
* they unregister their interrupt handlers. If that
* assumption turns out to be false, this mask operation
* can induce the same erratum result we're trying to
* avoid.
*/
}
/*
* This irq entry is the only one in the chain.
*/
if (bind_cpu & IRQ_USER_BOUND) {
/* If hardbound, temp_cpu == cpu */
bind_cpu &= ~IRQ_USER_BOUND;
} else
}
return (PSM_SUCCESS);
}
/*
* If we get here, we are sharing the vector and there are more than
* one active irq entries in the chain.
*/
/* Remove the irq entry from the chain */
} else {
}
/* Free the irq entry */
return (PSM_SUCCESS);
}
/*
* apic_introp_xlate() replaces apic_translate_irq() and is
* called only from apic_intr_ops(). With the new ADII framework,
* the priority can no longer be retrieved through i_ddi_get_intrspec().
* It has to be passed in from the caller.
*
* Return value:
* Success: irqno for the given device
* Failure: -1
*/
int
{
char dev_type[16];
struct apic_io_intr *intrp;
int parent_is_pci_or_pciex = 0;
int child_is_pciex = 0;
irqno));
&dev_len) == DDI_PROP_SUCCESS) {
}
&dev_len) == DDI_PROP_SUCCESS) {
child_is_pciex = 1;
}
if (DDI_INTR_IS_MSI_OR_MSIX(type)) {
}
}
bustype = 0;
/* check if we have already translated this irq */
while (airqp) {
}
}
}
if (apic_defconf)
goto defconf;
goto nonpci;
if (parent_is_pci_or_pciex) {
/* pci device */
goto nonpci;
busid = (int)apic_single_pci_busid;
return (-1);
if (apic_enable_acpi && !apic_use_acpi_madt_only) {
return (-1);
} else {
== NULL) {
return (-1);
}
}
if (apic_enable_acpi && !apic_use_acpi_madt_only) {
/* search iso entries first */
if (acpi_iso_cnt != 0) {
i = 0;
while (i < acpi_iso_cnt) {
isop =
>> 2;
return (apic_setup_irq_table(
}
i++;
}
}
}
} else {
if (bustype == 0) /* not initialized */
for (i = 0; i < 2; i++) {
!= NULL)) {
return (newirq);
}
goto defconf;
}
}
}
/* MPS default configuration */
if (newirq == -1)
return (-1);
return (newirq);
}
/*
* Attempt to share vector with someone else
*/
static int
{
#ifdef DEBUG
#endif /* DEBUG */
if (intr_flagp)
newirq = apic_vector_to_irq[i];
if (newirq == APIC_RESV_IRQ)
continue;
/* not compatible */
continue;
chosen_irq = newirq;
}
}
if (chosen_irq != -1) {
/*
* Assign a share id which is free or which is larger
* than the largest one.
*/
share_id = 1;
while (irqptr) {
break;
}
#ifdef DEBUG
#endif /* DEBUG */
}
if (!irqptr) {
#ifdef DEBUG
#endif /* DEBUG */
}
if (intr_flagp)
#ifdef DEBUG
/* shuffle the pointers to test apic_delspl path */
if (tmpirqp) {
}
#endif /* DEBUG */
}
return (-1);
}
/*
* Allocate/Initialize the apic_irq_table[] entry for given irqno. If the entry
* is used already, we will try to allocate a new irqno.
*
* Return value:
* Success: irqno
* Failure: -1
*/
static int
{
int newirq, intr_index;
if (DDI_INTR_IS_MSI_OR_MSIX(type)) {
/* MSI/X doesn't need to setup ioapic stuffs */
ioapicindex = 0xff;
ioapic = 0xff;
/* need an irq for MSI/X to index into autovect[] */
return (-1);
}
/* Find ioapicindex. If destid was ALL, we will exit with 0. */
break;
(ioapic == INTR_ALL_APIC));
/* check whether this intin# has been used by another irqno */
return (newirq);
}
} else if (intr_flagp != NULL) {
/* ACPI case */
if (apic_irq_table[irqno] &&
return (irqno);
}
} else {
/* default configuration */
ioapicindex = 0;
}
irqno));
/* This is OK to do really */
" instance %d and SCI",
} else {
" instance %d and %s instance %d",
}
return (newirq);
}
/* try high priority allocation now that share has failed */
return (-1);
}
}
} else {
/*
* The slot is used by another irqno, so allocate
* a free irqno for this interrupt
*/
if (newirq == -1) {
return (-1);
}
KM_SLEEP);
}
}
}
irqptr->airq_share_id = 0;
if (intr_flagp)
if (!DDI_INTR_IS_MSI_OR_MSIX(type)) {
/* setup I/O APIC entry for non-MSI/X interrupts */
}
return (irqno);
}
/*
* return the cpu to which this intr should be bound.
* Check properties or any other mechanism to see if user wants it
* bound to a specific CPU. If so, return the cpu id with high bit set.
* If not, use the policy to choose a cpu and return the id.
*/
{
char prop_name[32];
if (apic_intr_policy == INTR_LOWEST_PRIORITY)
return (IRQ_UNBOUND);
if (apic_nproc == 1)
return (0);
i = apic_min_device_irq;
for (; i <= apic_max_device_irq; i++) {
== FREE_INDEX))
continue;
(!(apic_irq_table[i]->airq_cpu &
IRQ_USER_BOUND))) {
"!%s: %s (%s) instance #%d "
"irq 0x%x vector 0x%x ioapic 0x%x "
"intin 0x%x is bound to cpu %d\n",
return (cpu);
}
}
}
/*
* search for "drvname"_intpt_bind_cpus property first, the
* syntax of the property should be "a[,b,c,...]" where
* instance 0 binds to cpu a, instance 1 binds to cpu b,
* instance 3 binds to cpu c...
* ddi_getlongprop() will search /option first, then /
* if "drvname"_intpt_bind_cpus doesn't exist, then find
* intpt_bind_cpus property. The syntax is the same, and
* it applies to all the devices if its "drvname" specific
* property doesn't exist
*/
if (rc != DDI_PROP_SUCCESS) {
}
}
if (rc == DDI_PROP_SUCCESS) {
if (prop_val[i] == ',')
count++;
count++;
/*
* if somehow the binding instances defined in the
* property are not enough for this instno., then
* reuse the pattern for the next instance until
* it reaches the requested instno
*/
i = 0;
while (i < instno)
if (*cptr++ == ',')
i++;
/* if specific CPU is bogus, then default to next cpu */
if (!apic_cpu_in_range(bind_cpu)) {
} else {
/* indicate that we are bound at user request */
}
/*
* no need to check apic_cpus[].aci_status, if specific CPU is
* not up, then post_cpu_start will handle it.
*/
}
if (rc != DDI_PROP_SUCCESS) {
iflag = intr_clear();
}
"vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n",
bind_cpu & ~IRQ_USER_BOUND);
else
"vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n",
}
/*
* Mark vector as being in the process of being deleted. Interrupts
* may still come in on some CPU. The moment an interrupt comes with
* the new vector, we know we can free the old one. Called only from
* addspl and delspl with interrupts disabled. Because an interrupt
* can be shared, but no interrupt from either device may come in,
* we also use a timeout mechanism, which we arbitrarily set to
* apic_revector_timeout microseconds.
*/
static void
{
iflag = intr_clear();
if (!apic_oldvec_to_newvec) {
if (!apic_oldvec_to_newvec) {
/*
* This failure is not catastrophic.
* But, the oldvec will never be freed.
*/
return;
}
}
/* See if we already did this for drivers which do double addintrs */
}
}
/*
* xlate_vector is called from intr_enter if revector_pending is set.
* It will xlate it if needed and mark the old vector as free.
*/
{
/* Do we really need to do this ? */
if (!apic_revector_pending) {
return (vector);
}
else {
/*
* The incoming vector is new . See if a stale entry is
* remaining
*/
}
if (oldvector) {
/* There could have been more than one reprogramming! */
return (apic_xlate_vector(newvector));
}
return (vector);
}
void
{
iflag = intr_clear();
}
}
/*
* Bind interrupt corresponding to irq_ptr to bind_cpu.
* Must be called with interrupts disabled and apic_ioapic_lock held
*/
int
struct ioapic_reprogram_data *drep)
{
int ioapicindex, intin_no;
int which_irq;
if (airq_temp_cpu & IRQ_USER_BOUND)
/* Mask off high bit so it can be used as array index */
}
/*
* Can't bind to a CPU that's not accepting interrupts:
*/
return (1);
/*
* If we are about to change the interrupt vector for this interrupt,
* and this interrupt is level-triggered, attached to an IOAPIC,
* has been delivered to a CPU and that CPU has not handled it
* yet, we cannot reprogram the IOAPIC now.
*/
intin_no);
return (0);
}
/*
* NOTE: We do not unmask the RDT here, as an interrupt MAY
* still come in before we have a chance to reprogram it below.
* The reprogramming below will simultaneously change and
* unmask the RDT entry.
*/
AV_TOALL);
/*
* Write the vector, trigger, and polarity portion of
* the RDT
*/
return (0);
}
}
if (bind_cpu & IRQ_USER_BOUND) {
} else {
}
}
/* Write the RDT entry -- bind to a specific CPU: */
/* Write the vector, trigger, and polarity portion of the RDT */
} else {
if (type == DDI_INTR_TYPE_MSI) {
if (irq_ptr->airq_ioapicindex ==
irq_ptr->airq_origirq) {
/* first one */
"apic_pci_msi_enable_vector\n"));
}
if ((irq_ptr->airq_ioapicindex +
"apic_pci_msi_enable_mode\n"));
}
} else { /* MSI-X */
}
}
return (0);
}
static void
{
& AV_REMOTE_IRR) != 0) {
/*
* Trying to clear the bit through normal
* channels has failed. So as a last-ditch
* effort, try to set the trigger mode to
* edge, then to level. This has been
* observed to work on many systems.
*/
/*
* If the bit's STILL set, this interrupt may
* be hosed.
*/
intin_no) & AV_REMOTE_IRR) != 0) {
prom_printf("%s: Remote IRR still "
"not clear for IOAPIC %d intin %d.\n"
"\tInterrupts to this pin may cease "
intin_no);
#ifdef DEBUG
#endif
}
}
}
/*
* This function is protected by apic_ioapic_lock coupled with the
* fact that interrupts are disabled.
*/
static void
{
return;
#ifdef DEBUG
#endif
if (--apic_reprogram_outstanding == 0) {
setlvlx = psm_intr_exit_fn();
}
}
/*
* Interrupts must be disabled during this function to prevent
* self-deadlock. Interrupts are disabled because this function
* is called from apic_check_stuck_interrupt(), which is called
* from apic_rebind(), which requires its caller to disable interrupts.
*/
static void
{
ASSERT(!interrupts_enabled());
/*
* On the off-chance that there's already a deferred
* reprogramming on this irq, check, and if so, just update the
* CPU and irq pointer to which the interrupt is targeted, then return.
*/
return;
}
/*
* This must be the last thing set, since we're not
* grabbing any locks, apic_try_deferred_reprogram() will
* make its decision about using this entry iff done
* is false.
*/
/*
* If there were previously no deferred reprogrammings, change
* setlvlx to call apic_try_deferred_reprogram()
*/
if (++apic_reprogram_outstanding == 1) {
}
}
static void
{
int reproirq;
struct ioapic_reprogram_data *drep;
if (!lock_try(&apic_defer_reprogram_lock)) {
return;
}
/*
* Acquire the apic_ioapic_lock so that any other operations that
* may affect the apic_reprogram_info state are serialized.
* It's still possible for the last deferred reprogramming to clear
* between the time we entered this function and the time we get to
* the for loop below. In that case, *setlvlx will have been set
* back to *_intr_exit and drep will be NULL. (There's no way to
* stop that from happening -- we would need to grab a lock before
* calling *setlvlx, which is neither realistic nor prudent).
*/
iflag = intr_clear();
/*
* For each deferred RDT entry, try to reprogram it now. Note that
* there is no lock acquisition to read apic_reprogram_info because
* '.done' is set only after the other fields in the structure are set.
*/
break;
}
}
/*
* Either we found a deferred action to perform, or
* we entered this function spuriously, after *setlvlx
* was restored to point to *_intr_exit. Any other
* permutation is invalid.
*/
/*
* Though we can't really do anything about errors
* at this point, keep track of them for reporting.
* Note that it is very possible for apic_setup_io_intr
* to re-register this very timeout if the Remote IRR bit
* has not yet cleared.
*/
#ifdef DEBUG
}
} else {
}
#else
#endif
}
static void
{
int waited;
/*
* Wait for the delivery pending bit to clear.
*/
/*
* If we're still waiting on the delivery of this interrupt,
* continue to wait here until it is delivered (this should be
* a very small amount of time, but include a timeout just in
* case).
*/
waited++) {
intin_no) & AV_PENDING) == 0) {
break;
}
}
}
}
/*
* Checks to see if the IOAPIC interrupt entry specified has its Remote IRR
* bit set. Calls functions that modify the function that setlvlx points to,
* so that the reprogramming can be retried very shortly.
*
* This function will mask the RDT entry if the interrupt is level-triggered.
* (The caller is responsible for unmasking the RDT entry.)
*
* Returns non-zero if the caller should defer IOAPIC reprogramming.
*/
static int
struct ioapic_reprogram_data *drep)
{
int waited;
int reps = 0;
/*
* Wait for the delivery pending bit to clear.
*/
do {
++reps;
/*
* Mask the RDT entry, but only if it's a level-triggered
* interrupt
*/
intin_no);
/* Mask it */
}
/*
* If there was a race and an interrupt was injected
* just before we masked, check for that case here.
* Then, unmask the RDT entry and try again. If we're
* on our last try, don't unmask (because we want the
* RDT entry to remain masked for the rest of the
* function).
*/
intin_no);
if ((rdt_entry & AV_PENDING) &&
(reps < apic_max_reps_clear_pending)) {
/* Unmask it */
}
}
} while ((rdt_entry & AV_PENDING) &&
#ifdef DEBUG
if (rdt_entry & AV_PENDING)
#endif
/*
* If the remote IRR bit is set, then the interrupt has been sent
* to a CPU for processing. We have no choice but to wait for
* that CPU to process the interrupt, at which point the remote IRR
* bit will be cleared.
*/
/*
* If the CPU that this RDT is bound to is NOT the current
* CPU, wait until that CPU handles the interrupt and ACKs
* it. If this interrupt is not bound to any CPU (that is,
* if it's bound to the logical destination of "anyone"), it
* may have been delivered to the current CPU so handle that
* case by deferring the reprogramming (below).
*/
if ((old_bind_cpu != IRQ_UNBOUND) &&
(old_bind_cpu != IRQ_UNINIT) &&
(old_bind_cpu != psm_get_cpu_id())) {
waited++) {
intin_no) & AV_REMOTE_IRR) == 0) {
/* Remote IRR has cleared! */
return (0);
}
}
}
/*
* If we waited and the Remote IRR bit is still not cleared,
* AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
* times for this interrupt, try the last-ditch workaround:
*/
/* Mark this one as reprogrammed: */
return (0);
} else {
#ifdef DEBUG
#endif
/*
* If waiting for the Remote IRR bit (above) didn't
* allow it to clear, defer the reprogramming.
* Add a new deferred-programming entry if the
* caller passed a NULL one (and update the existing one
* in case anything changed).
*/
if (drep)
/* Inform caller to defer IOAPIC programming: */
return (1);
}
}
/* Remote IRR is clear */
return (0);
}
/*
* Called to migrate all interrupts at an irq to another cpu.
* Must be called with interrupts disabled and apic_ioapic_lock held
*/
int
{
int retval = 0;
while (irqptr) {
}
return (retval);
}
/*
* apic_intr_redistribute does all the messy computations for identifying
* which interrupt to move to which CPU. Currently we do just one interrupt
* at a time. This reduces the time we spent doing all this within clock
* interrupt. When it is done in idle, we could do more than 1.
* First we find the most busy and the most free CPU (time in ISR only)
* skipping those CPUs that has been identified as being ineligible (cpu_skip)
* Then we look for IRQs which are closest to the difference between the
* most busy CPU and the average ISR load. We try to find one whose load
* is less than difference.If none exists, then we chose one larger than the
* difference, provided it does not make the most idle CPU worse than the
* most busy one. In the end, we clear all the busy fields for CPUs. For
* IRQs, they are cleared as they are scanned.
*/
void
apic_intr_redistribute(void)
{
int busiest_cpu, most_free_cpu;
int average_busy, cpus_online;
int i, busy;
cpus_online = 0;
/*
* Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu
* without ioapic_lock. That is OK as we are just doing statistical
* sampling anyway and any inaccuracy now will get corrected next time
* The call to rebind which actually changes things will make sure
* we are consistent.
*/
for (i = 0; i < apic_nproc; i++) {
if (apic_cpu_in_range(i) &&
!(apic_redist_cpu_skip & (1 << i)) &&
/*
* If no unbound interrupts or only 1 total on this
* CPU, skip
*/
if (!cpu_infop->aci_temp_bound ||
== 1) {
apic_redist_cpu_skip |= 1 << i;
continue;
}
average_busy += busy;
cpus_online++;
busiest_cpu = i;
}
most_free_cpu = i;
}
if (busy > apic_int_busy_mark) {
cpu_busy |= 1 << i;
} else {
if (busy < apic_int_free_mark)
cpu_free |= 1 << i;
}
}
}
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
"redistribute busy=%x free=%x max=%x min=%x",
}
#endif /* DEBUG */
max_busy = 0;
i = apic_min_device_irq;
for (; i <= apic_max_device_irq; i++) {
/* Change to linked list per CPU ? */
continue;
/* Check for irq_busy & decide which one to move */
/* Also zero them for next round */
/*
* Check for least busy CPU,
* best fit or what ?
*/
/*
* Most busy within the
* required differential
*/
}
} else {
/*
* least busy, but more than
* the reqd diff
*/
if (min_busy <
(diff + average_busy -
min_free)) {
/*
* Making sure new cpu
* will not end up
* worse
*/
min_busy =
}
}
}
}
}
if (max_busy_irq != NULL) {
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
prom_printf("rebinding %x to %x",
}
#endif /* DEBUG */
iflag = intr_clear();
if (lock_try(&apic_ioapic_lock)) {
most_free_cpu) == 0) {
/* Make change permenant */
}
}
} else if (min_busy_irq != NULL) {
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
prom_printf("rebinding %x to %x",
}
#endif /* DEBUG */
iflag = intr_clear();
if (lock_try(&apic_ioapic_lock)) {
most_free_cpu) == 0) {
/* Make change permenant */
}
}
} else {
/*
* We leave cpu_skip set so that next time we
* can choose another cpu
*/
}
}
} else {
/*
* found nothing. Could be that we skipped over valid CPUs
* or we have balanced everything. If we had a variable
* ticks_for_redistribution, it could be increased here.
* apic_int_busy, int_free etc would also need to be
* changed.
*/
if (apic_redist_cpu_skip)
apic_redist_cpu_skip = 0;
}
for (i = 0; i < apic_nproc; i++) {
if (apic_cpu_in_range(i)) {
}
}
}
void
apic_cleanup_busy(void)
{
int i;
for (i = 0; i < apic_nproc; i++) {
if (apic_cpu_in_range(i)) {
}
}
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
}
}
int
{
return (PSM_SUCCESS);
}