ioat.h revision eca2601cae391051acb146d28fba04237fe1eb85
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_IOAT_H
#define _SYS_IOAT_H
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/dcopy_device.h>
/* ioat ioctls */
typedef enum {
typedef struct ioat_ioctl_reg_s {
typedef ioat_ioctl_reg_t ioat_ioctl_wrreg_t;
typedef ioat_ioctl_reg_t ioat_ioctl_rdreg_t;
#ifdef _KERNEL
/* *** Driver Private Below *** */
/* IOAT_DMACAPABILITY flags */
#define IOAT_DMACAP_PAGEBREAK 0x1
#define IOAT_DMACAP_CRC 0x2
#define IOAT_DMACAP_MARKERSKIP 0x4
#define IOAT_DMACAP_XOR 0x8
#define IOAT_DMACAP_DCA 0x10
/* IOAT_INTRCTL bits */
#define IOAT_INTRCTL_MASTER_EN 0x1
#define IOAT_INTRCTL_INTR_STAT 0x2
/* MMIO Registers */
#define IOAT_CHANNELREG_OFFSET 0x80
/* Channel Registers */
#define IOAT_CHAN_STS_ADDR_MASK 0xFFFFFFFFFFFFFFC0
#define IOAT_CHAN_STS_XFER_MASK 0x3F
#define IOAT_CHAN_STS_FAIL_MASK 0x6
#define IOAT_CMPL_INDEX(channel) \
#define IOAT_CMPL_FAILED(channel) \
typedef struct ioat_chan_desc_s {
/* dca dd_ctrl bits */
#define IOAT_DESC_CTRL_CNTX_CHNG 0x1
typedef struct ioat_chan_dca_desc_s {
/* dma dd_ctrl bits */
#define IOAT_DESC_DMACTRL_NULL 0x20
#define IOAT_DESC_CTRL_FENCE 0x10
#define IOAT_DESC_CTRL_CMPL 0x8
#define IOAT_DESC_CTRL_NODSTSNP 0x4
#define IOAT_DESC_CTRL_NOSRCSNP 0x2
#define IOAT_DESC_CTRL_INTR 0x1
typedef struct ioat_chan_dma_desc_s {
typedef enum {
/* ioat private data per command */
typedef struct ioat_cmd_private_s {
/* descriptor ring state */
typedef struct ioat_channel_ring_s {
/* protects cr_cmpl_gen & cr_cmpl_last */
/* desc ring generation for the last completion we saw */
/* last descriptor index we saw complete */
/* protects cr_desc_* */
/*
* last descriptor posted. used to update its next pointer when we
* add a new desc. Also used to tack the completion (See comment for
* cr_desc_gen_prev).
*/
/* where to put the next descriptor */
/* what the current desc ring generation is */
/*
* used during cmd_post to track the last desc posted. cr_desc_next
* and cr_desc_gen will be pointing to the next free desc after
* writing the descriptor to the ring. But we want to track the
* completion for the last descriptor posted.
*/
/* the last desc in the ring (for wrap) */
/* pointer to the head of the ring */
/* physical address of the head of the ring */
/* back pointer to the channel state */
struct ioat_channel_s *cr_chan;
/* for CB v2, number of desc posted (written to IOAT_V2_CHAN_CNT) */
/* track channel state so we can handle a failure */
typedef enum {
IOAT_CHANNEL_OK = 0,
typedef struct ioat_channel_s *ioat_channel_t;
struct ioat_channel_s {
/* channel's ring state */
/* IOAT_CBv1 || IOAT_CBv2 */
/*
* state to determine if it's OK to post the the channel and if all
* future polls should return failure.
*/
/* channel command cache (*_cmd_alloc, *_cmd_free, etc) */
/* dcopy state for dcopy_device_channel_notify() call */
/* location in memory where completions are DMA'ed into */
/* channel specific registers */
/* if this channel is using DCA */
/* DCA ID the channel is currently pointing to */
/* devices channel number */
/* number of descriptors in ring */
/* descriptor ring alloc state */
/* completion buffer alloc state */
/* if inuse, we need to re-init the channel during resume */
/* backpointer to driver state */
struct ioat_state_s *ic_state;
};
typedef struct ioat_rs_s *ioat_rs_hdl_t;
/* driver state */
typedef struct ioat_state_s {
int is_instance;
/* register handle and pointer to registers */
/* IOAT_CBv1 || IOAT_CBv2 */
/* channel state */
/* device info */
/* dcopy_device_register()/dcopy_device_unregister() state */
} ioat_state_t;
int *rval);
void ioat_channel_quiesce(ioat_state_t *);
void ioat_channel_free(void *channel_private);
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_IOAT_H */