intel_iommu.h revision 4d6942938d78bfee90c3ed6b01b0ed4471a861aa
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Portions Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008, Intel Corporation.
* All rights reserved.
*/
#ifndef _SYS_INTEL_IOMMU_H
#define _SYS_INTEL_IOMMU_H
/*
* Intel IOMMU implementation specific state
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/dmar_acpi.h>
#include <sys/iommu_rscs.h>
/* extern functions */
extern int intel_iommu_attach_dmar_nodes(void);
extern void return_instr(void);
/* define the return value for iommu_map_sgl */
#define IOMMU_SGL_SUCCESS 0
#define IOMMU_SGL_DISABLE 1
#define IOMMU_SGL_NORESOURCES 2
/* register offset */
/* ioapic memory region */
#define IOAPIC_REGION_START (0xfee00000)
#define IOAPIC_REGION_END (0xfeefffff)
/* iommu page */
#define IOMMU_LEVEL_STRIDE (9)
#define IOMMU_PAGE_SHIFT (12)
#define IOMMU_BTOP(x) ((x) >> IOMMU_PAGE_SHIFT)
/* iommu page entry property */
#define IOMMU_PAGE_PROP_READ (1)
#define IOMMU_PAGE_PROP_WRITE (2)
#define IOMMU_PAGE_PROP_NOSYNC (4)
/* root context entry */
/* fault register */
#define IOMMU_FAULT_STS_PPF (2)
#define IOMMU_FAULT_STS_PFO (1)
#define IOMMU_FRR_GET_F(x) ((x) >> 63)
#define IOMMU_FRR_GET_SID(x) ((x) & 0xffff)
/* (ex)capability register */
#define IOMMU_ECAP_GET_C(x) ((x) & 0x1)
#define IOMMU_ECAP_GET_EIM(x) ((x) & 0x10)
#define IOMMU_ECAP_GET_IR(x) ((x) & 0x8)
#define IOMMU_ECAP_GET_DI(x) ((x) & 0x4)
#define IOMMU_ECAP_GET_QI(x) ((x) & 0x2)
/* iotlb invalidation */
#define TLB_IVA_LEAF 1
#define TLB_IVA_WHOLE 0
/* context invalidation */
/* global command register */
/* global status register */
/* psi address mask */
/* dmar fault event */
#define IOMMU_INTR_IPL (8)
#define IOMMU_REG_FEVNT_CON_IM_SHIFT (31)
/* iommu enable state */
#define DMAR_ENABLE 0x1
#define QINV_ENABLE 0x2
#define INTRR_ENABLE 0x4
/* invalidation queue table entry size */
#define QINV_ENTRY_SIZE 0x10
/* max value of Queue Size field of Invalidation Queue Address Register */
#define QINV_MAX_QUEUE_SIZE 0x7
/* status data size of invalidation wait descriptor */
#define QINV_SYNC_DATA_SIZE 0x4
/* status data value of invalidation wait descriptor */
#define QINV_SYNC_DATA_FENCE 1
#define QINV_SYNC_DATA_UNFENCE 2
/* invalidation queue head and tail */
#define QINV_IQA_TAIL_SHIFT 4
/* max value of Size field of Interrupt Remapping Table Address Register */
#define INTRR_MAX_IRTA_SIZE 0xf
/* interrupt remapping table entry size */
#define INTRR_RTE_SIZE 0x10
/* ioapic redirection table entry related shift of remappable interrupt */
#define INTRR_IOAPIC_IIDX_SHIFT 17
#define INTRR_IOAPIC_FORMAT_SHIFT 16
#define INTRR_IOAPIC_TM_SHIFT 15
#define INTRR_IOAPIC_POL_SHIFT 13
#define INTRR_IOAPIC_IIDX15_SHIFT 11
/* msi intr entry related shift of remappable interrupt */
#define INTRR_MSI_IIDX_SHIFT 5
#define INTRR_MSI_FORMAT_SHIFT 4
#define INTRR_MSI_SHV_SHIFT 3
#define INTRR_MSI_IIDX15_SHIFT 2
#define INTRR_DISABLE (void *)-1
/* page entry structure */
typedef struct iorce {
} *iorce_t;
/* kernel maintained page table entry */
typedef struct iovpte {
/*
* pointer to the cpu accessable
* iommu page table
*/
/*
* pointer to the real iommu
* page table
*/
} *iovpte_t;
/*
* struct iommu_kstat
* kstat tructure for iommu
*/
typedef struct iommu_kstat {
/* hardware dependent */
/* hardware independent */
/*
* struct iommu_stat
* statistics for iommu
*/
typedef struct iommu_stat {
} iommu_stat_t;
struct intel_iommu_state;
struct iommu_dvma_cookie;
struct dmar_domain_state;
/*
* invalidation granularity
*/
typedef enum {
TLB_INV_G_GLOBAL = 1,
} tlb_inv_g_t;
typedef enum {
CTT_INV_G_GLOBAL = 1,
} ctt_inv_g_t;
typedef enum {
IEC_INV_GLOBAL = 0,
} iec_inv_g_t;
/*
* struct dmar_ops
* dmar hardware operation functions
*/
struct dmar_ops {
/* enable */
/* page fault */
/* cache related */
/* root entry */
/* cpu cache line flush */
};
/*
* struct iotlb_cache_node
* the pending data for iotlb flush
*/
typedef struct iotlb_pend_node {
/* node to hook into the list */
/* ptr to dvma cookie array */
struct iommu_dvma_cookie *icn_dcookies;
/* valid cookie count */
/* array size */
/*
* struct iotlb_cache_head
* the pending head for the iotlb flush
*/
typedef struct iotlb_pend_head {
/* the pending iotlb list */
/* the pending node cache list */
struct inv_queue_state;
struct intr_remap_tbl_state;
struct iommu_pghdl;
#define IOMMU_PGHDL_HASH_SIZE (256)
/*
* struct intel_iommu_state
* This structure describes the state information
* of each iommu unit in the platform. It is cre-
* ated in the dmarnex driver's attach(), and will
* be used in every DMA DDI and the iommu transla-
* tion functions
*
* node - the list node to hook it in iommu_states
* iu_drhd - the related drhd
* iu_reg_handle - register access handler
* iu_reg_lock - lock to protect register operation
* iu_reg_address - virtual address of the register base address
* iu_capability - copy of the capability register
* iu_excapability - copy of the extention register
* iu_root_entry_paddr - root entry page table
* iu_root_context_lock - root context entry lock
* iu_gaw - guest address width
* iu_agaw - adjusted guest address width
* iu_level - the page table level
* iu_global_cmd_reg - global command register save place
* iu_max_domain - the maximum domain numbers
* iu_domain_id_hdl - domain id allocator handler
* iu_enabled - the soft state of the iommu
* iu_coherency - hardware access is coherent
* iu_kstat - kstat pointer
* iu_statistics - iommu statistics
* iu_dmar_ops - iommu operation functions
* iu_pend_head - pending iotlb list
* iu_inv_queue - invalidation queue state
* iu_intr_remap_tbl - interrupt remapping table state
* iu_pghdl_hash - hash of pages allocated for IOMMU internal work.
*/
typedef struct intel_iommu_state {
int iu_gaw;
int iu_agaw;
int iu_level;
int iu_max_domain;
struct dmar_ops *iu_dmar_ops;
struct inv_queue_state *iu_inv_queue;
struct intr_remap_tbl_state *iu_intr_remap_tbl;
/*
* struct dvma_cache_node
* dvma cache node
*/
typedef struct dvma_cache_node {
/* parameters */
/*
* struct dvma_cache_head
* dvma cache head
*/
typedef struct dvma_cache_head {
/* the list of the free dvma */
/* the cache for the node memory */
#define DVMA_CACHE_HEAD_CNT 64
/*
* struct dmar_domain_state
* This structure describes the state information
* of an iommu domain. It is created and initiated
* when the driver call ddi_dma_bind_handle(). And
* will be used in each iommu translation fucntions
*
* dm_domain_id - the domain id
* dm_iommu - iommu pointer this domain belongs to
* dm_dvma_map - dvma map
* dm_dvma_cache - dvma cahce lists
* dm_page_table_paddr - page table address for this domain
* dm_pgtable_lock - lock to protect changes to page table.
* dm_pt_tree - the kernel maintained page tables
* dm_identity - does this domain identity mapped
*/
typedef struct dmar_domain_state {
struct iovpte dm_pt_tree;
/*
* struct pci_dev_info
* pci device info structure
*/
typedef struct pci_dev_info {
int pdi_seg;
int pdi_bus;
int pdi_devfn;
#define IOMMU_PPB_NONE 0
#define IOMMU_PPB_PCIE_PCIE 1
#define IOMMU_PPB_PCIE_PCI 2
#define IOMMU_PPB_PCI_PCI 3
#define MAX_COOKIE_CACHE_SIZE 20
/*
* struct iommu_dvma_cookie
* this cookie record the dvma allocated for
* an individual device
*/
typedef struct iommu_dvma_cookie {
struct dmar_domain_state *dc_domain;
struct iommu_dvma_cookie *dc_next;
/*
* struct dvma_cookie_head
* the cookie cache head
*/
typedef struct dvma_cookie_head {
/* physical contigous pages for invalidation queue */
typedef struct inv_queue_mem {
/*
* invalidation queue state
* This structure describes the state information of the
* invalidation queue table and related status memeory for
* invalidation wait descriptor
*
* iq_table - invalidation queue table
* iq_sync - sync status memory for invalidation wait descriptor
* iotlb_pend_node - pending tlb node
*/
typedef struct inv_queue_state {
/* invalidation queue entry structure */
typedef struct inv_dsc {
} inv_dsc_t;
/* helper macro for making queue invalidation descriptor */
#define CC_INV_DSC_HIGH (0)
((uint64_t)(g) << 4) | \
1)
((uint64_t)(g) << 4) | \
2)
3)
#define IEC_INV_DSC_HIGH (0)
((uint64_t)(g) << 4) | \
4)
5)
/* save source id and iommu structure for ioapic */
typedef struct ioapic_iommu_info {
typedef struct intr_remap_private {
/* interrupt remapping table state info */
typedef struct intr_remap_tbl_state {
/* interrupt remapping table entry */
typedef struct intr_rte {
} intr_rte_t;
(p))
typedef enum {
SVT_NO_VERIFY = 0, /* no verification */
SVT_ALL_VERIFY, /* using sid and sq to verify */
SVT_BUS_VERIFY, /* verify #startbus and #endbus */
} intrr_svt_t;
typedef enum {
SQ_VERIFY_ALL = 0, /* verify all 16 bits */
SQ_VERIFY_IGR_1, /* ignore bit 3 */
SQ_VERIFY_IGR_2, /* ignore bit 2-3 */
SQ_VERIFY_IGR_3 /* ignore bit 1-3 */
} intrr_sq_t;
/*
* struct vmem_walk_arg
* the arg of vmem vmem walker
*/
typedef struct vmem_walk_arg {
#ifdef __cplusplus
}
#endif
#endif /* _SYS_INTEL_IOMMU_H */