immu.h revision 50200e773f0242e336d032a7b43485e1bcfc9bfe
9a016c63ca347047a236dff12f0da83aac8981d1stevel * CDDL HEADER START
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9a016c63ca347047a236dff12f0da83aac8981d1stevel * Portions Copyright (c) 2010, Oracle and/or its affiliates.
9a016c63ca347047a236dff12f0da83aac8981d1stevel * All rights reserved.
9a016c63ca347047a236dff12f0da83aac8981d1stevel * Copyright (c) 2008, Intel Corporation.
9a016c63ca347047a236dff12f0da83aac8981d1stevel * All rights reserved.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * Intel IOMMU implementation specific state
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dhextern "C" {
9a016c63ca347047a236dff12f0da83aac8981d1stevel * Some ON drivers have bugs. Keep this define until all such drivers
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * have been fixed
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh/* PD(T)E entries */
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_BTOP(b) (((uint64_t)b) >> IMMU_PAGESHIFT)
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_PTOB(p) (((uint64_t)p) << IMMU_PAGESHIFT)
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_BTOPR(x) ((((x) + IMMU_PAGEOFFSET) >> IMMU_PAGESHIFT))
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_ROUNDUP(size) (((size) + IMMU_PAGEOFFSET) & ~IMMU_PAGEOFFSET)
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_ROUNDOWN(addr) ((addr) & ~IMMU_PAGEOFFSET)
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_PGTABLE_LEVEL_MASK ((1<<IMMU_PGTABLE_LEVEL_STRIDE) - 1)
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_PGTABLE_OFFSHIFT (IMMU_PAGESHIFT - IMMU_PGTABLE_LEVEL_STRIDE)
9a016c63ca347047a236dff12f0da83aac8981d1stevel#define IMMU_PGTABLE_MAXIDX ((IMMU_PAGESIZE / sizeof (hw_pdte_t)) - 1)
9a016c63ca347047a236dff12f0da83aac8981d1stevel * DMAR global defines
9a016c63ca347047a236dff12f0da83aac8981d1stevel/* DMAR unit types */
9a016c63ca347047a236dff12f0da83aac8981d1stevel/* DRHD flag values */
9a016c63ca347047a236dff12f0da83aac8981d1stevel/* Device scope types */
9a016c63ca347047a236dff12f0da83aac8981d1stevel/* Forward declarations for IOMMU state structure and DVMA domain struct */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * The following structure describes the formate of DMAR ACPI table format.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * They are used to parse DMAR ACPI table. Read the spec for the meaning
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * of each member.
9a016c63ca347047a236dff12f0da83aac8981d1stevel/* lengths of various strings */
9a016c63ca347047a236dff12f0da83aac8981d1steveltypedef struct dmar_table {
int tbl_rawlen;
} dmar_table_t;
typedef struct drhd {
} drhd_t;
typedef struct rmrr {
} rmrr_t;
typedef struct scope {
} scope_t;
typedef struct ioapic_drhd {
typedef struct memrng {
} memrng_t;
typedef enum immu_flags {
} immu_flags_t;
typedef enum cont_avail {
} cont_avail_t;
#define TLB_IVA_WHOLE 0
typedef enum iotlb_inv {
typedef enum context_inv {
} tlb_inv_g_t;
} ctt_inv_g_t;
IEC_INV_GLOBAL = 0,
} iec_inv_g_t;
struct inv_queue_state;
struct intrmap_tbl_state;
typedef struct pgtable {
} pgtable_t;
typedef struct intrmap {
} intrmap_t;
typedef struct hw_rce {
} hw_rce_t;
struct immu_flushops;
typedef struct immu_inv_wait {
typedef struct immu_dcookie {
typedef struct immu {
char *immu_name;
void *immu_dmar_unit;
int immu_dvma_gaw;
int immu_dvma_agaw;
int immu_dvma_nlevels;
int immu_max_domains;
void *immu_qinv;
} immu_t;
typedef enum immu_maptype {
typedef struct domain {
} domain_t;
typedef enum immu_pcib {
IMMU_PCIB_BAD = 0,
} immu_pcib_t;
typedef struct immu_devi {
int imd_seg;
int imd_bus;
int imd_devfunc;
int imd_sec;
int imd_sub;
} immu_devi_t;
typedef struct immu_arg {
int ima_seg;
int ima_bus;
int ima_devfunc;
} immu_arg_t;
typedef struct immu_hdl_private {
int ihp_npremapped;
struct immu_flushops {
immu_inv_wait_t *);
immu_inv_wait_t *);
#define immu_flush_context_fsi(i, f, s, d, w) \
#define immu_flush_context_dsi(i, d, w) \
#define immu_flush_context_gbl(i, w) \
#define immu_flush_iotlb_psi(i, d, v, c, h, w) \
#define immu_flush_iotlb_dsi(i, d, w) \
#define immu_flush_iotlb_gbl(i, w) \
#define immu_flush_wait(i, w) \
extern int immu_use_tm;
extern int immu_use_alh;
void immu_init(void);
void immu_startup(void);
void immu_shutdown(void);
void immu_destroy(void);
void immu_device_tree_changed(void);
int immu_quiesce(void);
int immu_unquiesce(void);
/* immu_dmar.c interfaces */
int immu_dmar_setup(void);
int immu_dmar_parse(void);
void immu_dmar_startup(void);
void immu_dmar_shutdown(void);
void immu_dmar_destroy(void);
void immu_dmar_rmrr_map(void);
/* immu.c interfaces */
/* immu_regs.c interfaces */
/* immu_dvma.c interfaces */
/* immu_intrmap.c interfaces */
/* immu_qinv.c interfaces */
immu_inv_wait_t *);
#ifdef DEBUG
#ifdef __cplusplus