immu.h revision 3a634bfc9a31448c742688c603d3e76b83b041a0
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * CDDL HEADER START
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f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * CDDL HEADER END
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * Portions Copyright 2010 Sun Microsystems, Inc. All rights reserved.
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * Use is subject to license terms.
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * Copyright (c) 2008, Intel Corporation.
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * All rights reserved.
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * Intel IOMMU implementation specific state
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * Some ON drivers have bugs. Keep this define until all such drivers
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * have been fixed
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* PD(T)E entries */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_BTOP(b) (((uint64_t)b) >> IMMU_PAGESHIFT)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_PTOB(p) (((uint64_t)p) << IMMU_PAGESHIFT)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_ROUNDUP(size) (((size) + IMMU_PAGEOFFSET) & ~IMMU_PAGEOFFSET)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_ROUNDOWN(addr) ((addr) & ~IMMU_PAGEOFFSET)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_PGTABLE_LEVEL_MASK ((1<<IMMU_PGTABLE_LEVEL_STRIDE) - 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_PGTABLE_OFFSHIFT (IMMU_PAGESHIFT - IMMU_PGTABLE_LEVEL_STRIDE)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_PGTABLE_MAXIDX ((IMMU_PAGESIZE / sizeof (hw_pdte_t)) - 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_ROUNDUP(size) (((size) + IMMU_PAGEOFFSET) & ~IMMU_PAGEOFFSET)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_ROUNDOWN(addr) ((addr) & ~IMMU_PAGEOFFSET)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * DMAR global defines
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* DMAR unit types */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* DRHD flag values */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* Device scope types */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* Forward declarations for IOMMU state structure and DVMA domain struct */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * The following structure describes the formate of DMAR ACPI table format.
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * They are used to parse DMAR ACPI table. Read the spec for the meaning
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * of each member.
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* lengths of various strings */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct dmar_table {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct drhd {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby kmutex_t dr_lock; /* protects the dmar field */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct rmrr {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * Macros based on PCI spec
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_PCI_DEV(devfunc) ((uint64_t)devfunc >> 3) /* from devfunc */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_PCI_FUNC(devfunc) (devfunc & 7) /* get func from devfunc */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_PCI_DEVFUNC(d, f) (((d) << 3) | (f)) /* create devfunc */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct scope {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * interrupt source id and drhd info for ioapic
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct ioapic_drhd {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct memrng {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* Size of root and context tables and their entries */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* register offset */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_VERSION (0x00) /* Version Rigister, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_CAP (0x08) /* Capability Register, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_EXCAP (0x10) /* Extended Capability Reg, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_GLOBAL_CMD (0x18) /* Global Command Register, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_GLOBAL_STS (0x1C) /* Global Status Register, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_ROOTENTRY (0x20) /* Root-Entry Table Addr Reg, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_CONTEXT_CMD (0x28) /* Context Comand Register, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_FAULT_STS (0x34) /* Fault Status Register, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_FEVNT_CON (0x38) /* Fault Event Control Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_FEVNT_DATA (0x3C) /* Fault Event Data Register, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_FEVNT_ADDR (0x40) /* Fault Event Address Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_FEVNT_UADDR (0x44) /* Fault Event Upper Addr Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_AFAULT_LOG (0x58) /* Advanced Fault Log Reg, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_PMER (0x64) /* Protected Memory Enble Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_PLMBR (0x68) /* Protected Low Mem Base Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_PLMLR (0x6C) /* Protected Low Mem Lim Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_PHMBR (0X70) /* Protectd High Mem Base Reg, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_PHMLR (0x78) /* Protected High Mem Lim Reg, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_QH (0x80) /* Invalidation Queue Head, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_QT (0x88) /* Invalidation Queue Tail, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_QAR (0x90) /* Invalidtion Queue Addr Reg, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_CSR (0x9C) /* Inval Compl Status Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_CECR (0xA0) /* Inval Compl Evnt Ctrl Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_CEDR (0xA4) /* Inval Compl Evnt Data Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_CEAR (0xA8) /* Inval Compl Event Addr Reg, 32 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_INVAL_CEUAR (0xAC) /* Inval Comp Evnt Up Addr reg, 32bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_REG_IRTAR (0xB8) /* INTR Remap Tbl Addr Reg, 64 bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* ioapic memory region */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* fault register */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_FAULT_GET_INDEX(x) ((((uint64_t)x) >> 8) & 0xff)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_FRR_GET_FR(x) ((((uint64_t)x) >> 32) & 0xff)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_FRR_GET_FT(x) ((((uint64_t)x) >> 62) & 0x1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* (ex)capability register */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_NFR(x) (((((uint64_t)x) >> 40) & 0xff) + 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_DWD(x) ((((uint64_t)x) >> 54) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_DRD(x) ((((uint64_t)x) >> 55) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_PSI(x) ((((uint64_t)x) >> 39) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_SPS(x) ((((uint64_t)x) >> 34) & 0xf)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_ISOCH(x) ((((uint64_t)x) >> 23) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_ZLR(x) ((((uint64_t)x) >> 22) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_MAMV(x) ((((uint64_t)x) >> 48) & 0x3f)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_CM(x) ((((uint64_t)x) >> 7) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_PHMR(x) ((((uint64_t)x) >> 6) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_PLMR(x) ((((uint64_t)x) >> 5) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_RWBF(x) ((((uint64_t)x) >> 4) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_AFL(x) ((((uint64_t)x) >> 3) & 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_GET_FRO(x) (((((uint64_t)x) >> 24) & 0x3ff) * 16)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_MGAW(x) (((((uint64_t)x) >> 16) & 0x3f) + 1)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_SAGAW(x) ((((uint64_t)x) >> 8) & 0x1f)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_CAP_ND(x) (1 << (((x) & 0x7) *2 + 4)) -1
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_ECAP_GET_IRO(x) (((((uint64_t)x) >> 8) & 0x3ff) << 4)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_ECAP_GET_MHMV(x) (((uint64_t)x >> 20) & 0xf)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* iotlb invalidation */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define TLB_INV_GET_IAIG(x) ((((uint64_t)x) >> 57) & 7)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define TLB_INV_DRAIN_READ (((uint64_t)1) << 49)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define TLB_INV_DRAIN_WRITE (((uint64_t)1) << 48)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define TLB_INV_DID(x) (((uint64_t)((x) & 0xffff)) << 32)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* dont use value 0 for enums - to catch unit 8 */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* context invalidation */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CCMD_INV_DID(x) ((uint64_t)((x) & 0xffff))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CCMD_INV_SID(x) (((uint64_t)((x) & 0xffff)) << 16)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CCMD_INV_FM(x) (((uint64_t)((x) & 0x3)) << 32)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* global command register */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* global status register */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* psi address mask */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define ADDR_AM_OFFSET(n, m) ((n) & (ADDR_AM_MAX(m) - 1))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* dmar fault event */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define IMMU_ALLOC_RESOURCE_DELAY (drv_usectohz(5000))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* max value of Size field of Interrupt Remapping Table Address Register */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* interrupt remapping table entry size */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* ioapic redirection table entry related shift of remappable interrupt */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* msi intr entry related shift of remappable interrupt */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby * invalidation granularity
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef enum {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef enum {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef enum {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* A software page table structure */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct pgtable {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby list_node_t swpg_domain_node; /* domain list of pgtables */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* interrupt remapping table state info */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct intrmap {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltbytypedef struct hw_rce {
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define ROOT_GET_CONT(hrent) ((hrent)->lo & ~(0xFFF))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define ROOT_SET_CONT(hrent, paddr) ((hrent)->lo |= (paddr & (~0xFFF)))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_GET_DID(hcent) ((((uint64_t)(hcent)->hi) >> 8) & 0xFFFF)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_SET_DID(hcent, did) ((hcent)->hi |= ((0xFFFF & (did)) << 8))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_GET_AVAIL(hcent) ((((uint64_t)((hcent)->hi)) >> 0x3) & 0xF)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_SET_AVAIL(hcent, av) ((hcent)->hi |= ((0xF & (av)) << 0x3))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_GET_LO_AW(hcent) (30 + 9 *((hcent)->hi & 0x7))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby ((CONT_GET_LO_AW(hcent) == 66) ? 64 : CONT_GET_LO_AW(hcent))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby ((hcent)->hi |= (((((aw) + 2) - 30) / 9) & 0x7))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_GET_ASR(hcent) ((hcent)->lo & ~(0xFFF))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_SET_ASR(hcent, paddr) ((hcent)->lo |= (paddr & (~0xFFF)))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_GET_TTYPE(hcent) ((((uint64_t)(hcent)->lo) >> 0x2) & 0x3)
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define CONT_SET_TTYPE(hcent, ttype) ((hcent)->lo |= (((ttype) & 0x3) << 0x2))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby/* we use the bit 63 (available for system SW) as a present bit */
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define PDTE_SW4(hw_pdte) ((hw_pdte) & ((uint64_t)1<<63))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define PDTE_CLEAR_SW4(hw_pdte) ((hw_pdte) &= ~((uint64_t)1<<63))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define PDTE_P(hw_pdte) ((hw_pdte) & ((uint64_t)1<<63))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define PDTE_CLEAR_P(hw_pdte) ((hw_pdte) &= ~((uint64_t)1<<63))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define PDTE_SET_P(hw_pdte) ((hw_pdte) |= ((uint64_t)1<<63))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define PDTE_TM(hw_pdte) ((hw_pdte) & ((uint64_t)1<<62))
f6e214c7418f43af38bd8c3a557e3d0a1d311cfaGavin Maltby#define PDTE_CLEAR_TM(hw_pdte) ((hw_pdte) &= ~((uint64_t)1<<62))
typedef struct immu {
char *immu_name;
void *immu_dmar_unit;
int immu_dvma_gaw;
int immu_dvma_agaw;
int immu_dvma_nlevels;
int immu_max_domains;
void *immu_qinv;
} immu_t;
typedef enum immu_maptype {
typedef struct domain {
} domain_t;
typedef enum immu_pcib {
IMMU_PCIB_BAD = 0,
} immu_pcib_t;
typedef struct immu_devi {
int imd_seg;
int imd_bus;
int imd_devfunc;
int imd_sec;
int imd_sub;
} immu_devi_t;
typedef struct immu_arg {
int ima_seg;
int ima_bus;
int ima_devfunc;
} immu_arg_t;
void immu_init(void);
void immu_startup(void);
void immu_shutdown(void);
void immu_destroy(void);
void immu_device_tree_changed(void);
int immu_quiesce(void);
int immu_unquiesce(void);
/* functions in rootnex.c */
/* immu_dmar.c interfaces */
int immu_dmar_setup(void);
int immu_dmar_parse(void);
void immu_dmar_startup(void);
void immu_dmar_shutdown(void);
void immu_dmar_destroy(void);
void immu_dmar_rmrr_map(void);
/* immu.c interfaces */
/* immu_regs.c interfaces */
/* immu_dvma.c interfaces */
/* immu_intrmap.c interfaces */
/* immu_qinv.c interfaces */
#ifdef __cplusplus