trap.c revision 7ff178cd8db129d385d3177eb20744d3b6efc59b
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
/* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
/* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
/* All Rights Reserved */
/* */
/* Copyright (c) 1987, 1988 Microsoft Corporation */
/* All Rights Reserved */
/* */
#include <sys/sysmacros.h>
#include <sys/mutex_impl.h>
#include <sys/machsystm.h>
#include <sys/archsystm.h>
#include <vm/seg_kmem.h>
#include <sys/debugreg.h>
#include <sys/aio_impl.h>
#include <sys/tnf_probe.h>
#include <sys/x86_archext.h>
#include <sys/traptrace.h>
#include <sys/cpc_impl.h>
#include <sys/bootconf.h>
#include <sys/bootinfo.h>
#include <sys/mach_mmu.h>
#if defined(__xpv)
#include <sys/hypervisor.h>
#endif
static const char *trap_type_mnemonic[] = {
"de", "db", "2", "bp",
"of", "br", "ud", "nm",
"df", "9", "ts", "np",
"ss", "gp", "pf", "15",
"mf", "ac", "mc", "xf"
};
static const char *trap_type[] = {
"Divide error", /* trap id 0 */
"Debug", /* trap id 1 */
"NMI interrupt", /* trap id 2 */
"Breakpoint", /* trap id 3 */
"Overflow", /* trap id 4 */
"BOUND range exceeded", /* trap id 5 */
"Invalid opcode", /* trap id 6 */
"Device not available", /* trap id 7 */
"Double fault", /* trap id 8 */
"Coprocessor segment overrun", /* trap id 9 */
"Invalid TSS", /* trap id 10 */
"Segment not present", /* trap id 11 */
"Stack segment fault", /* trap id 12 */
"General protection", /* trap id 13 */
"Page fault", /* trap id 14 */
"Reserved", /* trap id 15 */
"x87 floating point error", /* trap id 16 */
"Alignment check", /* trap id 17 */
"Machine check", /* trap id 18 */
"SIMD floating point exception", /* trap id 19 */
};
#define SLOW_SCALL_SIZE 2
#define FAST_SCALL_SIZE 2
int tudebug = 0;
int tudebugbpt = 0;
int tudebugfpe = 0;
int tudebugsse = 0;
int tdebug = 0;
int lodebug = 0;
int faultdebug = 0;
#else
#define tdebug 0
#define lodebug 0
#define faultdebug 0
#endif /* defined(TRAPDEBUG) || defined(lint) */
#if defined(TRAPTRACE)
/*
* trap trace record for cpu0 is allocated here.
* trap trace records for non-boot cpus are allocated in mp_startup_init().
*/
{
(uintptr_t)0 /* current */
},
};
/*
* default trap buffer size
*/
int trap_trace_freeze = 0;
int trap_trace_off = 0;
/*
* A dummy TRAPTRACE entry to use after death.
*/
static void dump_ttrace(void);
#endif /* TRAPTRACE */
static int kern_gpfault(struct regs *);
/*ARGSUSED*/
static int
{
struct panic_trap_info ti;
const char *trap_name, *trap_mnemonic;
if (type < TRAP_TYPES) {
} else {
trap_name = "trap";
trap_mnemonic = "-";
}
#ifdef TRAPTRACE
#endif
panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p "
"occurred in module \"%s\" due to %s",
"a NULL pointer dereference" :
"an illegal access to a user address");
} else
panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p",
return (0);
}
/*
* Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction.
*
* int <vector> is two bytes: 0xCD <vector>
*/
static int
{
return (1);
return (0);
}
/*
* Test to see if the instruction at pc is sysenter or syscall. The second
* argument should be the x86 feature flag corresponding to the expected
* instruction.
*
* sysenter is two bytes: 0x0F 0x34
* syscall is two bytes: 0x0F 0x05
* int $T_SYSCALLINT is two bytes: 0xCD 0x91
*/
static int
{
return (0);
switch (which) {
case X86_SEP:
return (1);
break;
case X86_ASYSC:
return (1);
break;
case 0xCD:
return (1);
break;
}
return (0);
}
static const char *
{
switch (syscall_insn) {
case X86_SEP:
return ("sysenter");
case X86_ASYSC:
return ("syscall");
case 0xCD:
return ("int");
default:
return ("Unknown");
}
}
static int
{
int return_code = 0;
/*
* If another thread beat us here, it already changed
* this site to the slower (int) syscall instruction.
*/
return_code = 1;
if (rewrite_syscall(linearpc) == 0) {
return_code = 1;
}
#ifdef DEBUG
else
"instruction in process %d",
p->p_pid);
#endif /* DEBUG */
}
}
return (return_code);
}
/*
* Test to see if the instruction at pc is a system call instruction.
*
* The bytes of an lcall instruction used for the syscall trap.
* static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 };
* static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 };
*/
#define LCALLSIZE 7
static int
{
instr[0] == 0x9a &&
instr[1] == 0 &&
instr[2] == 0 &&
instr[3] == 0 &&
instr[4] == 0 &&
instr[6] == 0)
return (1);
return (0);
}
#ifdef __amd64
/*
* In the first revisions of amd64 CPUs produced by AMD, the LAHF and
* SAHF instructions were not implemented in 64-bit mode. Later revisions
* did implement these instructions. An extension to the cpuid instruction
* was added to check for the capability of executing these instructions
* in 64-bit mode.
*
* Intel originally did not implement these instructions in EM64T either,
* but added them in later revisions.
*
* So, there are different chip revisions by both vendors out there that
* may or may not implement these instructions. The easy solution is to
* just always emulate these instructions on demand.
*
* SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e)
* LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f)
*/
#define LSAHFSIZE 1
static int
{
return (1);
return (0);
}
/*
* Emulate the LAHF and SAHF instructions. The reference manuals define
* as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P).
*
* Note that %ah is bits 8-15 of %rax.
*/
static void
{
if (instr == 0x9e) {
/* sahf. Copy bits from %ah to flags. */
} else {
/* lahf. Copy bits from flags to %ah. */
}
}
#endif /* __amd64 */
#ifdef OPTERON_ERRATUM_91
/*
* Test to see if the instruction at pc is a prefetch instruction.
*
* The first byte of prefetch instructions is always 0x0F.
* The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch.
* The third byte (ModRM) contains the register field bits (bits 3-5).
* These bits must be between 0 and 3 inclusive for regular prefetch and
* 0 and 1 inclusive for AMD 3dnow prefetch.
*
* In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F).
*/
static int
{
#ifdef _LP64
if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */
p++;
#endif
return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) ||
(p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1));
}
static int
{
}
#endif /* OPTERON_ERRATUM_91 */
/*
* Called from the trap handler when a processor trap occurs.
*
* Note: All user-level traps that might call stop() must exit
* trap() by 'goto out' or by falling through.
* Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1)
* however, there are paths that arrive here with PS_IE == 0 so special care
* must be taken in those cases.
*/
void
{
unsigned type;
enum fault_type fault_type;
int mstate;
int sicode = 0;
int watchcode;
int watchpage;
int singlestep_twiddle;
int ta;
#ifdef __amd64
#endif
if (errcode & PF_ERR_WRITE)
else
#if defined(__i386)
/*
* Pentium Pro work-around
*/
== -1) {
errcode &= ~PF_ERR_PROT;
} else {
!(attr & PROT_WRITE);
if (!priv_violation && !access_violation)
goto cleanup;
}
}
#endif /* __i386 */
if (tdebug)
/*
* Set up the current cred to use during this trap. u_cred
* no longer exists. t_cred is used instead.
* The current process credential applies to the thread for
* the entire trap. If trapping from the kernel, this
* should already be set up.
*/
/*
* DTrace accesses t_cred in probe context. t_cred
* must always be either NULL, or point to a valid,
* allocated cred structure.
*/
}
switch (type) {
mstate = LMS_TFAULT;
else
mstate = LMS_DFAULT;
break;
default:
break;
}
/* Kernel probe */
}
switch (type) {
case T_SGLSTP:
break;
default:
FTRACE_2("trap(): type=0x%lx, regs=0x%lx",
break;
}
switch (type) {
case T_SIMDFPE:
/* Make sure we enable interrupts before die()ing */
sti(); /* The SIMD exception comes in via cmninttrap */
/*FALLTHROUGH*/
default:
if (tudebug)
printf("trap: Unknown trap type %d in user mode\n",
break;
} else {
/*NOTREACHED*/
}
case T_PGFLT: /* system page fault */
/*
* set ot_trap and bounce back to the on_trap() call site
* via the installed trampoline.
*/
goto cleanup;
}
/*
* See if we can handle as pagefault. Save lofault
* across this. Here we assume that an address
* less than KERNELBASE is a user fault.
* We can do this as copy.s routines verify that the
* starting address is less than KERNELBASE before
* starting and because we know that we always have
* KERNELBASE mapped as invalid to serve as a "barrier".
*/
addr < p->p_usrstack &&
res = 0;
} else {
}
/*
* Restore lofault. If we resolved the fault, exit.
* If we didn't and lofault wasn't set, die.
*/
if (res == 0)
goto cleanup;
#if defined(OPTERON_ERRATUM_93) && defined(_LP64)
if (lofault == 0 && opteron_erratum_93) {
/*
* Workaround for Opteron Erratum 93. On return from
* a System Managment Interrupt at a HLT instruction
* the %rip might be truncated to a 32 bit value.
* BIOS is supposed to fix this, but some don't.
* If this occurs we simply restore the high order bits.
* The HLT instruction is 1 byte of 0xf4.
*/
PFN_INVALID &&
goto cleanup;
}
}
}
#endif /* OPTERON_ERRATUM_93 && _LP64 */
#ifdef OPTERON_ERRATUM_91
if (lofault == 0 && opteron_erratum_91) {
/*
* Workaround for Opteron Erratum 91. Prefetches may
* generate a page fault (they're not supposed to do
* that!). If this occurs we simply return back to the
* instruction.
*/
/*
* If the faulting PC is not mapped, this is a
* legitimate kernel page fault that must result in a
* panic. If the faulting PC is mapped, it could contain
* a prefetch instruction. Check for that here.
*/
#ifdef DEBUG
"occurred: kernel prefetch"
" at %p generated a page fault!",
#endif /* DEBUG */
goto cleanup;
}
}
}
#endif /* OPTERON_ERRATUM_91 */
if (lofault == 0)
/*
* Cannot resolve fault. Return to lofault.
*/
if (lodebug) {
}
else
goto cleanup;
if (faultdebug) {
char *fault_str;
switch (rw) {
case S_READ:
fault_str = "read";
break;
case S_WRITE:
fault_str = "write";
break;
case S_EXEC:
fault_str = "exec";
break;
default:
fault_str = "";
break;
}
printf("user %s fault: addr=0x%lx errcode=0x%x\n",
}
#if defined(OPTERON_ERRATUM_100) && defined(_LP64)
/*
* Workaround for AMD erratum 100
*
* A 32-bit process may receive a page fault on a non
* 32-bit address by mistake. The range of the faulting
* address will be
*
* 0xffffffff80000000 .. 0xffffffffffffffff or
* 0x0000000100000000 .. 0x000000017fffffff
*
* The fault is always due to an instruction fetch, however
* the value of r_pc should be correct (in 32 bit range),
* so we ignore the page fault on the bogus address.
*/
if (p->p_model == DATAMODEL_ILP32 &&
if (!opteron_erratum_100)
panic("unexpected erratum #100");
goto out;
}
#endif /* OPTERON_ERRATUM_100 && _LP64 */
#ifdef __i386
/*
* In 32-bit mode, the lcall (system call) instruction fetches
* one word from the stack, at the stack pointer, because of the
* way the call gate is constructed. This is a bogus
* read and should not be counted as a read watchpoint.
* We work around the problem here by testing to see if
* this situation applies and, if so, simply jumping to
* the code in locore.s that fields the system call trap.
* The registers on the stack are already set up properly
* due to the match between the call gate sequence and the
* trap gate sequence. We just have to adjust the pc.
*/
extern void watch_syscall(void);
watch_syscall(); /* never returns */
/* NOTREACHED */
}
#endif /* __i386 */
if (ta) {
} else {
siginfo.si_trapafter = 0;
break;
}
} else {
/* XXX pr_watch_emul() never succeeds (for now) */
goto out;
}
/*
* If pagefault() succeeded, ok.
* Otherwise attempt to grow the stack.
*/
if (res == 0 ||
addr < p->p_usrstack &&
}
goto out;
report_stack_exec(p, addr);
}
#ifdef OPTERON_ERRATUM_91
/*
* Workaround for Opteron Erratum 91. Prefetches may generate a
* page fault (they're not supposed to do that!). If this
* occurs we simply return back to the instruction.
*
* We rely on copyin to properly fault in the page with r_pc.
*/
if (opteron_erratum_91 &&
#ifdef DEBUG
"prefetch at %p in pid %d generated a trap!",
#endif /* DEBUG */
goto out;
}
#endif /* OPTERON_ERRATUM_91 */
if (tudebug)
/*
* In the case where both pagefault and grow fail,
* set the code to the value provided by pagefault.
* We map all errors returned from pagefault() to SIGSEGV.
*/
case FC_HWERR:
case FC_NOSUPPORT:
break;
case FC_ALIGN:
break;
case FC_OBJERR:
}
break;
default: /* FC_NOMAP or FC_PROT */
break;
}
break;
/*
* If the syscall instruction is disabled due to LDT usage, a
* user program that attempts to execute it will trigger a #ud
* trap. Check for that case here. If this occurs on a CPU which
* doesn't even support syscall, the result of all of this will
* be to emulate that particular instruction.
*/
goto out;
#ifdef __amd64
/*
* Emulate the LAHF and SAHF instructions if needed.
* See the instr_is_lsahf function for details.
*/
if (p->p_model == DATAMODEL_LP64 &&
goto out;
}
#endif
/*FALLTHROUGH*/
if (tudebug)
break;
if (tudebug && tudebugfpe)
break;
if (tudebug && tudebugfpe)
break;
if (tudebug && tudebugfpe)
if (fpnoextflt(rp)) {
}
break;
case T_EXTOVRFLT: /* extension overrun fault */
/* check if we took a kernel trap on behalf of user */
{
extern void ndptrap_frstor(void);
sti(); /* T_EXTOVRFLT comes in via cmninttrap */
}
}
/*FALLTHROUGH*/
if (tudebug && tudebugfpe)
if (fpextovrflt(rp)) {
}
break;
case T_EXTERRFLT: /* x87 floating point exception pending */
/* check if we took a kernel trap on behalf of user */
{
extern void ndptrap_frstor(void);
sti(); /* T_EXTERRFLT comes in via cmninttrap */
}
}
/*FALLTHROUGH*/
if (tudebug && tudebugfpe)
}
break;
if (tudebug && tudebugsse)
/*
* There are rumours that some user instructions
* on older CPUs can cause this trap to occur; in
* which case send a SIGILL instead of a SIGFPE.
*/
}
sti(); /* The SIMD exception comes in via cmninttrap */
break;
case T_BPTFLT: /* breakpoint trap */
/*
* Kernel breakpoint traps should only happen when kmdb is
* active, and even then, it'll have interposed on the IDT, so
* control won't get here. If it does, we've hit a breakpoint
* without the debugger, which is very strange, and very
* fatal.
*/
if (tudebug && tudebugbpt)
break;
/* Now evaluate how we got here */
/*
* i386 single-steps even through lcalls which
* change the privilege level. So we take a trap at
* the first instruction in privileged mode.
*
* Set a flag to indicate that upon completion of
* the system call, deal with the single-step trap.
*
* The same thing happens for sysenter, too.
*/
singlestep_twiddle = 0;
singlestep_twiddle = 1;
#if defined(__amd64)
/*
* Since we are already on the kernel's
* %gs, on 64-bit systems the sysenter case
* needs to adjust the pc to avoid
* executing the swapgs instruction at the
* top of the handler.
*/
else
#endif
}
#if defined(__i386)
singlestep_twiddle = 1;
}
#endif
else {
if (tudebug && tudebugbpt)
}
if (singlestep_twiddle) {
goto cleanup;
}
}
/* XXX - needs review on debugger interface? */
debug_enter((char *)NULL);
else
break;
case T_NMIFLT: /* NMI interrupt */
printf("Unexpected NMI in system mode\n");
goto cleanup;
printf("Unexpected NMI in user mode\n");
break;
case T_GPFLT: /* general protection violation */
/*
* Any #GP that occurs during an on_trap .. no_trap bracket
* with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection,
* or in a on_fault .. no_fault bracket, is forgiven
* and we trampoline. This protection is given regardless
* of whether we are 32/64 bit etc - if a distinction is
* required then define new on_trap protection types.
*
* On amd64, we can get a #gp from referencing addresses
* in the virtual address hole e.g. from a copyin or in
* update_sregs while updating user segment registers.
*
* On the 32-bit hypervisor we could also generate one in
* mfn_to_pfn by reaching around or into where the hypervisor
* lives which is protected by segmentation.
*/
/*
* set ot_trap and trampoline back to the on_trap() call site
* for OT_DATA_ACCESS or OT_SEGMENT_ACCESS.
*/
if (ttype != 0) {
if (tudebug)
goto cleanup;
}
}
/*
* If we're under lofault protection (copyin etc.),
* longjmp back to lofault with an EFAULT.
*/
/*
* Fault is not resolvable, so just return to lofault
*/
if (lodebug) {
}
goto cleanup;
}
/*
* We fall through to the next case, which repeats
* the OT_SEGMENT_ACCESS check which we've already
* done, so we'll always fall through to the
* T_STKFLT case.
*/
/*FALLTHROUGH*/
case T_SEGFLT: /* segment not present fault */
/*
* One example of this is #NP in update_sregs while
* attempting to update a user segment register
* that points to a descriptor that is marked not
* present.
*/
if (tudebug)
goto cleanup;
}
/*FALLTHROUGH*/
case T_STKFLT: /* stack fault */
case T_TSSFLT: /* invalid TSS fault */
if (tudebug)
if (kern_gpfault(rp))
goto cleanup;
/*
* ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps
* should have no need for them, so we put a stop to it here.
*
* So: not-present fault is ONLY valid for 32-bit processes with
* a private LDT trying to do a system call. Emulate it.
*
* #gp fault is ONLY valid for 32-bit processes also, which DO NOT
* have a private LDT, and are trying to do a system call. Emulate it.
*/
#ifdef _SYSCALL32_IMPL
if (p->p_model != DATAMODEL_NATIVE) {
#endif /* _SYSCALL32_IMPL */
/*
* The user attempted a system call via the obsolete
* call gate mechanism. Because the process doesn't have
* an LDT (i.e. the ldtr contains 0), a #gp results.
* Emulate the syscall here, just as we do above for a
* #np trap.
*/
/*
* Since this is a not-present trap, rp->r_pc points to
* the trapping lcall instruction. We need to bump it
* to the next insn so the app can continue on.
*/
/*
* Normally the microstate of the LWP is forced back to
* LMS_USER by the syscall handlers. Emulate that
* behavior here.
*/
dosyscall();
goto out;
}
}
#ifdef _SYSCALL32_IMPL
}
#endif /* _SYSCALL32_IMPL */
/*
* If the current process is using a private LDT and the
* trapping instruction is sysenter, the sysenter instruction
* has been disabled on the CPU because it destroys segment
* registers. If this is the case, rewrite the instruction to
* be a safe system call and retry it. If this occurs on a CPU
* which doesn't even support sysenter, the result of all of
* this will be to emulate that particular instruction.
*/
goto out;
/*FALLTHROUGH*/
if (tudebug)
break;
if (tudebug)
break;
if (tudebug && tudebugbpt)
/* Was it single-stepping? */
/*
* If both NORMAL_STEP and WATCH_STEP are in effect,
* give precedence to WATCH_STEP. If neither is set,
* user must have set the PS_T bit in %efl; treat this
* as NORMAL_STEP.
*/
}
}
break;
if (tudebug && tudebugbpt)
/*
* int 3 (the breakpoint instruction) leaves the pc referring
* to the address one byte after the breakpointed address.
* If the P_PR_BPTADJ flag has been set via /proc, We adjust
* it back so it refers to the breakpointed address.
*/
if (p->p_proc_flag & P_PR_BPTADJ)
break;
case T_AST:
/*
* This occurs only after the cs register has been made to
* look like a kernel selector, either through debugging or
* possibly by functions like setcontext(). The thread is
* about to cause a general protection fault at common_iret()
* in locore. We let that happen immediately instead of
* doing the T_AST processing.
*/
goto cleanup;
p);
contract_process_hwerr(p->p_ct_process, p);
if (kcpc_overflow_ast()) {
/*
* Signal performance counter overflow
*/
if (tudebug)
}
}
break;
}
/*
* We can't get here from a system trap
*/
if (fault) {
/* We took a fault so abort single step. */
/*
* Remember the fault and fault adddress
* for real-time (SIGPROF) profiling.
*/
/*
* If a debugger has declared this fault to be an
* event of interest, stop the lwp. Otherwise just
* deliver the associated signal.
*/
}
if (lwp->lwp_oweupc)
/*
* Turn off the AST flag before checking all the conditions that
* may have caused an AST. This flag is on whenever a signal or
* unusual condition should be handled after the next trap or
* syscall.
*/
/*
* If a single-step trap occurred on a syscall (see above)
* recognize it now. Do this before checking for signals
* because deferred_singlestep_trap() may generate a SIGTRAP to
* the LWP or may otherwise mark the LWP to call issig(FORREAL).
*/
ct->t_sig_check = 0;
mutex_enter(&p->p_lock);
}
mutex_exit(&p->p_lock);
/*
* for kaio requests that are on the per-process poll queue,
* aiop->aio_pollq, they're AIO_POLL bit is set, the kernel
* should copyout their result_t to user memory. by copying
* out the result_t, the user can poll on memory waiting
* for the kaio request to complete.
*/
if (p->p_aio)
aio_cleanup(0);
/*
* If this LWP was asked to hold, call holdlwp(), which will
* stop. holdlwps() sets this up and calls pokelwps() which
* sets the AST flag.
*
* Also check TP_EXITLWP, since this is used by fresh new LWPs
* through lwp_rtt(). That flag is set if the lwp_create(2)
* syscall failed after creating the LWP.
*/
if (ISHOLD(p))
holdlwp();
/*
* All code that sets signals and makes ISSIG evaluate true must
* set t_astflag afterwards.
*/
psig();
}
realsigprof(0, 0, 0);
}
/*
* because that could race with the call gate used by
* system calls via "lcall". If that happened, an
* invalid EFLAGS would result. prstep()/prnostep()
* therefore schedule an AST for the purpose.
*/
}
}
}
out: /* We can't get here from a system trap */
if (ISHOLD(p))
holdlwp();
/*
* Set state to LWP_USER here so preempt won't give us a kernel
* priority if it occurs after this point. Call CL_TRAPRET() to
* restore the user-level priority.
*
* It is important that no locks (other than spinlocks) be entered
* after this point before returning to user mode (unless lwp_state
* is set back to LWP_SYS).
*/
CL_TRAPRET(ct);
}
preempt();
prunstop();
/* Kernel probe */
return;
cleanup: /* system traps end up here */
}
/*
* Patch non-zero to disable preemption of threads in the kernel.
*/
int IGNORE_KERNEL_PREEMPTION = 0; /* XXX - delete this someday */
struct kpreempt_cnts { /* kernel preemption statistics */
int kpc_idle; /* executing idle thread */
int kpc_intr; /* executing interrupt thread */
int kpc_clock; /* executing clock thread */
int kpc_blocked; /* thread has blocked preemption (t_preempt) */
int kpc_notonproc; /* thread is surrendering processor */
int kpc_inswtch; /* thread has ratified scheduling decision */
int kpc_prilevel; /* processor interrupt level is too high */
int kpc_apreempt; /* asynchronous preemption */
int kpc_spreempt; /* synchronous preemption */
/*
* kernel preemption: forced rescheduling, preempt the running kernel thread.
* the argument is old PIL for an interrupt,
* or the distingished value KPREEMPT_SYNC.
*/
void
{
if (IGNORE_KERNEL_PREEMPTION) {
return;
}
/*
* Check that conditions are right for kernel preemption
*/
do {
/*
* either a privileged thread (idle, panic, interrupt)
* or will check when t_preempt is lowered
* We need to specifically handle the case where
* the thread is in the middle of swtch (resume has
* been called) and has its t_preempt set
* [idle thread and a thread which is in kpreempt
* already] and then a high priority thread is
* available in the local dispatch queue.
* In this case the resumed thread needs to take a
* trap so that it can call kpreempt. We achieve
* this by using siron().
* How do we detect this condition:
* idle thread is running and is in the midst of
* resume: curthread->t_pri == -1 && CPU->dispthread
* != CPU->thread
* Need to ensure that this happens only at high pil
* resume is called at high pil
* Only in resume_from_idle is the pil changed.
*/
siron();
} else {
siron();
}
return;
}
/* this thread will be calling swtch() shortly */
/* already in swtch(), force another */
siron();
}
return;
}
if (getpil() >= DISP_LEVEL) {
/*
* We can't preempt this thread if it is at
* a PIL >= DISP_LEVEL since it may be holding
* a spin lock (like sched_lock).
*/
siron(); /* check back later */
return;
}
if (!interrupts_enabled()) {
/*
* Can't preempt while running with ints disabled
*/
return;
}
if (asyncspl != KPREEMPT_SYNC)
else
preempt();
} while (CPU->cpu_kprunrun);
}
/*
* Print out debugging info.
*/
static void
{
int s;
s = spl7();
if (type < TRAP_TYPES)
else
switch (type) {
case T_SYSCALL:
printf("Syscall Trap:\n");
break;
case T_AST:
printf("AST\n");
break;
default:
break;
}
printf("Bad %s fault at addr=0x%lx\n",
} else if (addr) {
}
printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n",
#if defined(__lint)
/*
* this clause can be deleted when lint bug 4870403 is fixed
* (lint thinks that bit 32 is illegal in a %b format string)
*/
printf("cr0: %x cr4: %b\n",
#else
printf("cr0: %b cr4: %b\n",
#endif /* __lint */
#if !defined(__xpv)
#if defined(__amd64)
#endif
#endif
printf("\n");
splx(s);
}
static void
{
#if defined(__amd64)
const char fmt[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n";
const char fmt[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n";
printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n",
#endif /* __i386 */
}
/*
* Test to see if the instruction is iret on i386 or iretq on amd64.
*
* On the hypervisor we can only test for nopop_sys_rtt_syscall. If true
* then we are in the context of hypervisor's failsafe handler because it
* tried to iret and failed due to a bad selector. See xen_failsafe_callback.
*/
static int
{
#if defined(__xpv)
extern void nopop_sys_rtt_syscall(void);
#else
#if defined(__amd64)
#endif /* __i386 */
#endif /* __xpv */
}
#if defined(__i386)
/*
* Test to see if the instruction is part of __SEGREGS_POP
*
* Note carefully the appallingly awful dependency between
* the instruction sequence used in __SEGREGS_POP and these
* instructions encoded here.
*/
static int
{
return (1);
return (0);
}
#endif /* __i386 */
/*
* Test to see if the instruction is part of _sys_rtt.
*
* Again on the hypervisor if we try to IRET to user land with a bad code
* or stack selector we will get vectored through xen_failsafe_callback.
* In which case we assume we got here via _sys_rtt since we only allow
* IRET to user land to take place in _sys_rtt.
*/
static int
{
extern void _sys_rtt(), _sys_rtt_end();
return (0);
return (1);
}
/*
* Handle #gp faults in kernel mode.
*
* One legitimate way this can happen is if we attempt to update segment
* registers to naughty values on the way out of the kernel.
*
* This can happen in a couple of ways: someone - either accidentally or
* on purpose - creates (setcontext(2), lwp_create(2)) or modifies
* (signal(2)) a ucontext that contains silly segment register values.
* Or someone - either accidentally or on purpose - modifies the prgregset_t
* of a subject process via /proc to contain silly segment register values.
*
* (The unfortunate part is that we can end up discovering the bad segment
* register value in the middle of an 'iret' after we've popped most of the
* stack. So it becomes quite difficult to associate an accurate ucontext
* with the lwp, because the act of taking the #gp trap overwrites most of
* what we were going to send the lwp.)
*
* OTOH if it turns out that's -not- the problem, and we're -not- an lwp
* trying to return to user mode and we get a #gp fault, then we need
* to die() -- which will happen if we return non-zero from this routine.
*/
static int
{
int v;
/*
* if we're not an lwp, or in the case of running native the
* pc range is outside _sys_rtt, then we should immediately
* be die()ing horribly.
*/
return (1);
/*
* So at least we're in the right part of the kernel.
*
* Disassemble the instruction at the faulting pc.
* Once we know what it is, we carefully reconstruct the stack
* based on the order in which the stack is deconstructed in
* _sys_rtt. Ew.
*/
if (instr_is_iret(pc)) {
/*
* We took the #gp while trying to perform the IRET.
* This means that either %cs or %ss are bad.
* All we know for sure is that most of the general
* registers have been restored, including the
* segment registers, and all we have left on the
* topmost part of the lwp's stack are the
* registers that the iretq was unable to consume.
*
* All the rest of the state was crushed by the #gp
* which pushed -its- registers atop our old save area
* (because we had to decrement the stack pointer, sigh) so
* all that we can try and do is to reconstruct the
* crushed frame from the #gp trap frame itself.
*/
/*
* Validate simple math
*/
}
#if defined(__amd64)
/*
* This is the common case -- we're trying to load
* a bad segment register value in the only section
* of kernel code that ever loads segment registers.
*
* We don't need to do anything at this point because
* the pcb contains all the pending segment register
* state, and the regs are still intact because we
* didn't adjust the stack pointer yet. Given the fidelity
* of all this, we could conceivably send a signal
* to the lwp, rather than core-ing.
*/
}
#endif /* __i386 */
return (1);
/*
* If we get to here, we're reasonably confident that we've
* correctly decoded what happened on the way out of the kernel.
* Rewrite the lwp's registers so that we can create a core dump
* the (at least vaguely) represents the mcontext we were
* being asked to restore when things went so terribly wrong.
*/
/*
* Make sure that we have a meaningful %trapno and %err.
*/
mutex_enter(&p->p_lock);
mutex_exit(&p->p_lock);
/*
* Terminate all LWPs but don't discard them. If another lwp beat
* us to the punch by calling exit(), evaporate now.
*/
proc_is_exiting(p);
if (exitlwps(1) != 0) {
mutex_enter(&p->p_lock);
lwp_exit();
}
if (auditing) /* audit core dump */
if (auditing) /* audit core dump */
return (0);
}
/*
* dump_tss() - Display the TSS structure
*/
#if !defined(__xpv)
#if defined(__amd64)
static void
dump_tss(void)
{
}
static void
dump_tss(void)
{
}
#endif /* __amd64 */
#endif /* !__xpv */
#if defined(TRAPTRACE)
int ttrace_dump_nregs = 0; /* dump out this many records with regs too */
/*
* Dump out the last ttrace_nrec traptrace records on each CPU
*/
static void
dump_ttrace(void)
{
int i, j, k;
int n = NCPU;
#if defined(__amd64)
const char banner[] =
"\ncpu address timestamp "
"type vc handler pc\n";
const char fmt1[] = "%3d %016lx %12llx ";
const char banner[] =
"\ncpu address timestamp type vc handler pc\n";
const char fmt1[] = "%3d %08lx %12llx ";
#endif
const char fmt2[] = "%4s %3x ";
const char fmt3[] = "%8s ";
if (ttrace_nrec == 0)
return;
for (i = 0; i < n; i++) {
ttc = &trap_trace_ctl[i];
continue;
for (j = 0; j < ttrace_nrec; j++) {
int type;
current =
continue;
break;
switch (rec->ttr_marker) {
case TT_SYSCALL:
case TT_SYSENTER:
case TT_SYSC:
case TT_SYSC64:
#if defined(__amd64)
switch (rec->ttr_marker) {
case TT_SYSC64:
/*FALLTHROUGH*/
switch (rec->ttr_marker) {
case TT_SYSC64:
#endif
case TT_SYSC:
break;
case TT_SYSCALL:
break;
case TT_SYSENTER:
break;
default:
break;
}
&off);
else
} else {
}
break;
case TT_INTERRUPT:
if (get_intr_handler != NULL)
else
vec =
else
} else {
}
break;
case TT_TRAP:
case TT_EVENT:
if (type < TRAP_TYPES)
printf(" #%s ",
else
switch (type) {
case T_AST:
break;
default:
break;
}
break;
default:
break;
}
else
if (ttrace_dump_nregs-- > 0) {
int s;
"\t\tipl %x spl %x pri %x\n",
(void *)rec->ttr_curthread);
/*
* print out the pc stack that we recorded
* at trap time (if any)
*/
for (s = 0; s < rec->ttr_sdepth; s++) {
if (s >= TTR_STACK_DEPTH) {
printf("ttr_sdepth corrupt\n");
break;
}
printf("-> %s+0x%lx()\n",
else
}
printf("\n");
}
current -= sizeof (trap_trace_rec_t);
}
}
}
#endif /* TRAPTRACE */
void
{
#if defined(TRAPTRACE)
dump_ttrace();
#endif
#if !defined(__xpv)
dump_tss();
#endif
}
void
{
}