timestamp.c revision ae115bc77f6fcde83175c75b4206dc2e50747966
/*
* CDDL HEADER START
*
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* Common Development and Distribution License (the "License").
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*
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* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
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*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/x86_archext.h>
#include <sys/archsystm.h>
#include <sys/psm_defs.h>
#include <sys/lockstat.h>
#include <sys/smp_impldefs.h>
/*
* Using the Pentium's TSC register for gethrtime()
* ------------------------------------------------
*
* The Pentium family, like many chip architectures, has a high-resolution
* timestamp counter ("TSC") which increments once per CPU cycle. The contents
* of the timestamp counter are read with the RDTSC instruction.
*
* As with its UltraSPARC equivalent (the %tick register), TSC's cycle count
* must be translated into nanoseconds in order to implement gethrtime().
* We avoid inducing floating point operations in this conversion by
* implementing the same nsec_scale algorithm as that found in the sun4u
* platform code. The sun4u NATIVE_TIME_TO_NSEC_SCALE block comment contains
* a detailed description of the algorithm; the comment is not reproduced
* here. This implementation differs only in its value for NSEC_SHIFT:
* we implement an NSEC_SHIFT of 5 (instead of sun4u's 4) to allow for
* 60 MHz Pentiums.
*
* While TSC and %tick are both cycle counting registers, TSC's functionality
* falls short in several critical ways:
*
* (a) TSCs on different CPUs are not guaranteed to be in sync. While in
* practice they often _are_ in sync, this isn't guaranteed by the
* architecture.
*
* (b) The TSC cannot be reliably set to an arbitrary value. The architecture
* only supports writing the low 32-bits of TSC, making it impractical
* to rewrite.
*
* (c) The architecture doesn't have the capacity to interrupt based on
* arbitrary values of TSC; there is no TICK_CMPR equivalent.
*
* Together, (a) and (b) imply that software must track the skew between
* TSCs and account for it (it is assumed that while there may exist skew,
* there does not exist drift). To determine the skew between CPUs, we
* have newly onlined CPUs call tsc_sync_slave(), while the CPU performing
* the online operation calls tsc_sync_master(). Once both CPUs are ready,
* the master sets a shared flag, and each reads its TSC register. To reduce
* bias, we then wait until both CPUs are ready again, but this time the
* slave sets the shared flag, and each reads its TSC register again. The
* master compares the average of the two sample values, and, if observable
* skew is found, changes the gethrtimef function pointer to point to a
* gethrtime() implementation which will take the discovered skew into
* consideration.
*
* In the absence of time-of-day clock adjustments, gethrtime() must stay in
* sync with gettimeofday(). This is problematic; given (c), the software
* cannot drive its time-of-day source from TSC, and yet they must somehow be
* kept in sync. We implement this by having a routine, tsc_tick(), which
* is called once per second from the interrupt which drives time-of-day.
* tsc_tick() recalculates nsec_scale based on the number of the CPU cycles
* since boot versus the number of seconds since boot. This algorithm
* becomes more accurate over time and converges quickly; the error in
* nsec_scale is typically under 1 ppm less than 10 seconds after boot, and
* is less than 100 ppb 1 minute after boot.
*
* Note that the hrtime base for gethrtime, tsc_hrtime_base, is modified
* atomically with nsec_scale under CLOCK_LOCK. This assures that time
* monotonically increases.
*/
#define NSEC_SHIFT 5
static uint_t nsec_scale;
/*
* These two variables used to be grouped together inside of a structure that
* lived on a single cache line. A regression (bug ID 4623398) caused the
* compiler to emit code that "optimized" away the while-loops below. The
* result was that no synchronization between the onlining and onlined CPUs
* took place.
*/
static volatile int tsc_ready;
static volatile int tsc_sync_go;
/*
* Used as indices into the tsc_sync_snaps[] array.
*/
#define TSC_MASTER 0
#define TSC_SLAVE 1
/*
* Used in the tsc_master_sync()/tsc_slave_sync() rendezvous.
*/
#define TSC_SYNC_STOP 1
#define TSC_SYNC_GO 2
#define TSC_SYNC_AGAIN 3
/*
* XX64 Is the faster way to do this with a 64-bit ABI?
*/
}
}
int tsc_master_slave_sync_needed = 1;
static int tsc_max_delta;
static hrtime_t tsc_last_jumped = 0;
static hrtime_t tsc_hrtime_base = 0;
static int tsc_jumped = 0;
static hrtime_t shadow_tsc_hrtime_base;
static hrtime_t shadow_tsc_last;
static uint_t shadow_nsec_scale;
static uint32_t shadow_hres_lock;
/*
* Called by the master after the sync operation is complete. If the
* slave is discovered to lag, gethrtimef will be changed to point to
* tsc_gethrtime_delta().
*/
static void
{
int max = tsc_max_delta;
int update;
/*
* We divide by 2 since each of the data points is the sum of two TSC
* reads; this takes the average of the two.
*/
return;
}
}
}
/*
* Called by a CPU which has just performed an online operation on another
* CPU. It is expected that the newly onlined CPU will call tsc_sync_slave().
*/
void
{
return;
flags = clear_int_flag();
/*
* Wait for the slave CPU to arrive.
*/
while (tsc_ready != TSC_SYNC_GO)
continue;
/*
* Tell the slave CPU to begin reading its TSC; read our own.
*/
/*
* Tell the slave that we're ready, and wait for the slave to tell us
* to read our TSC again.
*/
while (tsc_sync_go != TSC_SYNC_AGAIN)
continue;
/*
* Wait for the slave to finish reading its TSC.
*/
while (tsc_ready != TSC_SYNC_STOP)
continue;
/*
* At this point, both CPUs have performed their tsc_read() calls.
* We'll digest it now before letting the slave CPU return.
*/
}
/*
* Called by a CPU which has just been onlined. It is expected that the CPU
* performing the online operation will call tsc_sync_master().
*/
void
tsc_sync_slave(void)
{
return;
flags = clear_int_flag();
/* to test tsc_gethrtime_delta, add wrmsr(REG_TSC, 0) here */
/*
* Tell the master CPU that we're ready, and wait for the master to
* tell us to begin reading our TSC.
*/
while (tsc_sync_go != TSC_SYNC_GO)
continue;
/*
* Wait for the master CPU to be ready to read its TSC again.
*/
while (tsc_ready != TSC_SYNC_AGAIN)
continue;
/*
* Tell the master CPU to read its TSC again; read ours again.
*/
/*
* Tell the master that we're done, and wait to be dismissed.
*/
while (tsc_sync_go != TSC_SYNC_STOP)
continue;
}
void
{
/*
* cpu_freq_hz is the measured cpu frequency in hertz
*/
/*
* We can't accommodate CPUs slower than 31.25 MHz.
*/
(uint_t)
flags = clear_int_flag();
(void) tsc_gethrtime();
}
/*
* Called once per second on a CPU from the cyclic subsystem's
* CY_HIGH_LEVEL interrupt. (No longer just cpu0-only)
*/
void
tsc_tick(void)
{
/*
* Before we set the new variables, we set the shadow values. This
* allows for lock free operation in dtrace_gethrtime().
*/
CLOCK_LOCK(&spl);
if (gethrtimef == tsc_gethrtime_delta)
/*
* The TSC has just jumped into the past. We assume that
* to use the _current_ value of TSC as the delta. This
* will keep tsc_hrtime_base correct. We're also going to
* assume that rate of tsc does not change after a suspend
* resume (i.e nsec_scale remains the same).
*/
tsc_jumped = 1;
} else {
/*
* Determine the number of TSC ticks since the last clock
* tick, and add that to the hrtime base.
*/
}
}
tsc_gethrtime(void)
{
do {
/*
* It would seem to be obvious that this is true
* (that is, the past is less than the present),
* cycles. If we manage to call gethrtime()
* after a resume, but before the first call to
* tsc_tick(), we will see the jump. In this case,
* we will simply use the value in TSC as the delta.
*/
/*
* There is a chance that tsc_tick() has just run on
* another CPU, and we have drifted just enough so that
* we appear behind tsc_last. In this case, force the
* delta to be zero.
*/
tsc = 0;
}
return (hrt);
}
/*
* This is similar to the above, but it cannot actually spin on hres_lock.
* As a result, it caches all of the variables it needs; if the variables
* don't change, it's done.
*/
dtrace_gethrtime(void)
{
do {
/*
* See the comments in tsc_gethrtime(), above.
*/
tsc = 0;
break;
/*
* If we're here, the clock lock is locked -- or it has been
* unlocked and locked since we looked. This may be due to
* tsc_tick() running on another CPU -- or it may be because
* some code path has ended up in dtrace_probe() with
* CLOCK_LOCK held. We'll try to determine that we're in
* the former case by taking another lap if the lock has
* changed since when we first looked at it.
*/
if (old_hres_lock != hres_lock)
continue;
/*
* So the lock was and is locked. We'll use the old data
* instead.
*/
/*
* See the comments in tsc_gethrtime(), above.
*/
tsc -= shadow_tsc_last;
tsc = 0;
return (hrt);
}
tsc_gethrtime_delta(void)
{
int flags;
do {
/*
* We need to disable interrupts here to assure that we
* don't migrate between the call to tsc_read() and
* adding the CPU's TSC tick delta. Note that disabling
* and reenabling preemption is forbidden here because
* we may be in the middle of a fast trap. In the amd64
* kernel we cannot tolerate preemption during a fast
* trap. See _update_sregs().
*/
flags = clear_int_flag();
/* See comments in tsc_gethrtime() above */
tsc = 0;
}
return (hrt);
}
extern uint64_t cpu_freq_hz;
extern int tsc_gethrtime_enable;
/*
* The following converts nanoseconds of highres-time to ticks
*/
static uint64_t
{
}
/*
* This is used to convert scaled high-res time from nanoseconds to
* unscaled hardware ticks. (Read from hardware timestamp counter)
*/
{
if (tsc_gethrtime_enable) {
while (diff > (nsec_per_tick)) {
}
return (unscale);
}
return (0);
}
tsc_gethrtimeunscaled(void)
{
do {
/* See tsc_tick(). */
return (tsc);
}
/* Convert a tsc timestamp to nanoseconds */
void
{
return;
}
{
int flags;
/*
* Similarly to tsc_gethrtime_delta, we need to disable preemption
* to prevent migration between the call to tsc_gethrtimeunscaled
* and adding the CPU's hrtime delta. Note that disabling and
* reenabling preemption is forbidden here because we may be in the
* middle of a fast trap. In the amd64 kernel we cannot tolerate
* preemption during a fast trap. See _update_sregs().
*/
flags = clear_int_flag();
return (hrt);
}