mlsetup.c revision 0b70c4673a08649be68425e869e9d6357ea777a4
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/sysmacros.h>
#include <sys/x86_archext.h>
#include <sys/privregs.h>
#include <sys/machsystm.h>
#include <sys/bootconf.h>
#include <sys/kdi_machimpl.h>
#include <sys/archsystm.h>
#include <sys/bootconf.h>
#include <sys/kobj_lex.h>
#include <sys/pci_cfgspace.h>
#ifdef __xpv
#include <sys/hypervisor.h>
#endif
/*
* some globals for patching the result of cpuid
* to solve problems w/ creative cpu vendors
*/
extern uint32_t cpuid_feature_ecx_include;
extern uint32_t cpuid_feature_ecx_exclude;
extern uint32_t cpuid_feature_edx_include;
extern uint32_t cpuid_feature_edx_exclude;
/*
* Dummy spl priority masks
*/
0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf
};
static uint32_t
bootprop_getval(char *name)
{
char prop[32];
return (0);
}
/*
* Setup routine called right before main(). Interposing this function
* before main() allows us to call it in a machine-independent fashion.
*/
void
{
extern struct classfuncs sys_classfuncs;
extern char t0stack[];
int boot_ncpus;
#if !defined(__xpv)
extern int xpv_is_hvm;
#endif
/*
* initialize cpu_self
*/
#if defined(__xpv)
/*
* Point at the hypervisor's virtual cpu structure
*/
#endif
/*
* Set up dummy cpu_pri_data values till psm spl code is
* installed. This allows splx() to work on amd64.
*/
/*
* check if we've got special bits to clear or set
* when checking cpu features
*/
bootprop_getval("cpuid_feature_ecx_include");
bootprop_getval("cpuid_feature_ecx_exclude");
bootprop_getval("cpuid_feature_edx_include");
bootprop_getval("cpuid_feature_edx_exclude");
/*
* The first lightweight pass (pass0) through the cpuid data
* was done in locore before mlsetup was called. Do the next
* pass in C code.
*
* The x86_feature bits are set here on the basis of the capabilities
* of the boot CPU. Note that if we choose to support CPUs that have
* different feature sets (at which point we would almost certainly
* want to set the feature bits to correspond to the feature
* minimum) this value may be altered.
*/
/*
* Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
*/
#if !defined(__xpv)
/*
* Patch the tsc_read routine with appropriate set of instructions,
* depending on the processor family and architecure, to read the
* time-stamp counter while ensuring no out-of-order execution.
* Patch it while the kernel text is still writable.
*
* Note: tsc_read is not patched for intel processors whose family
* is >6 and for amd whose family >f (in case they don't support rdtscp
* instruction, unlikely). By default tsc_read will use cpuid for
* serialization in such cases. The following code needs to be
* revisited if intel processors of family >= f retains the
* instruction serialization nature of mfence instruction.
* Note: tsc_read is not patched for x86 processors which do
* not support "mfence". By default tsc_read will use cpuid for
* serialization in such cases.
*
* The Xen hypervisor does not correctly report whether rdtscp is
* supported or not, so we must assume that it is not.
*/
#endif /* !__xpv */
/*
* Some i386 processors do not implement the rdtsc instruction,
* or at least they do not implement it correctly. Patch them to
* return 0.
*/
if ((x86_feature & X86_TSC) == 0)
#endif /* __i386 && !__xpv */
#if !defined(__xpv)
/* XXPV what, if anything, should be dorked with here under xen? */
/*
* While we're thinking about the TSC, let's set up %cr4 so that
* userland can issue rdtsc, and initialize the TSC_AUX value
* (the cpuid) for the rdtscp instruction on appropriately
* capable hardware.
*/
if (x86_feature & X86_TSC)
if (x86_feature & X86_TSCP)
(void) wrmsr(MSR_AMD_TSCAUX, 0);
if (x86_feature & X86_DE)
#endif /* __xpv */
/*
* initialize t0
*/
p0.p_stkpageszc = 0;
p0.p_brkpageszc = 0;
/*
* The kernel doesn't use LDTs unless a process explicitly requests one.
*/
/*
*/
/*
* Initialize lists of available and active CPUs.
*/
/*
* Now that we have taken over the GDT, IDT and have initialized
* active CPU list it's time to inform kmdb if present.
*/
kdi_idt_sync();
/*
* If requested (boot -d) drop into kmdb.
*
* This must be done after cpu_list_init() on the 64-bit kernel
* since taking a trap requires that we re-compute gsbase based
* on the cpu list.
*/
if (boothowto & RB_DEBUGENTER)
kmdb_enter();
/* lgrp_init() needs PCI config space access */
#if defined(__xpv)
if (DOMAIN_IS_INITDOMAIN(xen_info))
#else
#endif
/*
* Initialize the lgrp framework
*/
lgrp_init();
boot_ncpus = NCPU;
prom_printf("unix: kernel halted by -h flag\n");
}
#if !defined(__xpv)
/*
* Fill out cpu_ucode_info. Update microcode if necessary.
*/
#endif
if (workaround_errata(CPU) != 0)
panic("critical workaround(s) missing for boot cpu");
}
void
{
/*
* Construct the directory path from the filename.
*/
int len;
char *p;
const char isastr[] = "/amd64";
return;
p--; /* remove trailing '/' characters */
if (p == filename)
p++; /* so "/" -is- the modpath in this case */
/*
* Remove optional isa-dependent directory name - the module
* subsystem will put this back again (!)
*/
p -= isalen;
/*
* "/platform/mumblefrotz" + " " + MOD_DEFPATH
*/
}