microcode.c revision 843e19887f64dde75055cf8842fc4db2171eff45
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/asm_linkage.h>
#include <sys/bootconf.h>
#include <sys/controlregs.h>
#include <sys/kobj_impl.h>
#include <sys/machsystm.h>
#include <sys/machparam.h>
#include <sys/sysmacros.h>
#include <sys/x86_archext.h>
#ifdef __xpv
#include <sys/hypervisor.h>
#endif
/*
* Microcode specific information per core
*/
struct cpu_ucode_info {
};
/*
* Data structure used for xcall
*/
struct ucode_update_struct {
};
/*
* mcpu_ucode_info for the boot CPU. Statically allocated.
*/
static struct cpu_ucode_info cpu_ucode_info0;
static ucode_file_t ucodefile = { 0 };
static int ucode_capable(cpu_t *);
ucode_header_t *, ucode_ext_table_t *);
ucode_file_t *);
static void ucode_read_rev(struct cpu_ucode_info *);
static const char ucode_failure_fmt[] =
"cpu%d: failed to update microcode code from version 0x%x to 0x%x\n";
static const char ucode_success_fmt[] =
"?cpu%d: microcode code has been updated from version 0x%x to 0x%x\n";
/*
* Force flag. If set, the first microcode binary that matches
* signature and platform id will be used for microcode update,
* regardless of version. Should only be used for debugging.
*/
int ucode_force_update = 0;
/*
* Allocate space for mcpu_ucode_info in the machcpu structure
* for all non-boot CPUs.
*/
void
{
}
void
{
}
/*
* Called when we are done with microcode update on all processors to free up
* space allocated for the microcode file.
*/
void
{
}
/*
* Check whether or not a processor is capable of microcode operations
* Returns 1 if it is capable, 0 if not.
*/
/*ARGSUSED*/
static int
{
/* i86xpv guest domain can't update microcode */
#ifdef __xpv
if (!DOMAIN_IS_INITDOMAIN(xen_info)) {
return (0);
}
#endif
#ifndef __xpv
/*
* At this point we only support microcode update for Intel
* processors family 6 and above.
*
* We also assume that we don't support a mix of Intel and
* AMD processors in the same box.
*/
return (0);
else
return (1);
#else
/*
* XXPV - remove when microcode loading works in dom0. Don't support
* microcode loading in dom0 right now.
*/
return (0);
#endif
}
/*
* Called when it is no longer necessary to keep the microcode around,
* or when the cached microcode doesn't match the CPU being processed.
*/
static void
{
int total_size, body_size;
return;
/*
* Space for the boot CPU is allocated with BOP_ALLOC()
* and does not require a free.
*/
if (id != 0)
}
if (ucodefp->uf_ext_table) {
/*
* Space for the boot CPU is allocated with BOP_ALLOC()
* and does not require a free.
*/
if (id != 0)
}
}
/*
* Populate the ucode file structure from microcode file corresponding to
* this CPU, if exists.
*
* Return EM_OK on success, corresponding error code on failure.
*/
static ucode_errno_t
{
char name[MAXPATHLEN];
int count;
int header_size = UCODE_HEADER_SIZE;
/*
* If the microcode matches the CPU we are processing, use it.
*/
return (EM_OK);
}
/*
* Look for microcode file with the right name.
*/
uinfop->cui_platid);
return (EM_OPENFILE);
}
/*
* We found a microcode file for the CPU we are processing,
* reset the microcode data structure and read in the new
* file.
*/
switch (count) {
case UCODE_HEADER_SIZE: {
/*
* Make sure that the header contains valid fields.
*/
KM_NOSLEEP)) == NULL) {
break;
}
} else {
/*
* BOP_ALLOC() failure results in panic so we
* don't have to check for NULL return.
*/
}
rc = EM_FILESIZE;
}
if (rc)
break;
rc = EM_CHECKSUM;
break;
}
/*
* Check to see if there is extended signature table.
*/
if (ext_size <= 0)
break;
KM_NOSLEEP)) == NULL) {
break;
}
} else {
/*
* BOP_ALLOC() failure results in panic so we
* don't have to check for NULL return.
*/
}
rc = EM_FILESIZE;
} else if (ucode_checksum(0, ext_size,
rc = EM_CHECKSUM;
} else {
int i;
i++) {
if (ucode_checksum(0, UCODE_EXT_SIG_SIZE,
uet_ext_sig[i])))) {
rc = EM_CHECKSUM;
break;
}
}
}
break;
}
default:
rc = EM_FILESIZE;
break;
}
kobj_close(fd);
return (rc);
return (rc);
}
/*
* Returns 1 if the microcode is for this processor; 0 otherwise.
*/
static ucode_errno_t
{
return (EM_HIGHERREV);
return (EM_OK);
}
int i;
return (EM_HIGHERREV);
return (EM_OK);
}
}
}
return (EM_NOMATCH);
}
/*ARGSUSED*/
static int
{
/*
* Check one more time to see if it is really necessary to update
* microcode just in case this is a hyperthreaded processor where
* the threads share the same microcode.
*/
if (!ucode_force_update) {
return (0);
}
return (0);
}
static void
{
}
static void
{
struct cpuid_regs crs;
/*
* The Intel 64 and IA-32 Architecture Software Developer's Manual
* recommends that MSR_INTC_UCODE_REV be loaded with 0 first, then
* execute cpuid to guarantee the correct reading of this register.
*/
wrmsr(MSR_INTC_UCODE_REV, 0);
(void) __cpuid_insn(&crs);
}
/*
* Entry point to microcode update from the ucode_drv driver.
*
* Returns EM_OK on success, corresponding error code on failure.
*/
{
int remaining;
int found = 0;
struct ucode_update_struct cached = { 0 };
if (!ucode_capable(CPU))
return (EM_NOTSUP);
struct ucode_update_struct uus = { 0 };
/*
* If there is no such CPU or it is not xcall ready, skip it.
*/
continue;
/*
* If the current CPU has the same signature and platform
* id as the previous one we processed, reuse the information.
*/
/*
* Intuitively we should check here to see whether the
* running microcode rev is >= the expected rev, and
* quit if it is. But we choose to proceed with the
* xcall regardless of the running version so that
* the other threads in an HT processor can update
* the cpu_ucode_info structure in machcpu.
*/
} else {
/*
* Go through the whole buffer in case there are
* multiple versions of matching microcode for this
* processor.
*/
ext_size = total_size -
(header_size + body_size);
if (ext_size > 0)
uetp = (ucode_ext_table_t *)
/*
* Since we are searching through a big file
* containing microcode for pretty much all the
* processors, we are bound to get EM_NOMATCH
* at one point. However, if we return
* EM_NOMATCH to users, it will really confuse
* them. Therefore, if we ever find a match of
* a lower rev, we will set return code to
* EM_HIGHERREV.
*/
if (tmprc == EM_HIGHERREV)
found = 1;
}
remaining -= total_size;
}
}
/* Nothing to do */
continue;
} else {
}
}
if (!found)
return (rc);
}
/*
* Initialize mcpu_ucode_info, and perform microcode update if necessary.
* This is the entry point from boot path where pointer to CPU structure
* is available.
*
* cpuid_info must be initialized before ucode_check can be called.
*/
void
{
struct cpu_ucode_info *uinfop;
if (!ucode_capable(cp))
return;
/*
* The MSR_INTC_PLATFORM_ID is supported in Celeron and Xeon
* (Family 6, model 5 and above) and all processors after.
*/
}
/*
* Check to see if we need ucode update
*/
}
/*
* If we fail to find a match for any reason, free the file structure
* just in case we have read in a partial file.
*
* Since the scratch memory for holding the microcode for the boot CPU
* came from BOP_ALLOC, we will reset the data structure as if we
* never did the allocation so we don't have to keep track of this
* special chunk of memory. We free the memory used for the rest
* of the CPUs in start_other_cpus().
*/
}
/*
* Returns microcode revision from the machcpu structure.
*/
{
int i;
if (!ucode_capable(CPU))
return (EM_NOTSUP);
for (i = 0; i < max_ncpus; i++) {
continue;
}
return (EM_OK);
}