fpu_subr.c revision ae115bc77f6fcde83175c75b4206dc2e50747966
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ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Use is subject to license terms.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj#pragma ident "%Z%%M% %I% %E% SMI"
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Floating point configuration.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * If fpu_exists is non-zero, fpu_probe will attempt to use any
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * hardware FPU (subject to other constraints, see below). If
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * fpu_exists is zero, fpu_probe will report that there is no
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * FPU even if there is one.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * The variable fpu_ignored is provided to allow other code to
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * determine whether emulation is being done because there is
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * no FPU or because of an override requested via /etc/system.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Used by ppcopy and ppzero to determine whether or not to use the
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * SSE-based pagecopy and pagezero routines
ae115bc77f6fcde83175c75b4206dc2e50747966mrj#if defined(__i386)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * The variable fpu_pentium_fdivbug is provided to allow other code to
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * determine whether the system contains a Pentium with the FDIV problem.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj#define ENABLE_SSE() setcr4(CR4_ENABLE_SSE_FLAGS(getcr4()))
ae115bc77f6fcde83175c75b4206dc2e50747966mrj#define DISABLE_SSE() setcr4(CR4_DISABLE_SSE_FLAGS(getcr4()))
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Try and figure out what kind of FP capabilities we have, and
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * set up the control registers accordingly.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj#if defined(__i386)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * The test does some real floating point operations.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Reset it back to previous state.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Check and see if the fpu is present by looking
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * at the "extension type" bit. (While this used to
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * indicate a 387DX coprocessor in days gone by,
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * it's forced on by modern implementations for
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * compatibility.)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj#if defined(__amd64)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * SSE and SSE2 are required for the 64-bit ABI.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * If they're not present, we can in principal run
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * 32-bit userland, though 64-bit processes will be hosed.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * (Perhaps we should complain more about this case!)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj if ((x86_feature & X86_SSE|X86_SSE2) == (X86_SSE|X86_SSE2)) {
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * SSE and SSE2 are both optional, and we patch kernel
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * code to exploit it when present.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * (Just in case the BIOS decided we wanted SSE
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * enabled when we didn't. See 4965674.)
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Extract the mxcsr mask from our first fxsave
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Override default mask initialized in fpu.c
ae115bc77f6fcde83175c75b4206dc2e50747966mrj /*CONSTANTCONDITION*/
ae115bc77f6fcde83175c75b4206dc2e50747966mrj } while (0);
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * No FPU hardware present