cpuid.c revision 7417cfdecea1902cef03c0d61a72df97d945925d
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
/*
* Copyright (c) 2009, Intel Corporation.
* All rights reserved.
*/
/*
* Portions Copyright 2009 Advanced Micro Devices, Inc.
*/
/*
* Various routines to handle identification
* and classification of x86 processors.
*/
#include <sys/archsystm.h>
#include <sys/x86_archext.h>
#include <sys/processor.h>
#include <sys/sysmacros.h>
#include <sys/controlregs.h>
#include <sys/auxv_386.h>
#include <sys/pci_cfgspace.h>
#ifdef __xpv
#include <sys/hypervisor.h>
#else
#endif
/*
* Pass 0 of cpuid feature analysis happens in locore. It contains special code
* to recognize Cyrix processors that are not cpuid-compliant, and to deal with
* them accordingly. For most modern processors, feature detection occurs here
* in pass 1.
*
* Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
* for the boot CPU and does the basic analysis that the early kernel needs.
* x86_featureset is set based on the return value of cpuid_pass1() of the boot
* CPU.
*
* Pass 1 includes:
*
* x86_vendor accordingly.
* o Processing the feature flags returned by the cpuid instruction while
* applying any workarounds or tricks for the specific processor.
* o Mapping the feature flags into Solaris feature bits (X86_*).
* o Processing extended feature flags if supported by the processor,
* again while applying specific processor knowledge.
* o Determining the CMT characteristics of the system.
*
* Pass 1 is done on non-boot CPUs during their initialization and the results
* are used only as a meager attempt at ensuring that all processors within the
* system support the same features.
*
* Pass 2 of cpuid feature analysis happens just at the beginning
* of startup(). It just copies in and corrects the remainder
* of the cpuid data we depend on: standard cpuid functions that we didn't
* need for pass1 feature analysis, and extended cpuid functions beyond the
* simple feature processing done in pass1.
*
* Pass 3 of cpuid analysis is invoked after basic kernel services; in
* particular kernel memory allocation has been made available. It creates a
* readable brand string based on the data collected in the first two passes.
*
* Pass 4 of cpuid analysis is invoked after post_startup() when all
* the support infrastructure for various hardware features has been
* initialized. It determines which processor features will be reported
* to userland via the aux vector.
*
* All passes are executed on all CPUs, but only the boot CPU determines what
* features the kernel will use.
*
* Much of the worst junk in this file is for the support of processors
* that didn't really implement the cpuid instruction properly.
*
* NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
* the pass numbers. Accordingly, changes to the pass code may require changes
* to the accessor code.
*/
uint_t x86_clflush_size = 0;
#define NUM_X86_FEATURES 33
void *x86_featureset;
char *x86_feature_names[NUM_X86_FEATURES] = {
"lgpg",
"tsc",
"msr",
"mtrr",
"pge",
"de",
"cmov",
"mmx",
"mca",
"pae",
"cv8",
"pat",
"sep",
"sse",
"sse2",
"htt",
"asysc",
"nx",
"sse3",
"cx16",
"cmp",
"tscp",
"mwait",
"sse4a",
"cpuid",
"ssse3",
"sse4_1",
"sse4_2",
"1gpg",
"clfsh",
"64",
"aes",
"pclmulqdq" };
static void *
init_x86_featureset(void)
{
}
void
free_x86_featureset(void *featureset)
{
}
{
}
void
{
}
void
{
}
{
/*
* We assume that the unused bits of the bitmap are always zero.
*/
return (B_TRUE);
} else {
return (B_FALSE);
}
}
void
print_x86_featureset(void *featureset)
{
uint_t i;
for (i = 0; i < NUM_X86_FEATURES; i++) {
if (is_x86_feature(featureset, i)) {
x86_feature_names[i]);
}
}
}
/*
* This is set to platform type Solaris is running on.
*/
static int platform_type = -1;
#if !defined(__xpv)
/*
* Variable to patch if hypervisor platform detection needs to be
* disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
*/
int enable_platform_detection = 1;
#endif
/*
*
* size_actual and buf_actual are the real address and size allocated to get
* proper mwait_buf alignement. buf_actual and size_actual should be passed
* to kmem_free(). Currently kmem_alloc() and mwait happen to both use
* processor cache-line alignment, but this is not guarantied in the furture.
*/
struct mwait_info {
void *buf_actual; /* memory actually allocated */
};
/*
* These constants determine how many of the elements of the
* cpuid we cache in the cpuid_info data structure; the
* remaining elements are accessible via the cpuid instruction.
*/
/*
* Some terminology needs to be explained:
* - Socket: Something that can be plugged into a motherboard.
* - Package: Same as socket
* - Chip: Same as socket. Note that AMD's documentation uses term "chip"
* differently: there, chip is the same as processor node (below)
* - Processor node: Some AMD processors have more than one
* "subprocessor" embedded in a package. These subprocessors (nodes)
* are fully-functional processors themselves with cores, caches,
* memory controllers, PCI configuration spaces. They are connected
* inside the package with Hypertransport links. On single-node
*/
struct cpuid_info {
/*
* standard function information
*/
int cpi_clogid; /* fn 1: %ebx: thread # */
/*
* extended function information
*/
int cpi_pkgcoreid; /* core number within single package */
/* Intel: fn 4: %eax[31-26] */
/*
* supported feature information
*/
#define STD_EDX_FEATURES 0
#define AMD_EDX_FEATURES 1
#define TM_EDX_FEATURES 2
#define STD_ECX_FEATURES 3
#define AMD_ECX_FEATURES 4
/*
* Synthesized information, where known.
*/
const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
/* Intel: 1 */
};
static struct cpuid_info cpuid_info0;
/*
* These bit fields are defined by the Intel Application Note AP-485
* "Intel Processor Identification and the CPUID Instruction"
*/
#define CPI_XMAXEAX_MAX 0x80000100
/*
* Function 4 (Deterministic Cache Parameters) macros
* Defined by Intel Application Note AP-485
*/
/*
* A couple of shorthand macros to identify "later" P6-family chips
* like the Pentium M and Core. First, the "older" P6-based stuff
* (loosely defined as "pre-Pentium-4"):
* P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
*/
#define IS_LEGACY_P6(cpi) ( \
)
/* A "new F6" is everything with family 6 that's not the above */
/*
*
* See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
* Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
* 2006.
* Documentation Updates" #33633, Rev 2.05, December 2006.
*/
/*
* Number of sub-cstates for a given c-state.
*/
/*
* Functions we consune from cpuid_subr.c; don't publish these in a header
* file to try and keep people using the expected cpuid_* interfaces.
*/
extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
/*
* Apply up various platform-dependent restrictions where the
* underlying platform restrictions mean the CPU can be marked
* as less capable than its cpuid instruction would imply.
*/
#if defined(__xpv)
static void
{
switch (eax) {
case 1: {
0 : CPUID_INTC_EDX_MCA;
~(mcamask |
break;
}
case 0x80000001:
break;
default:
break;
}
switch (vendor) {
case X86_VENDOR_Intel:
switch (eax) {
case 4:
/*
* Zero out the (ncores-per-chip - 1) field
*/
break;
default:
break;
}
break;
case X86_VENDOR_AMD:
switch (eax) {
case 0x80000001:
break;
case 0x80000008:
/*
* Zero out the (ncores-per-chip - 1) field
*/
break;
default:
break;
}
break;
default:
break;
}
}
#else
#endif
/*
* Some undocumented ways of patching the results of the cpuid
* instruction to permit running Solaris 10 on future cpus that
* we don't currently support. Could be set to non-zero values
* via settings in eeprom.
*/
/*
* Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
*/
void
{
/*
* By convention, cpu0 is the boot cpu, which is set up
* before memory allocation is available. All other cpus get
* their cpuid_info struct allocated here.
*/
}
void
{
int i;
/*
* Free up any function 4 related dynamic storage
*/
if (cpi->cpi_std_4_size > 0)
}
#if !defined(__xpv)
static void
{
struct cpuid_regs cp;
char *xen_str;
return;
/*
* In a fully virtualized domain, Xen's pseudo-cpuid function
* returns a string representing the Xen signature in %ebx, %ecx,
* and %edx. %eax contains the maximum supported cpuid function.
* We need at least a (base + 2) leaf value to do what we want
* to do. Try different base values, since the hypervisor might
* use a different one depending on whether hyper-v emulation
* is switched on by default or not.
*/
(void) __cpuid_insn(&cp);
xen_signature[3] = 0;
xen_str = (char *)xen_signature;
return;
}
}
if (vmware_platform()) /* running under vmware hypervisor? */
}
int
get_hwenv(void)
{
if (platform_type == -1)
return (platform_type);
}
int
is_controldom(void)
{
return (0);
}
#else
int
get_hwenv(void)
{
return (HW_XEN_PV);
}
int
is_controldom(void)
{
return (DOMAIN_IS_INITDOMAIN(xen_info));
}
#endif /* __xpv */
static void
{
uint_t i;
uint_t chipid_shift = 0;
uint_t coreid_shift = 0;
chipid_shift++;
/*
* Multi-core (and possibly multi-threaded)
* processors.
*/
/*
* 8bit APIC IDs on dual core Pentiums
* look like this:
*
* +-----------------------+------+------+
* | Physical Package ID | MC | HT |
* +-----------------------+------+------+
* <------- chipid -------->
* <------- coreid --------------->
* <--- clogid -->
* <------>
* pkgcoreid
*
* Where the number of bits necessary to
* represent MC and HT fields together equals
* to the minimum number of bits necessary to
* store the value of cpi->cpi_ncpu_per_chip.
* Of those bits, the MC part uses the number
* of bits necessary to store the value of
* cpi->cpi_ncore_per_chip.
*/
coreid_shift++;
/*
* Single-core multi-threaded processors.
*/
cpi->cpi_pkgcoreid = 0;
}
}
static void
{
int i, first_half, coreidsz;
/*
* AMD CMP chips currently have a single thread per core.
*
* Since no two cpus share a core we must assign a distinct coreid
* per cpu, and we do this by using the cpu_id. This scheme does not,
* however, guarantee that sibling cores of a chip will have sequential
* coreids starting at a multiple of the number of cores per chip -
* that is usually the case, but if the ACPI MADT table is presented
* in a different order then we need to perform a few more gymnastics
* for the pkgcoreid.
*
* All processors in the system have the same number of enabled
* cores. Cores within a processor are always numbered sequentially
* from 0 regardless of how many or which are disabled, and there
* is no way for operating system to discover the real core id when some
* are disabled.
*/
/*
* In AMD parlance chip is really a node while Solaris
*/
if (coreidsz == 0) {
/* Use legacy method */
coreidsz++;
if (coreidsz == 0)
coreidsz = 1;
}
} else {
/* Assume single-core part */
coreidsz = 1;
}
/* Get nodeID */
/*
* See if we are a multi-node processor.
* All processors in the system have the same number of nodes
*/
/* Single-node */
coreidsz);
} else {
/*
* Multi-node revision D (2 nodes per package
* are supported)
*/
/* We are BSP */
} else {
/* We are AP */
/* NodeId[2:1] bits to use for reading F3xe8 */
/*
* Check IntNodeNum bit (31:30, but bit 31 is
* always 0 on dual-node processors)
*/
else
}
}
} else {
cpi->cpi_procnodeid = 0;
}
}
void *
{
void *featureset;
struct cpuid_info *cpi;
struct cpuid_regs *cp;
int xcpuid;
#if !defined(__xpv)
extern int idle_cpu_prefer_mwait;
#endif
#if !defined(__xpv)
#endif
/*
* Space statically allocated for BSP, ensure pointer is set
*/
} else {
}
{
}
/*
* Limit the range in case of weird hardware
*/
goto pass1_done;
(void) __cpuid_insn(cp);
/*
* Extract identifying constants for easy access.
*/
/*
* Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
* Intel, and presumably everyone else, uses model == 0xf, as
* one would expect (max value means possible overflow). Sigh.
*/
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
if (IS_EXTENDED_MODEL_INTEL(cpi))
break;
case X86_VENDOR_AMD:
break;
default:
break;
}
/*
* *default* assumptions:
* - believe %edx feature word
* - ignore %ecx feature word
* - 32-bit virtual and physical addressing
*/
mask_edx = 0xffffffff;
mask_ecx = 0;
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
else if (IS_LEGACY_P6(cpi)) {
/*
* Clear the SEP bit when it was set erroneously
*/
/*
* We don't currently depend on any of the %ecx
* features until Prescott, so we'll only check
* this from P4 onwards. We might want to revisit
* that idea later.
*/
mask_ecx = 0xffffffff;
mask_ecx = 0xffffffff;
/*
* to obtain the monitor linesize.
*/
break;
case X86_VENDOR_IntelClone:
default:
break;
case X86_VENDOR_AMD:
#if defined(OPTERON_ERRATUM_108)
} else
#endif
/*
* AMD K5 and K6
*
* These CPUs have an incomplete implementation
*/
/*
* Model 0 uses the wrong (APIC) bit
* to indicate PGE. Fix it here.
*/
}
}
/*
* Early models had problems w/ MMX; disable.
*/
}
/*
* For newer families, SSE3 and CX16, at least, are valid;
* enable all
*/
mask_ecx = 0xffffffff;
/*
* to obtain the monitor linesize.
*/
#if !defined(__xpv)
/*
* processors. AMD does not intend MWAIT to be used in the cpu
* idle loop on current and future processors. 10h and future
* AMD processors use more power in MWAIT than HLT.
* Pre-family-10h Opterons do not have the MWAIT instruction.
*/
#endif
break;
case X86_VENDOR_TM:
/*
* workaround the NT workaround in CMS 4.1
*/
break;
case X86_VENDOR_Centaur:
/*
* workaround the NT workarounds again
*/
break;
case X86_VENDOR_Cyrix:
/*
* We rely heavily on the probing in locore
* to actually figure out what parts, if any,
* of the Cyrix cpuid instruction to believe.
*/
switch (x86_type) {
case X86_TYPE_CYRIX_486:
mask_edx = 0;
break;
case X86_TYPE_CYRIX_6x86:
mask_edx = 0;
break;
case X86_TYPE_CYRIX_6x86L:
mask_edx =
break;
case X86_TYPE_CYRIX_6x86MX:
mask_edx =
break;
case X86_TYPE_CYRIX_GXm:
mask_edx =
break;
case X86_TYPE_CYRIX_MediaGX:
break;
case X86_TYPE_CYRIX_MII:
case X86_TYPE_VIA_CYRIX_III:
mask_edx =
break;
default:
break;
}
break;
}
#if defined(__xpv)
/*
*/
#endif /* __xpv */
/*
* Now we've figured out the masks that determine
* which bits we choose to believe, apply the masks
* to the feature words, then map the kernel's view
* of these feature words into its feature word.
*/
/*
* apply any platform restrictions (we don't call this
* immediately after __cpuid_insn here, because we need the
* workarounds applied above first)
*/
/*
* fold in overrides from the "eeprom" mechanism
*/
}
}
}
}
}
}
}
}
}
}
}
}
}
/*
* are prerequisites before we'll even
* try and do SSE things.
*/
}
}
}
}
}
}
}
}
}
}
}
#if !defined(__xpv)
/*
* We require the CLFLUSH instruction for erratum workaround
*/
} else {
extern int idle_cpu_assert_cflush_monitor;
/*
* All processors we are aware of which have
*/
}
}
}
#endif /* __xpv */
/*
* Only need it first time, rest of the cpus would follow suite.
* we only capture this for the bootcpu.
*/
}
/*
* Hyperthreading configuration is slightly tricky on Intel
* and pure clones, and even trickier on AMD.
*
* (AMD chose to set the HTT bit on their CMP processors,
* even though they're not actually hyperthreaded. Thus it
* takes a bit more work to figure out what's really going
* on ... see the handling of the CMP_LGCY bit below)
*/
} else {
}
/*
* Work on the "extended" feature information, doing
* some basic initialization for cpuid_pass2()
*/
xcpuid = 0;
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
xcpuid++;
break;
case X86_VENDOR_AMD:
xcpuid++;
break;
case X86_VENDOR_Cyrix:
/*
* Only these Cyrix CPUs are -known- to support
* extended cpuid operations.
*/
if (x86_type == X86_TYPE_VIA_CYRIX_III ||
xcpuid++;
break;
case X86_VENDOR_Centaur:
case X86_VENDOR_TM:
default:
xcpuid++;
break;
}
if (xcpuid) {
}
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
break;
(void) __cpuid_insn(cp);
/*
* K6 model 6 uses bit 10 to indicate SYSC
* Later models use bit 11. Fix it here.
*/
}
}
/*
* Compute the additions to the kernel's feature word.
*/
}
/*
* Regardless whether or not we boot 64-bit,
* we should have a way to identify whether
* the CPU is capable of running 64-bit.
*/
}
#if defined(__amd64)
/* 1 GB large page - enable only for 64 bit kernel */
}
#endif
}
/*
* If both the HTT and CMP_LGCY bits are set,
* then we're not actually HyperThreaded. Read
* "AMD CPUID Specification" for more details.
*/
}
#if defined(__amd64)
/*
* instead. In the amd64 kernel, things are -way-
* better.
*/
}
/*
* While we're thinking about system calls, note
* that AMD processors don't support sysenter
* in long mode at all, so don't try to program them.
*/
if (x86_vendor == X86_VENDOR_AMD) {
}
#endif
}
break;
default:
break;
}
/*
* Get CPUID data about processor cores and hyperthreads.
*/
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
(void) __cpuid_insn(cp);
}
/*FALLTHROUGH*/
case X86_VENDOR_AMD:
break;
(void) __cpuid_insn(cp);
/*
* Virtual and physical address limits from
* cpuid override previously guessed values.
*/
break;
default:
break;
}
/*
* Derive the number of cores per chip
*/
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
break;
} else {
}
break;
case X86_VENDOR_AMD:
break;
} else {
/*
* On family 0xf cpuid fn 2 ECX[7:0] "NC" is
* 1 less than the number of physical cores on
* the chip. In family 0x10 this value can
* be affected by "downcoring" - it reflects
* 1 less than the number of cores actually
* enabled on this node.
*/
}
break;
default:
break;
}
/*
* Get CPUID data about TSC Invariance in Deep C-State.
*/
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
(void) __cpuid_insn(cp);
}
break;
default:
break;
}
} else {
}
/*
* If more than one core, then this processor is CMP.
*/
}
/*
* If the number of cores is the same as the number
* of CPUs, then we cannot have HyperThreading.
*/
}
/*
* Single-core single-threaded processors.
*/
cpi->cpi_clogid = 0;
cpi->cpi_pkgcoreid = 0;
else
else {
/*
* All other processors are currently
* assumed to have single cores.
*/
cpi->cpi_pkgcoreid = 0;
}
}
/*
* Synthesize chip "revision" and socket type
*/
return (featureset);
}
/*
* Make copies of the cpuid table entries we depend on, in
* part for ease of parsing now, in part so that we have only
* one place to correct any of it, in part for ease of
* later export to userland, and in part so we can look at
* this stuff in a crash dump.
*/
/*ARGSUSED*/
void
{
int i;
struct cpuid_regs *cp;
goto pass2_done;
nmax = NMAX_CPI_STD;
/*
* (We already handled n == 0 and n == 1 in pass 1)
*/
/*
* CPUID function 4 expects %ecx to be initialized
* with an index which indicates which cache to return
* information about. The OS is expected to call function 4
* with %ecx set to 0, 1, 2, ... until it returns with
* EAX[4:0] set to 0, which indicates there are no more
* caches.
*
* Here, populate cpi_std[4] with the information returned by
* function 4 when %ecx == 0, and do the rest in cpuid_pass3()
* when dynamic memory allocation becomes available.
*
* Note: we need to explicitly initialize %ecx here, since
* function 4 may have been previously invoked.
*/
if (n == 4)
(void) __cpuid_insn(cp);
switch (n) {
case 2:
/*
* "the lower 8 bits of the %eax register
* contain a value that identifies the number
* of times the cpuid [instruction] has to be
* executed to obtain a complete image of the
* processor's caching systems."
*
* How *do* they make this stuff up?
*/
if (cpi->cpi_ncache == 0)
break;
/*
* Well, for now, rather than attempt to implement
* this slightly dubious algorithm, we just look
* at the first 15 ..
*/
for (i = 1; i < 4; i++)
if (p[i] != 0)
*dp++ = p[i];
}
for (i = 0; i < 4; i++)
if (p[i] != 0)
*dp++ = p[i];
}
for (i = 0; i < 4; i++)
if (p[i] != 0)
*dp++ = p[i];
}
for (i = 0; i < 4; i++)
if (p[i] != 0)
*dp++ = p[i];
}
break;
case 3: /* Processor serial number, if PSN supported */
break;
case 4: /* Deterministic cache parameters */
break;
{
/*
* check cpi_mwait.support which was set in cpuid_pass1
*/
break;
/*
* Protect ourself from insane mwait line size.
* Workaround for incomplete hardware emulator(s).
*/
if (mwait_size < sizeof (uint32_t) ||
!ISP2(mwait_size)) {
#if DEBUG
#endif
break;
}
if (MWAIT_EXTENSION(cpi)) {
if (MWAIT_INT_ENABLE(cpi))
}
break;
}
default:
break;
}
}
struct cpuid_regs regs;
(void) __cpuid_insn(cp);
/*
* Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
* indicates that the extended topology enumeration leaf is
* available.
*/
uint_t coreid_shift = 0;
uint_t chipid_shift = 0;
uint_t i;
for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
(void) __cpuid_insn(cp);
if (level == 1) {
} else if (level == 2) {
}
}
}
/* Make cp NULL so that we don't stumble on others */
}
goto pass2_done;
/*
* Copy the extended properties, fixing them as we go.
* (We already handled n == 0 and n == 1 in pass 1)
*/
(void) __cpuid_insn(cp);
switch (n) {
case 2:
case 3:
case 4:
/*
* Extract the brand string
*/
break;
case 5:
switch (cpi->cpi_vendor) {
case X86_VENDOR_AMD:
/*
* The Athlon and Duron were the first
* parts to report the sizes of the
* TLB for large pages. Before then,
* we don't trust the data.
*/
break;
default:
break;
}
break;
case 6:
switch (cpi->cpi_vendor) {
case X86_VENDOR_AMD:
/*
* The Athlon and Duron were the first
* AMD parts with L2 TLB's.
* Before then, don't trust the data.
*/
/*
* AMD Duron rev A0 reports L2
* cache size incorrectly as 1K
* when it is really 64K
*/
}
break;
case X86_VENDOR_Cyrix: /* VIA C3 */
/*
* VIA C3 processors are a bit messed
* up w.r.t. encoding cache sizes in %ecx
*/
break;
/*
* model 7 and 8 were incorrectly encoded
*
* xxx is model 8 really broken?
*/
/*
* model 9 stepping 1 has wrong associativity
*/
break;
case X86_VENDOR_Intel:
/*
* Extended L2 Cache features function.
* First appeared on Prescott.
*/
default:
break;
}
break;
default:
break;
}
}
}
static const char *
{
int i;
return ("i486");
switch (cpi->cpi_family) {
case 5:
return ("Intel Pentium(r)");
case 6:
const struct cpuid_regs *cp;
case 0:
case 1:
case 2:
return ("Intel Pentium(r) Pro");
case 3:
case 4:
return ("Intel Pentium(r) II");
case 6:
return ("Intel Celeron(r)");
case 5:
case 7:
for (i = 1; i < 4; i++) {
if (tmp == 0x40)
celeron++;
xeon++;
}
for (i = 0; i < 2; i++) {
if (tmp == 0x40)
celeron++;
xeon++;
}
for (i = 0; i < 4; i++) {
if (tmp == 0x40)
celeron++;
xeon++;
}
for (i = 0; i < 4; i++) {
if (tmp == 0x40)
celeron++;
xeon++;
}
if (celeron)
return ("Intel Celeron(r)");
if (xeon)
"Intel Pentium(r) II Xeon(tm)" :
"Intel Pentium(r) III Xeon(tm)");
"Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
"Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
default:
break;
}
default:
break;
}
/* BrandID is present if the field is nonzero */
if (cpi->cpi_brandid != 0) {
static const struct {
const char *bt_str;
} brand_tbl[] = {
{ 0x1, "Intel(r) Celeron(r)" },
{ 0x2, "Intel(r) Pentium(r) III" },
{ 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
{ 0x4, "Intel(r) Pentium(r) III" },
{ 0x6, "Mobile Intel(r) Pentium(r) III" },
{ 0x7, "Mobile Intel(r) Celeron(r)" },
{ 0x8, "Intel(r) Pentium(r) 4" },
{ 0x9, "Intel(r) Pentium(r) 4" },
{ 0xa, "Intel(r) Celeron(r)" },
{ 0xb, "Intel(r) Xeon(tm)" },
{ 0xc, "Intel(r) Xeon(tm) MP" },
{ 0xe, "Mobile Intel(r) Pentium(r) 4" },
{ 0xf, "Mobile Intel(r) Celeron(r)" },
{ 0x11, "Mobile Genuine Intel(r)" },
{ 0x12, "Intel(r) Celeron(r) M" },
{ 0x13, "Mobile Intel(r) Celeron(r)" },
{ 0x14, "Intel(r) Celeron(r)" },
{ 0x15, "Mobile Genuine Intel(r)" },
{ 0x16, "Intel(r) Pentium(r) M" },
{ 0x17, "Mobile Intel(r) Celeron(r)" }
};
for (i = 0; i < btblmax; i++)
break;
if (i < btblmax) {
return ("Intel(r) Celeron(r)");
return ("Intel(r) Xeon(tm) MP");
return ("Intel(r) Xeon(tm)");
}
}
return (NULL);
}
static const char *
{
return ("i486 compatible");
switch (cpi->cpi_family) {
case 5:
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
return ("AMD-K5(r)");
case 6:
case 7:
return ("AMD-K6(r)");
case 8:
return ("AMD-K6(r)-2");
case 9:
return ("AMD-K6(r)-III");
default:
return ("AMD (family 5)");
}
case 6:
case 1:
return ("AMD-K7(tm)");
case 0:
case 2:
case 4:
return ("AMD Athlon(tm)");
case 3:
case 7:
return ("AMD Duron(tm)");
case 6:
case 8:
case 10:
/*
* Use the L2 cache size to distinguish
*/
"AMD Athlon(tm)" : "AMD Duron(tm)");
default:
return ("AMD (family 6)");
}
default:
break;
}
cpi->cpi_brandid != 0) {
case 3:
return ("AMD Opteron(tm) UP 1xx");
case 4:
return ("AMD Opteron(tm) DP 2xx");
case 5:
return ("AMD Opteron(tm) MP 8xx");
default:
return ("AMD Opteron(tm)");
}
}
return (NULL);
}
static const char *
{
return ("i486 compatible");
switch (type) {
case X86_TYPE_CYRIX_6x86:
return ("Cyrix 6x86");
case X86_TYPE_CYRIX_6x86L:
return ("Cyrix 6x86L");
case X86_TYPE_CYRIX_6x86MX:
return ("Cyrix 6x86MX");
case X86_TYPE_CYRIX_GXm:
return ("Cyrix GXm");
case X86_TYPE_CYRIX_MediaGX:
return ("Cyrix MediaGX");
case X86_TYPE_CYRIX_MII:
return ("Cyrix M2");
case X86_TYPE_VIA_CYRIX_III:
return ("VIA Cyrix M3");
default:
/*
* Have another wild guess ..
*/
return ("Cyrix 5x86");
case 2:
return ("Cyrix 6x86"); /* Cyrix M1 */
case 4:
return ("Cyrix MediaGX");
default:
break;
}
case 0:
return ("Cyrix 6x86MX"); /* Cyrix M2? */
case 5:
case 6:
case 7:
case 8:
case 9:
return ("VIA C3");
default:
break;
}
}
break;
}
return (NULL);
}
/*
* This only gets called in the case that the CPU extended
* feature brand string (0x80000002, 0x80000003, 0x80000004)
* aren't available, or contain null bytes for some reason.
*/
static void
{
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
break;
case X86_VENDOR_AMD:
break;
case X86_VENDOR_Cyrix:
break;
case X86_VENDOR_NexGen:
brand = "NexGen Nx586";
break;
case X86_VENDOR_Centaur:
case 4:
brand = "Centaur C6";
break;
case 8:
brand = "Centaur C2";
break;
case 9:
brand = "Centaur C3";
break;
default:
break;
}
break;
case X86_VENDOR_Rise:
brand = "Rise mP6";
break;
case X86_VENDOR_SiS:
brand = "SiS 55x";
break;
case X86_VENDOR_TM:
brand = "Transmeta Crusoe TM3x00 or TM5x00";
break;
case X86_VENDOR_NSC:
case X86_VENDOR_UMC:
default:
break;
}
if (brand) {
return;
}
/*
* If all else fails ...
*/
}
/*
* This routine is called just after kernel memory allocation
* becomes available on cpu0, and as part of mp_startup() on
* the other cpus.
*
* Fixup the brand string, and collect any information from cpuid
* that requires dynamicically allocated storage to represent.
*/
/*ARGSUSED*/
void
{
struct cpuid_regs regs;
struct cpuid_regs *cp;
/*
* Function 4: Deterministic cache parameters
*
* Take this opportunity to detect the number of threads
* sharing the last level cache, and construct a corresponding
* cache id. The respective cpuid_info members are initialized
* to the default case of "no last level cache sharing".
*/
/*
* Find the # of elements (size) returned by fn 4, and along
* the way detect last level cache sharing details.
*/
for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
(void) __cpuid_insn(cp);
if (CPI_CACHE_TYPE(cp) == 0)
break;
}
}
/*
* Allocate the cpi_std_4 array. The first element
* references the regs for fn 4, %ecx == 0, which
* cpuid_pass2() stashed in cpi->cpi_std[4].
*/
if (size > 0) {
/*
* Allocate storage to hold the additional regs
* for function 4, %ecx == 1 .. cpi_std_4_size.
*
* The regs for fn 4, %ecx == 0 has already
* been allocated as indicated above.
*/
for (i = 1; i < size; i++) {
(void) __cpuid_insn(cp);
}
}
/*
* Determine the number of bits needed to represent
* the number of CPUs sharing the last level cache.
*
* Shift off that number of bits from the APIC id to
* derive the cache id.
*/
shft = 0;
shft++;
}
/*
* Now fixup the brand string
*/
} else {
/*
* If we successfully extracted a brand string from the cpuid
* instruction, clean it up by removing leading spaces and
* similar junk.
*/
if (cpi->cpi_brandstr[0]) {
/*
* strip leading spaces
*/
while (*src == ' ')
src++;
/*
* Remove any 'Genuine' or "Authentic" prefixes
*/
src += 8;
src += 10;
/*
* Now do an in-place copy.
* Map (R) to (r) and (TM) to (tm).
* The era of teletypes is long gone, and there's
* -really- no need to shout.
*/
while (*src != '\0') {
if (src[0] == '(') {
src += 3;
dst += 3;
continue;
}
src += 4;
dst += 4;
continue;
}
}
}
*dst = '\0';
/*
* Finally, remove any trailing spaces
*/
if (*dst == ' ')
*dst = '\0';
else
break;
} else
}
}
/*
* This routine is called out of bind_hwcap() much later in the life
* of the kernel (post_startup()). The job of this routine is to resolve
* the hardware feature support and kernel support for those features into
* what we're actually going to tell applications via the aux vector.
*/
{
struct cpuid_info *cpi;
uint_t hwcap_flags = 0;
/*
* [these require explicit kernel support]
*/
*edx &= ~CPUID_INTC_EDX_SEP;
*edx &= ~CPUID_INTC_EDX_SSE2;
*edx &= ~CPUID_INTC_EDX_HTT;
*ecx &= ~CPUID_INTC_ECX_SSE3;
*ecx &= ~CPUID_INTC_ECX_SSSE3;
*ecx &= ~CPUID_INTC_ECX_SSE4_1;
*ecx &= ~CPUID_INTC_ECX_SSE4_2;
*ecx &= ~CPUID_INTC_ECX_AES;
*ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
}
/*
* [no explicit support required beyond x87 fp context]
*/
if (!fpu_exists)
/*
* Now map the supported feature vector to things that we
* think userland will care about.
*/
if (*edx & CPUID_INTC_EDX_SEP)
if (*edx & CPUID_INTC_EDX_SSE)
if (*edx & CPUID_INTC_EDX_SSE2)
if (*ecx & CPUID_INTC_ECX_SSE3)
if (*ecx & CPUID_INTC_ECX_SSSE3)
if (*ecx & CPUID_INTC_ECX_SSE4_1)
if (*ecx & CPUID_INTC_ECX_SSE4_2)
if (*ecx & CPUID_INTC_ECX_MOVBE)
if (*ecx & CPUID_INTC_ECX_AES)
if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
}
if (*ecx & CPUID_INTC_ECX_POPCNT)
if (*edx & CPUID_INTC_EDX_FPU)
if (*edx & CPUID_INTC_EDX_MMX)
if (*edx & CPUID_INTC_EDX_TSC)
if (*edx & CPUID_INTC_EDX_CX8)
if (*edx & CPUID_INTC_EDX_CMOV)
if (*ecx & CPUID_INTC_ECX_CX16)
}
goto pass4_done;
switch (cpi->cpi_vendor) {
struct cpuid_regs cp;
case X86_VENDOR_Intel:
/*
* Seems like Intel duplicated what we necessary
* here to make the initial crop of 64-bit OS's work.
* Hopefully, those are the only "extended" bits
* they'll add.
*/
/*FALLTHROUGH*/
case X86_VENDOR_AMD:
/*
* [these features require explicit kernel support]
*/
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
*edx &= ~CPUID_AMD_EDX_TSCP;
break;
case X86_VENDOR_AMD:
*edx &= ~CPUID_AMD_EDX_TSCP;
*ecx &= ~CPUID_AMD_ECX_SSE4A;
break;
default:
break;
}
/*
* [no explicit support required beyond
* x87 fp context and exception handlers]
*/
if (!fpu_exists)
*edx &= ~(CPUID_AMD_EDX_MMXamd |
*edx &= ~CPUID_AMD_EDX_NX;
#if !defined(__amd64)
*edx &= ~CPUID_AMD_EDX_LM;
#endif
/*
* Now map the supported feature vector to
* things that we think userland will care about.
*/
#if defined(__amd64)
if (*edx & CPUID_AMD_EDX_SYSC)
#endif
if (*edx & CPUID_AMD_EDX_MMXamd)
if (*edx & CPUID_AMD_EDX_3DNow)
if (*edx & CPUID_AMD_EDX_3DNowx)
switch (cpi->cpi_vendor) {
case X86_VENDOR_AMD:
if (*edx & CPUID_AMD_EDX_TSCP)
if (*ecx & CPUID_AMD_ECX_AHF64)
if (*ecx & CPUID_AMD_ECX_SSE4A)
if (*ecx & CPUID_AMD_ECX_LZCNT)
break;
case X86_VENDOR_Intel:
if (*edx & CPUID_AMD_EDX_TSCP)
/*
* Aarrgh.
* Intel uses a different bit in the same word.
*/
if (*ecx & CPUID_INTC_ECX_AHF64)
break;
default:
break;
}
break;
case X86_VENDOR_TM:
(void) __cpuid_insn(&cp);
break;
default:
break;
}
return (hwcap_flags);
}
/*
* Simulate the cpuid instruction using the data we previously
* captured about this CPU. We try our best to return the truth
* about the hardware, independently of kernel support.
*/
{
struct cpuid_info *cpi;
struct cpuid_regs *xcp;
/*
* CPUID data is cached in two separate places: cpi_std for standard
* CPUID functions, and cpi_extd for extended CPUID functions.
*/
else
/*
* The caller is asking for data from an input parameter which
* the kernel has not cached. In this case we go fetch from
* the hardware and return the data directly to the user.
*/
return (__cpuid_insn(cp));
}
int
{
}
int
{
}
int
{
}
/*
* AMD and Intel both implement the 64-bit variant of the syscall
* instruction (syscallq), so if there's -any- support for syscall,
* cpuid currently says "yes, we support this".
*
* However, Intel decided to -not- implement the 32-bit variant of the
* syscall instruction, so we provide a predicate to allow our caller
* to test that subtlety here.
*
* XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
* even in the case where the hardware would in fact support it.
*/
/*ARGSUSED*/
int
{
#if !defined(__xpv)
/*CSTYLED*/
{
return (1);
}
#endif
return (0);
}
int
{
static const char fmt[] =
"x86 (%s %X family %d model %d step %d clock %d MHz)";
static const char fmt_ht[] =
"x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
if (cpuid_is_cmt(cpu))
}
const char *
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
const char *
{
}
{
}
const char *
{
struct cpuid_info *cpi;
/* Assume that socket types are the same across the system */
return (socketstr);
}
int
{
if (cpuid_is_cmt(cpu))
}
{
}
int
{
}
int
{
}
int
{
}
{
}
{
}
/*ARGSUSED*/
int
{
#if defined(__amd64)
return (1);
#else
struct cpuid_info *cpi;
return (1);
return (0);
#endif
}
{
return (UINT32_MAX);
} else {
}
}
void
{
struct cpuid_info *cpi;
if (pabits)
if (vabits)
}
/*
* Returns the number of data TLB entries for a corresponding
* pagesize. If it can't be computed, or isn't known, the
* routine returns zero. If you ask about an architecturally
* impossible pagesize, the routine will panic (so that the
* hat implementor knows that things are inconsistent.)
*/
{
struct cpuid_info *cpi;
/*
* Check the L2 TLB info
*/
switch (pagesize) {
case 4 * 1024:
/*
* All zero in the top 16 bits of the register
* indicates a unified TLB. Size is in low 16 bits.
*/
else
break;
case 2 * 1024 * 1024:
else
break;
default:
panic("unknown L2 pagesize");
/*NOTREACHED*/
}
}
if (dtlb_nent != 0)
return (dtlb_nent);
/*
* No L2 TLB support for this size, try L1.
*/
switch (pagesize) {
case 4 * 1024:
break;
case 2 * 1024 * 1024:
break;
default:
panic("unknown L1 d-TLB pagesize");
/*NOTREACHED*/
}
}
return (dtlb_nent);
}
/*
* Return 0 if the erratum is not present or not applicable, positive
* if it is, and negative if the status of the erratum is unknown.
*
* See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
* Processors" #25759, Rev 3.57, August 2005
*/
int
{
/*
* Bail out if this CPU isn't an AMD CPU, or if it's
* a legacy (32-bit) AMD CPU.
*/
return (0);
switch (erratum) {
case 1:
case 51: /* what does the asterisk mean? */
case 52:
return (B(eax));
case 57:
case 58:
return (B(eax));
case 60:
case 61:
case 62:
case 63:
case 64:
case 65:
case 66:
case 68:
case 69:
case 70:
case 71:
return (B(eax));
case 72:
case 74:
return (B(eax));
case 75:
case 76:
return (B(eax));
case 77:
case 78:
case 79:
case 80:
case 81:
case 82:
return (B(eax));
case 83:
case 85:
case 86:
case 88:
#if !defined(__amd64)
return (0);
#else
#endif
case 89:
case 90:
case 91:
case 92:
case 93:
case 94:
case 95:
#if !defined(__amd64)
return (0);
#else
#endif
case 96:
case 97:
case 98:
case 99:
case 100:
case 101:
case 103:
case 104:
case 105:
case 106:
case 107:
case 108:
case 109:
case 110:
case 111:
case 112:
case 113:
return (eax == 0x20fc0);
case 114:
case 115:
case 116:
case 117:
case 118:
case 121:
case 122:
case 123:
case 131:
case 6336786:
/*
* Test for AdvPowerMgmtInfo.TscPStateInvariant
* if this is a K8 family or newer processor
*/
struct cpuid_regs regs;
(void) __cpuid_insn(®s);
}
return (0);
case 6323525:
case 6671130:
/*
* check for processors (pre-Shanghai) that do not provide
* optimal management of 1gb ptes in its tlb.
*/
case 298:
default:
return (-1);
}
}
/*
* Determine if specified erratum is present via OSVW (OS Visible Workaround).
* Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
*/
int
{
struct cpuid_info *cpi;
static int osvwfeature = -1;
/* confirm OSVW supported */
if (osvwfeature == -1) {
} else {
/* assert that osvw feature setting is consistent on all cpus */
}
if (!osvwfeature)
return (-1);
switch (erratum) {
case 298: /* osvwid is 0 */
osvwid = 0;
/* osvwid 0 is unknown */
return (-1);
}
/*
* Check the OSVW STATUS MSR to determine the state
* of the erratum where:
* 0 - fixed by HW
* 1 - BIOS has applied the workaround when BIOS
* workaround is available. (Or for other errata,
* OS workaround is required.)
* For a value of 1, caller will confirm that the
* erratum 298 workaround has indeed been applied by BIOS.
*
* A 1 may be set in cpus that have a HW fix
* in a mixed cpu system. Regarding erratum 298:
* In a multiprocessor platform, the workaround above
* should be applied to all processors regardless of
* silicon revision when an affected processor is
* present.
*/
return (rdmsr(MSR_AMD_OSVW_STATUS +
(osvwid / OSVW_ID_CNT_PER_MSR)) &
default:
return (-1);
}
}
static const char assoc_str[] = "associativity";
static const char line_str[] = "line-size";
static const char size_str[] = "size";
static void
{
char buf[128];
/*
* ndi_prop_update_int() is used because it is desirable for
* DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
*/
}
/*
*
* Standard cpuid level 2 gives a randomly ordered
* selection of tags that index into a table that describes
* cache and tlb properties.
*/
static const char l1_icache_str[] = "l1-icache";
static const char l1_dcache_str[] = "l1-dcache";
static const char l2_cache_str[] = "l2-cache";
static const char l3_cache_str[] = "l3-cache";
static const char itlb4k_str[] = "itlb-4K";
static const char dtlb4k_str[] = "dtlb-4K";
static const char itlb2M_str[] = "itlb-2M";
static const char itlb4M_str[] = "itlb-4M";
static const char dtlb4M_str[] = "dtlb-4M";
static const char dtlb24_str[] = "dtlb0-2M-4M";
static const char itlb424_str[] = "itlb-4K-2M-4M";
static const char itlb24_str[] = "itlb-2M-4M";
static const char dtlb44_str[] = "dtlb-4K-4M";
static const char sl1_dcache_str[] = "sectored-l1-dcache";
static const char sl2_cache_str[] = "sectored-l2-cache";
static const char itrace_str[] = "itrace-cache";
static const char sl3_cache_str[] = "sectored-l3-cache";
static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
static const struct cachetab {
const char *ct_label;
} intel_ctab[] = {
/*
* maintain descending order!
*
* Codes ignored - Reason
* ----------------------
*/
{ 0 }
};
static const struct cachetab cyrix_ctab[] = {
{ 0x70, 4, 0, 32, "tlb-4K" },
{ 0x80, 4, 16, 16*1024, "l1-cache" },
{ 0 }
};
/*
* Search a cache table for a matching entry
*/
static const struct cachetab *
{
if (code != 0) {
break;
return (ct);
}
return (NULL);
}
/*
* Populate cachetab entry with L2 or L3 cache-information using
* cpuid function 4. This function is called from intel_walk_cacheinfo()
* when descriptor 0x49 is encountered. It returns 0 if no such cache
* information is found.
*/
static int
{
int ret = 0;
for (i = 0; i < cpi->cpi_std_4_size; i++) {
ct->ct_line_size =
ct->ct_line_size *
if (level == 2) {
} else if (level == 3) {
}
ret = 1;
}
}
return (ret);
}
/*
* Walk the cacheinfo descriptor, applying 'func' to every valid element
* The walk is terminated if the walker returns non-zero.
*/
static void
{
int i;
return;
/*
* For overloaded descriptor 0x49 we use cpuid function 4
* if supported by the current processor, to create
* cache information.
* For overloaded descriptor 0xb1 we use X86_PAE flag
* to disambiguate the cache information.
*/
} else if (*dp == 0xb1) {
des_b1_ct.ct_line_size = 0;
} else {
}
} else {
continue;
}
}
break;
}
}
}
/*
* (Like the Intel one, except for Cyrix CPUs)
*/
static void
{
int i;
return;
/*
* Search Cyrix-specific descriptor table first ..
*/
break;
continue;
}
/*
* .. else fall back to the Intel one
*/
break;
continue;
}
}
}
/*
* A cacheinfo walker that adds associativity, line-size, and size properties
* to the devinfo node it is passed as an argument.
*/
static int
{
if (ct->ct_line_size != 0)
ct->ct_line_size);
return (0);
}
static const char fully_assoc[] = "fully-associative?";
/*
*
* Extended functions 5 and 6 directly describe properties of
* tlbs and various cache levels.
*/
static void
{
switch (assoc) {
case 0: /* reserved; ignore */
break;
default:
break;
case 0xff:
break;
}
}
static void
{
if (size == 0)
return;
}
static void
{
return;
/*
* Most AMD parts have a sectored cache. Multiple cache lines are
* associated with each tag. A sector consists of all cache lines
* associated with a tag. For example, the AMD K6-III has a sector
* size of 2 cache lines per tag.
*/
if (lines_per_tag != 0)
}
static void
{
switch (assoc) {
case 0: /* off */
break;
case 1:
case 2:
case 4:
break;
case 6:
break;
case 8:
break;
case 0xf:
break;
default: /* reserved; ignore */
break;
}
}
static void
{
return;
}
static void
{
return;
if (lines_per_tag != 0)
}
static void
{
struct cpuid_regs *cp;
return;
/*
* 4M/2M L1 TLB configuration
*
* We report the size for 2M pages because AMD uses two
* TLB entries for one 4M page.
*/
/*
* 4K L1 TLB configuration
*/
switch (cpi->cpi_vendor) {
case X86_VENDOR_TM:
/*
* Crusoe processors have 256 TLB entries, but
* cpuid data format constrains them to only
* reporting 255 of them.
*/
nentries = 256;
/*
* Crusoe processors also have a unified TLB
*/
nentries);
break;
}
/*FALLTHROUGH*/
default:
break;
}
/*
* data L1 cache configuration
*/
/*
* code L1 cache configuration
*/
return;
/* Check for a unified L2 TLB for large pages */
else {
}
/* Check for a unified L2 TLB for 4K pages */
} else {
}
}
/*
* There are two basic ways that the x86 world describes it cache
* and tlb architecture - Intel's way and AMD's way.
*
* Return which flavor of cache architecture we should use
*/
static int
{
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
return (X86_VENDOR_Intel);
break;
case X86_VENDOR_AMD:
/*
* The K5 model 1 was the first part from AMD that reported
* cache sizes via extended cpuid functions.
*/
return (X86_VENDOR_AMD);
break;
case X86_VENDOR_TM:
return (X86_VENDOR_AMD);
/*FALLTHROUGH*/
default:
/*
* If they have extended CPU data for 0x80000005
* then we assume they have AMD-format cache
* information.
*
* If not, and the vendor happens to be Cyrix,
* then try our-Cyrix specific handler.
*
* If we're not Cyrix, then assume we're using Intel's
* table-driven format instead.
*/
return (X86_VENDOR_AMD);
return (X86_VENDOR_Cyrix);
return (X86_VENDOR_Intel);
break;
}
return (-1);
}
void
struct cpuid_info *cpi)
{
int create;
/* device_type */
"device_type", "cpu");
/* reg */
"reg", cpu_id);
/* cpu-mhz, and clock-frequency */
if (cpu_freq > 0) {
long long mul;
"cpu-mhz", cpu_freq);
"clock-frequency", (int)mul);
}
return;
}
/* vendor-id */
if (cpi->cpi_maxeax == 0) {
return;
}
/*
* family, model, and step
*/
/* type */
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
create = 1;
break;
default:
create = 0;
break;
}
if (create)
/* ext-family */
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
break;
default:
create = 0;
break;
}
if (create)
/* ext-model */
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
break;
case X86_VENDOR_AMD:
break;
default:
create = 0;
break;
}
if (create)
/* generation */
switch (cpi->cpi_vendor) {
case X86_VENDOR_AMD:
/*
* AMD K5 model 1 was the first part to support this
*/
break;
default:
create = 0;
break;
}
if (create)
/* brand-id */
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
/*
* brand id first appeared on Pentium III Xeon model 8,
* and Celeron model 8 processors and Opteron
*/
break;
case X86_VENDOR_AMD:
break;
default:
create = 0;
break;
}
}
/* chunks, and apic-id */
switch (cpi->cpi_vendor) {
/*
* first available on Pentium IV and Opteron (K8)
*/
case X86_VENDOR_Intel:
break;
case X86_VENDOR_AMD:
break;
default:
create = 0;
break;
}
if (create) {
if (cpi->cpi_chipid >= 0) {
}
}
/* cpuid-features */
/* cpuid-features-ecx */
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
break;
default:
create = 0;
break;
}
if (create)
/* ext-cpuid-features */
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
case X86_VENDOR_Cyrix:
case X86_VENDOR_TM:
case X86_VENDOR_Centaur:
break;
default:
create = 0;
break;
}
if (create) {
}
/*
* Brand String first appeared in Intel Pentium IV, AMD K5
* model 1, and Cyrix GXm. On earlier models we try and
* simulate something similar .. so this string should always
* same -something- about the processor, however lame.
*/
/*
* Finally, cache and tlb information
*/
switch (x86_which_cacheinfo(cpi)) {
case X86_VENDOR_Intel:
break;
case X86_VENDOR_Cyrix:
break;
case X86_VENDOR_AMD:
break;
default:
break;
}
}
struct l2info {
int *l2i_csz;
int *l2i_lsz;
int *l2i_assoc;
int l2i_ret;
};
/*
* A cacheinfo walker that fetches the size, line-size and associativity
* of the L2 cache
*/
static int
{
int *ip;
return (0); /* not an L2 -- keep walking */
return (1); /* was an L2 -- terminate walk */
}
/*
*
* Unlike the associativity for the L1 cache and tlb where the 8 bit
* value is the associativity, the associativity for the L2 cache and
* tlb is encoded in the following table. The 4 bit L2 value serves as
* an index into the amd_afd[] array to determine the associativity.
* -1 is undefined. 0 is fully associative.
*/
static int amd_afd[] =
{-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
static void
{
struct cpuid_regs *cp;
int i;
int *ip;
return;
}
}
int
{
switch (x86_which_cacheinfo(cpi)) {
case X86_VENDOR_Intel:
break;
case X86_VENDOR_Cyrix:
break;
case X86_VENDOR_AMD:
break;
default:
break;
}
}
#if !defined(__xpv)
uint32_t *
{
if (mwait_size == 0)
return (NULL);
/*
* kmem_alloc() returns cache line size aligned data for mwait_size
* allocations. mwait_size is currently cache line sized. Neither
* of these implementation details are guarantied to be true in the
* future.
*
* First try allocating mwait_size as kmem_alloc() currently returns
* correctly aligned memory. If kmem_alloc() does not return
* mwait_size aligned memory, then use mwait_size ROUNDUP.
*
* Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
* decide to free this memory.
*/
*ret = MWAIT_RUNNING;
return (ret);
} else {
*ret = MWAIT_RUNNING;
return (ret);
}
}
void
{
return;
}
}
}
void
patch_tsc_read(int flag)
{
switch (flag) {
case X86_NO_TSC:
break;
case X86_HAVE_TSCP:
break;
case X86_TSC_MFENCE:
(void *)&_tsc_mfence_start, cnt);
break;
case X86_TSC_LFENCE:
(void *)&_tsc_lfence_start, cnt);
break;
default:
break;
}
}
int
{
struct cpuid_info *cpi;
struct cpuid_regs regs;
return (0);
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
return (0);
/*
* TSC run at a constant rate in all ACPI C-states?
*/
(void) __cpuid_insn(®s);
default:
return (0);
}
}
#endif /* !__xpv */
void
post_startup_cpu_fixups(void)
{
#ifndef __xpv
/*
* Some AMD processors support C1E state. Entering this state will
* cause the local APIC timer to stop, which we can't deal with at
* this time.
*/
/* Disable C1E state if it is enabled by BIOS */
if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
reg &= ~(AMD_ACTONCMPHALT_MASK <<
}
}
no_trap();
}
#endif /* !__xpv */
}
/*
* Starting with the Westmere processor the local
* APIC timer will continue running in all C-states,
* including the deepest C-states.
*/
int
cpuid_arat_supported(void)
{
struct cpuid_info *cpi;
struct cpuid_regs regs;
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
/*
* Always-running Local APIC Timer is
* indicated by CPUID.6.EAX[2].
*/
} else {
return (0);
}
default:
return (0);
}
}
/*
* Check support for Intel ENERGY_PERF_BIAS feature
*/
int
{
struct cpuid_regs regs;
return (0);
}
/*
* Intel ENERGY_PERF_BIAS MSR is indicated by
* capability bit CPUID.6.ECX.3
*/
return (0);
}
/*
* Patch in versions of bcopy for high performance Intel Nhm processors
* and later...
*/
void
{
if ((vendor == X86_VENDOR_Intel) &&
to = &bcopy_ck_size;
for (i = 0; i < cnt; i++) {
}
}
}
#endif /* __amd64 && !__xpv */
/*
* This function finds the number of bits to represent the number of cores per
* chip and the number of strands per core for the Intel platforms.
* It re-uses the x2APIC cpuid code of the cpuid_pass2().
*/
void
{
struct cpuid_regs regs;
if (vendor != X86_VENDOR_Intel) {
return;
}
/* if the cpuid level is 0xB, extended topo is available. */
(void) __cpuid_insn(cp);
/*
* Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
* indicates that the extended topology enumeration leaf is
* available.
*/
uint_t coreid_shift = 0;
uint_t chipid_shift = 0;
uint_t i;
for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
(void) __cpuid_insn(cp);
if (level == 1) {
/*
* Thread level processor topology
* Number of bits shift right APIC ID
* to get the coreid.
*/
} else if (level == 2) {
/*
* Core level processor topology
* Number of bits shift right APIC ID
* to get the chipid.
*/
}
}
}
}
}
}