cpuid.c revision 2449e17f82f6097fd2c665b64723e31ceecbeca6
0ec5755428223b8105e488e8fddc19de4db26521raf * CDDL HEADER START
0ec5755428223b8105e488e8fddc19de4db26521raf * The contents of this file are subject to the terms of the
0ec5755428223b8105e488e8fddc19de4db26521raf * Common Development and Distribution License (the "License").
0ec5755428223b8105e488e8fddc19de4db26521raf * You may not use this file except in compliance with the License.
0ec5755428223b8105e488e8fddc19de4db26521raf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
0ec5755428223b8105e488e8fddc19de4db26521raf * See the License for the specific language governing permissions
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0ec5755428223b8105e488e8fddc19de4db26521raf * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
0ec5755428223b8105e488e8fddc19de4db26521raf * If applicable, add the following below this CDDL HEADER, with the
0ec5755428223b8105e488e8fddc19de4db26521raf * fields enclosed by brackets "[]" replaced with your own identifying
0ec5755428223b8105e488e8fddc19de4db26521raf * information: Portions Copyright [yyyy] [name of copyright owner]
0ec5755428223b8105e488e8fddc19de4db26521raf * CDDL HEADER END
0ec5755428223b8105e488e8fddc19de4db26521raf * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
ae115bc77f6fcde83175c75b4206dc2e50747966mrj * Use is subject to license terms.
0ec5755428223b8105e488e8fddc19de4db26521raf#pragma ident "%Z%%M% %I% %E% SMI"
0ec5755428223b8105e488e8fddc19de4db26521raf * Various routines to handle identification
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * and classification of x86 processors.
0ec5755428223b8105e488e8fddc19de4db26521raf * Pass 0 of cpuid feature analysis happens in locore. It contains special code
0ec5755428223b8105e488e8fddc19de4db26521raf * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
0ec5755428223b8105e488e8fddc19de4db26521raf * them accordingly. For most modern processors, feature detection occurs here
0ec5755428223b8105e488e8fddc19de4db26521raf * in pass 1.
0ec5755428223b8105e488e8fddc19de4db26521raf * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
0ec5755428223b8105e488e8fddc19de4db26521raf * for the boot CPU and does the basic analysis that the early kernel needs.
0ec5755428223b8105e488e8fddc19de4db26521raf * x86_feature is set based on the return value of cpuid_pass1() of the boot
0ec5755428223b8105e488e8fddc19de4db26521raf * Pass 1 includes:
0ec5755428223b8105e488e8fddc19de4db26521raf * o Determining vendor/model/family/stepping and setting x86_type and
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * x86_vendor accordingly.
0ec5755428223b8105e488e8fddc19de4db26521raf * o Processing the feature flags returned by the cpuid instruction while
0ec5755428223b8105e488e8fddc19de4db26521raf * applying any workarounds or tricks for the specific processor.
0ec5755428223b8105e488e8fddc19de4db26521raf * o Mapping the feature flags into Solaris feature bits (X86_*).
0ec5755428223b8105e488e8fddc19de4db26521raf * o Processing extended feature flags if supported by the processor,
0ec5755428223b8105e488e8fddc19de4db26521raf * again while applying specific processor knowledge.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * o Determining the CMT characteristics of the system.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Pass 1 is done on non-boot CPUs during their initialization and the results
0ec5755428223b8105e488e8fddc19de4db26521raf * are used only as a meager attempt at ensuring that all processors within the
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * system support the same features.
0ec5755428223b8105e488e8fddc19de4db26521raf * Pass 2 of cpuid feature analysis happens just at the beginning
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * of startup(). It just copies in and corrects the remainder
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * of the cpuid data we depend on: standard cpuid functions that we didn't
0ec5755428223b8105e488e8fddc19de4db26521raf * need for pass1 feature analysis, and extended cpuid functions beyond the
0ec5755428223b8105e488e8fddc19de4db26521raf * simple feature processing done in pass1.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Pass 3 of cpuid analysis is invoked after basic kernel services; in
0ec5755428223b8105e488e8fddc19de4db26521raf * particular kernel memory allocation has been made available. It creates a
0ec5755428223b8105e488e8fddc19de4db26521raf * readable brand string based on the data collected in the first two passes.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Pass 4 of cpuid analysis is invoked after post_startup() when all
0ec5755428223b8105e488e8fddc19de4db26521raf * the support infrastructure for various hardware features has been
0ec5755428223b8105e488e8fddc19de4db26521raf * initialized. It determines which processor features will be reported
0ec5755428223b8105e488e8fddc19de4db26521raf * to userland via the aux vector.
0ec5755428223b8105e488e8fddc19de4db26521raf * All passes are executed on all CPUs, but only the boot CPU determines what
0ec5755428223b8105e488e8fddc19de4db26521raf * features the kernel will use.
0ec5755428223b8105e488e8fddc19de4db26521raf * Much of the worst junk in this file is for the support of processors
0ec5755428223b8105e488e8fddc19de4db26521raf * that didn't really implement the cpuid instruction properly.
0ec5755428223b8105e488e8fddc19de4db26521raf * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
0ec5755428223b8105e488e8fddc19de4db26521raf * the pass numbers. Accordingly, changes to the pass code may require changes
0ec5755428223b8105e488e8fddc19de4db26521raf * to the accessor code.
0ec5755428223b8105e488e8fddc19de4db26521raf * This set of strings are for processors rumored to support the cpuid
0ec5755428223b8105e488e8fddc19de4db26521raf * instruction, and is used by locore.s to figure out how to set x86_vendor
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe size_t mon_min; /* min size to avoid missed wakeups */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe size_t mon_max; /* size to avoid false wakeups */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe uint32_t support; /* processor support of monitor/mwait */
0ec5755428223b8105e488e8fddc19de4db26521raf * These constants determine how many of the elements of the
0ec5755428223b8105e488e8fddc19de4db26521raf * cpuid we cache in the cpuid_info data structure; the
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * remaining elements are accessible via the cpuid instruction.
0ec5755428223b8105e488e8fddc19de4db26521raf#define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * standard function information
0ec5755428223b8105e488e8fddc19de4db26521raf chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
0ec5755428223b8105e488e8fddc19de4db26521raf * extended function information
0ec5755428223b8105e488e8fddc19de4db26521raf struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe /* Intel: fn 4: %eax[31-26] */
0ec5755428223b8105e488e8fddc19de4db26521raf * supported feature information
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Synthesized information, where known.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
0ec5755428223b8105e488e8fddc19de4db26521raf struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
0ec5755428223b8105e488e8fddc19de4db26521raf * These bit fields are defined by the Intel Application Note AP-485
0ec5755428223b8105e488e8fddc19de4db26521raf * "Intel Processor Identification and the CPUID Instruction"
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe#define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe#define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe#define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
0ec5755428223b8105e488e8fddc19de4db26521raf#define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
0ec5755428223b8105e488e8fddc19de4db26521raf#define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe#define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe#define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
0ec5755428223b8105e488e8fddc19de4db26521raf#define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
0ec5755428223b8105e488e8fddc19de4db26521raf#define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
0ec5755428223b8105e488e8fddc19de4db26521raf#define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
0ec5755428223b8105e488e8fddc19de4db26521raf#define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe#define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
41efec2219526a9b3ecce26f97aba761ef1e1d0draf#define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
0ec5755428223b8105e488e8fddc19de4db26521raf * A couple of shorthand macros to identify "later" P6-family chips
0ec5755428223b8105e488e8fddc19de4db26521raf * like the Pentium M and Core. First, the "older" P6-based stuff
0ec5755428223b8105e488e8fddc19de4db26521raf * (loosely defined as "pre-Pentium-4"):
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe/* A "new F6" is everything with family 6 that's not the above */
41efec2219526a9b3ecce26f97aba761ef1e1d0draf#define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
0ec5755428223b8105e488e8fddc19de4db26521raf * AMD family 0xf socket types.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * First index is 0 for revs B thru E, 1 for F and G.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Second index by (model & 0x3)
0ec5755428223b8105e488e8fddc19de4db26521raf * Table for mapping AMD Family 0xf model/stepping combination to
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * chip "revision" and socket type. Only rm_family 0xf is used at the
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * moment, but AMD family 0x10 will extend the exsiting revision names
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * so will likely also use this table.
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * The first member of this array that matches a given family, extended model
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * plus model range, and stepping range will be considered a match.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowestatic const struct amd_rev_mapent {
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 },
41efec2219526a9b3ecce26f97aba761ef1e1d0draf { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 },
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8
41efec2219526a9b3ecce26f97aba761ef1e1d0draf { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 },
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * Rev CG is the rest of extended model 0x0 - i.e., everything
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * but the rev B and C0 combinations covered above.
41efec2219526a9b3ecce26f97aba761ef1e1d0draf { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 },
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Rev D has extended model 0x1.
41efec2219526a9b3ecce26f97aba761ef1e1d0draf { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 },
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * Rev E has extended model 0x2.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Extended model 0x3 is unused but available to grow into.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 },
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Rev F has extended models 0x4 and 0x5.
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 },
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Rev G has extended model 0x6.
41efec2219526a9b3ecce26f97aba761ef1e1d0draf { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 },
41efec2219526a9b3ecce26f97aba761ef1e1d0draf * Info for monitor/mwait idle loop.
0ec5755428223b8105e488e8fddc19de4db26521raf * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
0ec5755428223b8105e488e8fddc19de4db26521raf * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
0ec5755428223b8105e488e8fddc19de4db26521raf * Documentation Updates" #33633, Rev 2.05, December 2006.
0ec5755428223b8105e488e8fddc19de4db26521raf#define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
6a3e8e8695d5c7d1d18c6800d676990d7f61a2a4Richard Lowe#define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
0ec5755428223b8105e488e8fddc19de4db26521raf#define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
0ec5755428223b8105e488e8fddc19de4db26521raf#define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
0ec5755428223b8105e488e8fddc19de4db26521raf#define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
0ec5755428223b8105e488e8fddc19de4db26521raf#define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
0ec5755428223b8105e488e8fddc19de4db26521raf#define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
0ec5755428223b8105e488e8fddc19de4db26521raf * Number of sub-cstates for a given c-state.
0ec5755428223b8105e488e8fddc19de4db26521rafstatic void
0ec5755428223b8105e488e8fddc19de4db26521raf * Currently only AMD family 0xf uses these fields.
i++, rmp++) {
case X86_VENDOR_AMD:
int xcpuid;
goto pass1_done;
case X86_VENDOR_AMD:
mask_ecx = 0;
case X86_VENDOR_Intel:
case X86_VENDOR_IntelClone:
case X86_VENDOR_AMD:
#if defined(OPTERON_ERRATUM_108)
case X86_VENDOR_TM:
case X86_VENDOR_Centaur:
case X86_VENDOR_Cyrix:
switch (x86_type) {
case X86_TYPE_CYRIX_486:
mask_edx = 0;
case X86_TYPE_CYRIX_6x86:
mask_edx = 0;
case X86_TYPE_CYRIX_6x86L:
mask_edx =
case X86_TYPE_CYRIX_6x86MX:
mask_edx =
case X86_TYPE_CYRIX_GXm:
mask_edx =
case X86_TYPE_CYRIX_MediaGX:
case X86_TYPE_CYRIX_MII:
case X86_TYPE_VIA_CYRIX_III:
mask_edx =
xcpuid = 0;
case X86_VENDOR_Intel:
xcpuid++;
case X86_VENDOR_AMD:
xcpuid++;
case X86_VENDOR_Cyrix:
xcpuid++;
case X86_VENDOR_Centaur:
case X86_VENDOR_TM:
xcpuid++;
if (xcpuid) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
#if defined(__amd64)
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
uint_t i;
chipid_shift++;
coreid_shift++;
return (feature);
goto pass2_done;
*dp++ = p[i];
*dp++ = p[i];
*dp++ = p[i];
*dp++ = p[i];
* check cpi_mwait.support which was set in cpuid_pass1
goto pass2_done;
case X86_VENDOR_AMD:
case X86_VENDOR_AMD:
* up w.r.t. encoding cache sizes in %ecx
case X86_VENDOR_Intel:
celeron++;
xeon++;
celeron++;
xeon++;
celeron++;
xeon++;
celeron++;
xeon++;
if (celeron)
if (xeon)
const char *bt_str;
} brand_tbl[] = {
for (i = 0; i < btblmax; i++)
if (i < btblmax) {
return (NULL);
return (NULL);
switch (type) {
case X86_TYPE_CYRIX_6x86:
case X86_TYPE_CYRIX_6x86L:
case X86_TYPE_CYRIX_6x86MX:
case X86_TYPE_CYRIX_GXm:
case X86_TYPE_CYRIX_MediaGX:
case X86_TYPE_CYRIX_MII:
case X86_TYPE_VIA_CYRIX_III:
return (NULL);
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
case X86_VENDOR_Cyrix:
case X86_VENDOR_NexGen:
case X86_VENDOR_Centaur:
case X86_VENDOR_Rise:
case X86_VENDOR_SiS:
case X86_VENDOR_TM:
case X86_VENDOR_NSC:
case X86_VENDOR_UMC:
if (brand) {
goto pass3_done;
src++;
if (!fpu_exists)
goto pass4_done;
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
if (!fpu_exists)
#if !defined(__amd64)
#if defined(__amd64)
case X86_VENDOR_AMD:
case X86_VENDOR_Intel:
case X86_VENDOR_TM:
return (hwcap_flags);
static const char fmt[] =
static const char fmt_ht[] =
if (pabits)
if (vabits)
switch (pagesize) {
if (dtlb_nent != 0)
return (dtlb_nent);
switch (pagesize) {
return (dtlb_nent);
switch (erratum) {
return (B(eax));
return (B(eax));
return (B(eax));
return (B(eax));
return (B(eax));
return (B(eax));
#if !defined(__amd64)
#if !defined(__amd64)
static const struct cachetab {
const char *ct_label;
} intel_ctab[] = {
static const struct cachetab *
if (code != 0) {
return (ct);
return (NULL);
switch (assoc) {
if (size == 0)
if (lines_per_tag != 0)
switch (assoc) {
if (lines_per_tag != 0)
case X86_VENDOR_TM:
nentries);
case X86_VENDOR_Intel:
return (X86_VENDOR_Intel);
case X86_VENDOR_AMD:
return (X86_VENDOR_AMD);
case X86_VENDOR_TM:
return (X86_VENDOR_AMD);
return (X86_VENDOR_AMD);
return (X86_VENDOR_Cyrix);
return (X86_VENDOR_Intel);
int create;
cpu_id);
if (cpu_freq > 0) {
long long mul;
case X86_VENDOR_Intel:
create = 0;
if (create)
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
create = 0;
if (create)
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
create = 0;
if (create)
case X86_VENDOR_AMD:
create = 0;
if (create)
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
create = 0;
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
create = 0;
if (create) {
case X86_VENDOR_Intel:
create = 0;
if (create)
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
case X86_VENDOR_Cyrix:
case X86_VENDOR_TM:
case X86_VENDOR_Centaur:
create = 0;
if (create) {
case X86_VENDOR_Intel:
case X86_VENDOR_Cyrix:
case X86_VENDOR_AMD:
struct l2info {
int *l2i_csz;
int *l2i_lsz;
int *l2i_assoc;
int l2i_ret;
int *ip;
int *ip;
case X86_VENDOR_Intel:
case X86_VENDOR_Cyrix:
case X86_VENDOR_AMD: