cpr_impl.c revision 3d995820f4ce8cd712d97f05aae6d30d9952d298
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * CDDL HEADER START
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * The contents of this file are subject to the terms of the
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Common Development and Distribution License (the "License").
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * You may not use this file except in compliance with the License.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * See the License for the specific language governing permissions
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * and limitations under the License.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * When distributing Covered Code, include this CDDL HEADER in each
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * If applicable, add the following below this CDDL HEADER, with the
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2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * information: Portions Copyright [yyyy] [name of copyright owner]
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * CDDL HEADER END
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Use is subject to license terms.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Platform specific implementation code
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Currently only suspend to RAM is supported (ACPI S3)
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfextern void *wc_long_mode_64(void);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf#endif /* __amd64 */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfextern void i_cpr_start_cpu(void);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfinit_real_mode_platter(int cpun, uint32_t offset, uint_t cr4, wc_desctbr_t gdt);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfstatic int i_cpr_platform_alloc(psm_state_request_t *req);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfstatic void i_cpr_platform_free(psm_state_request_t *req);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfstatic int i_cpr_restore_apic(psm_state_request_t *req);
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsendstatic void i_cpr_save_stack(kthread_t *t, wc_cpu_t *wc_cpu);
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsendvoid i_cpr_restore_stack(kthread_t *t, greg_t *save_stack);
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend#define CPR_GET_STACK_START(t) ((t)->t_stkbase)
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend#define CPR_GET_STACK_START(t) ((t)->t_stk)
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend#define CPR_GET_STACK_END(t) ((t)->t_stkbase)
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend#endif /* STACK_GROWTH_DOWN */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * restart paused slave cpus
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Stop all interrupt activities in the system
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Set machine up to take interrupts
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Save miscellaneous information which needs to be written to the
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * state file. This information is required to re-initialize
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * kernel/prom handshaking.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (0);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * cpu0 should contain bootcpu info
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Save context for the specified CPU
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("i_cpr_save_context() index = %ld\n", index))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * wc_save_context returns twice, once when susending and
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * once when resuming, wc_save_context() returns 0 when
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * suspending and non-zero upon resume
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend resuming = (wc_save_context(wc_cpu) == 0);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * do NOT call any functions after this point, because doing so
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * will modify the stack that we are running on
643e2e74e1c00e6b3d1896a6a67dbdb7308135c3bholler * Enable interrupts on this cpu.
643e2e74e1c00e6b3d1896a6a67dbdb7308135c3bholler * Do not bind interrupts to this CPU's local APIC until
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * the CPU is ready to receive interrupts.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Setting the bit in cpu_ready_set must be the last operation
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * in processor initialization; the boot CPU will continue to
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * boot once it sees this bit set for all active CPUs.
a563a037ee1e9e7c39304f3775eb7327ab86b914bholler ("i_cpr_save_context() resuming cpu %d in cpu_ready_set\n",
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * Disable interrupts on this CPU so that PSM knows not to bind
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * interrupts here on resume until the CPU has executed
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * cpu_enable_intr() (above) in the resume path.
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * We explicitly do not grab cpu_lock here because at this point
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * in the suspend process, the boot cpu owns cpu_lock and all
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * other cpus are also executing in the pause thread (only
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * modifying their respective CPU structure).
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg PMD(PMD_SX, ("i_cpr_save_context: wc_save_context returns %d\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf if (!(warm_reset_vector = (ushort_t *)psm_map_phys(WARM_RESET_VECTOR,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * setup secondary cpu bios boot up vector
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf ((struct rm_platter *)rm_platter_va)->rm_code - rm_platter_va
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * this is a cut down version of start_other_cpus()
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * just do the initialization to wake the other cpus
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf extern int get_tsc_ready();
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf rm_platter_t *real_mode_platter = (rm_platter_t *)rm_platter_va;
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg * If startup wasn't able to find a page under 1M, we cannot
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg cmn_err(CE_WARN, "Cannot suspend the system because no "
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg "memory below 1M could be found for processor startup");
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Copy the real mode code at "real_mode_start" to the
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * page at rm_platter_va.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("i_cpr_pre_resume_cpus() returning #2\n"))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * We lock our affinity to the master CPU to ensure that all slave CPUs
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * do their TSC syncs with the same CPU.
a563a037ee1e9e7c39304f3775eb7327ab86b914bholler * Mark the boot cpu as being ready and in the procset, since we are
a563a037ee1e9e7c39304f3775eb7327ab86b914bholler * running on that cpu.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf code_length = (uint32_t)wc_long_mode_64 - (uint32_t)wc_rm_start;
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf init_real_mode_platter(who, code_length, cpup->wc_cr4, gdt);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf if ((err = mach_cpuid_start(who, rm_platter_va)) != 0) {
a563a037ee1e9e7c39304f3775eb7327ab86b914bholler PMD(PMD_SX, ("%s() #1 waiting for %d in procset\n", str, who))
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan PMD(PMD_SX, ("%s() tsc_ready = %d\n", str, get_tsc_ready()))
a563a037ee1e9e7c39304f3775eb7327ab86b914bholler PMD(PMD_SX, ("%s() waiting for %d in cpu_ready_set\n", str,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Wait for cpu to declare that it is ready, we want the
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * cpus to start serially instead of in parallel, so that
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * they do not contend with each other in wc_rm_start()
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * do not need to re-initialize dtrace using dtrace_cpu_init
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf psm_unmap_phys((caddr_t)warm_reset_vector, sizeof (ushort_t *));
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * We need to setup a 1:1 (virtual to physical) mapping for the
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * page containing the wakeup code.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfstatic struct as *save_as; /* when switching to kas */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf hat_setup(save_as->a_hat, 0); /* switch back from kernel hat */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf hat_unload(kas.a_hat, (caddr_t)wp, PAGESIZE, HAT_UNLOAD);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf hat_unload(kas.a_hat, (caddr_t)(uintptr_t)rm_platter_pa, MMU_PAGESIZE,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * cmi_post_mpstartup() is only required upon boot not upon
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * resume from RAM
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf /* Tear down 1:1 mapping for wakeup code */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf/* ARGSUSED */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (0);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf hat_devload(kas.a_hat, (caddr_t)wp, PAGESIZE, btop(wakephys),
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf (PROT_READ|PROT_WRITE|PROT_EXEC|HAT_STORECACHING_OK|HAT_NOSYNC),
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf hat_setup(kas.a_hat, 0); /* switch to kernel-only hat */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("prt_other_cpus() other cpu table empty for "
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf "uniprocessor machine\n"))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("prt_other_cpus() who = %d, gdt=%p:%x, "
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf "idt=%p:%x, ldt=%lx, tr=%lx, kgsbase="
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Power down the system.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf rm_platter_t *real_mode_platter = (rm_platter_t *)rm_platter_va;
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf extern void kernel_wc_code();
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf /* Setup 1:1 mapping for wakeup code */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("wc_rm_end - wc_rm_start=%lx WC_CODESIZE=%x\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf ((size_t)((uint_t)wc_rm_end - (uint_t)wc_rm_start)), WC_CODESIZE))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf ASSERT(((size_t)((uint_t)wc_rm_end - (uint_t)wc_rm_start)) <
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf /* Copy code to rm_platter */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_cr4=%lx, getcr4()=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf (ulong_t)real_mode_platter->rm_cr4, (ulong_t)getcr4()))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_pdbr=%lx, getcr3()=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Since the CPU needs to jump to protected mode using an identity
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * mapped address, we need to calculate it here.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf real_mode_platter->rm_longmode64_addr = rm_platter_pa +
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_cr4=%lx, getcr4()=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_pdbr=%lx, getcr3()=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_longmode64_addr=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf ret = i_cpr_platform_alloc(&(wc_other_cpus->wc_apic_state));
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf ret = i_cpr_save_apic(&(wc_other_cpus->wc_apic_state));
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("%s: i_cpr_save_apic() returned %d\n", str, ret))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("ebx=%x, edi=%x, esi=%x, ebp=%x, esp=%x\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf cpup->wc_ebx, cpup->wc_edi, cpup->wc_esi, cpup->wc_ebp,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("cs=%x, ds=%x, es=%x, ss=%x, fs=%lx, gs=%lx, "
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("gdt=%p:%x, idt=%p:%x, ldt=%lx, tr=%lx, "
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf init_real_mode_platter(0, code_length, cpup->wc_cr4, gdt);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_cr4=%lx, getcr4()=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_pdbr=%lx, getcr3()=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("real_mode_platter->rm_longmode64_addr=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf ("real_mode_platter->rm_temp_gdt[TEMPGDT_KCODE64]=%lx\n",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("gdt=%p:%x, idt=%p:%x, ldt=%lx, tr=%lx, "
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf wcpp->rm_idt_lim, (long)cpup->wc_ldt, (long)cpup->wc_tr,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf power_req.req.ppm_power_enter_sx_req.wakephys = wakephys;
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("%s: pm_ctlops PMR_PPM_ENTER_SX\n", str))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf (void) pm_ctlops(ppm, ddi_root_node(), DDI_CTLOPS_POWER,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * If it works, we get control back to the else branch below
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * If we get control back here, it didn't work.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * XXX return EINVAL here?
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("%s: pm_ctlops PMR_PPM_EXIT_SX\n", str))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf (void) pm_ctlops(ppm, ddi_root_node(), DDI_CTLOPS_POWER,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf ret = i_cpr_restore_apic(&(wc_other_cpus->wc_apic_state));
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * the restore should never fail, if the saved suceeded
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf i_cpr_platform_free(&(wc_other_cpus->wc_apic_state));
643e2e74e1c00e6b3d1896a6a67dbdb7308135c3bholler * Enable interrupts on boot cpu.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Stop all other cpu's before halting or rebooting. We pause the cpu's
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * instead of sending a cross call.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Stolen from sun4/os/mp_states.c
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (0);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * The next statement tests if a specific platform has turned off
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * cpr support.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (0);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * If a platform has specifically turned on cpr support ...
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (1);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Needed only for S3 so far
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("cpu = %d, %s(%p) \n", CPU->cpu_id, str, (void *)req))
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg PMD(PMD_SX, ("%s() : psm_state == NULL\n", str))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (0);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Needed only for S3 so far
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("cpu = %d, %s(%p) \n", CPU->cpu_id, str, (void *)req))
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg PMD(PMD_SX, ("%s() : psm_state == NULL\n", str))
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg PMD(PMD_SX, ("%s() : psm_state == NULL\n", str))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (0);
55d507a98872ca680fb002fbfda82397def13241Seth Goldberg PMD(PMD_SX, ("%s() : psm_state == NULL\n", str))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf return (0);
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf/* stop lint complaining about offset not being used in 32bit mode */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf#if !defined(__amd64)
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf/*ARGSUSED*/
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyfinit_real_mode_platter(int cpun, uint32_t offset, uint_t cr4, wc_desctbr_t gdt)
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf rm_platter_t *real_mode_platter = (rm_platter_t *)rm_platter_va;
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Fill up the real mode platter to make it easy for real mode code to
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * kick it off. This area should really be one passed by boot to kernel
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * and guaranteed to be below 1MB and aligned to 16 bytes. Should also
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * have identical physical and virtual address in paged mode.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf panic("Cannot initialize CPUs; kernel's 64-bit page tables\n"
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf "located above 4G in physical memory (@ 0x%llx).",
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf (unsigned long long)getcr3());
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Setup pseudo-descriptors for temporary GDT and IDT for use ONLY
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * by code in real_mode_start():
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * GDT[0]: NULL selector
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * GDT[1]: 64-bit CS: Long = 1, Present = 1, bits 12, 11 = 1
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Clear the IDT as interrupts will be off and a limit of 0 will cause
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * the CPU to triple fault and reset on an NMI, seemingly as reasonable
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * a course of action as any other, though it may cause the entire
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * platform to reset in some cases...
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf real_mode_platter->rm_temp_gdt[TEMPGDT_KCODE64] = 0x20980000000000ULL;
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf real_mode_platter->rm_temp_gdt_base = rm_platter_pa +
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Since the CPU needs to jump to protected mode using an identity
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * mapped address, we need to calculate it here.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf real_mode_platter->rm_longmode64_addr = rm_platter_pa + offset;
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf#endif /* __amd64 */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf /* return; */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * We need to Sync PAT with cpu0's PAT. We have to do
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * this with interrupts disabled.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Initialize this CPU's syscall handlers
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("%s() #1 cp->cpu_base_spl %d\n", str, cp->cpu_base_spl))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Do not need to call cpuid_pass2(), cpuid_pass3(), cpuid_pass4() or
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * init_cpu_info(), since the work that they do is only needed to
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * be done once at boot time
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("%s() cp->cpu_id %d, cp->cpu_intr_actv %d\n", str,
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * Set up the CPU module for this CPU. This can't be done before
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * this CPU is made CPU_READY, because we may (in heterogeneous systems)
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * need to go load another CPU module. The act of attempting to load
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * a module may trigger a cross-call, which will ASSERT unless this
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * cpu is CPU_READY.
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * cmi already been init'd (during boot), so do not need to do it again
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf /* return; */
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf PMD(PMD_SX, ("%s() CPU->cpu_id %d\n", str, CPU->cpu_id))
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * we allocate this only when we actually need it to save on
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * kernel memory
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf wc_other_cpus = kmem_zalloc(ncpus * sizeof (wc_cpu_t),
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf kmem_free((void *) wc_other_cpus, ncpus * sizeof (wc_cpu_t));
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * wrapper for acpica_ddi_save_resources()
2df1fe9ca32bb227b9158c67f5c00b54c20b10fdrandyf * wrapper for acpica_ddi_restore_resources()
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan * After five seconds, things are probably
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan * looking a bit bleak - explain the hang.
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan "but not running in the kernel yet\n",
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan * We waited at least 20 seconds, bail ..
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan return (0);
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan * wait at least 10ms, then check again..
4716fd887b81cd876928e6c03a0c6d0dcf362c90jan return (1);
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsendi_cpr_save_stack(kthread_t *t, wc_cpu_t *wc_cpu)
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend caddr_t start = CPR_GET_STACK_START(t); /* stack start */
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend caddr_t end = CPR_GET_STACK_END(t); /* stack end */
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend if (wc_cpu->wc_saved_stack_size < stack_size) {
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend wc_cpu->wc_saved_stack = kmem_zalloc(stack_size, KM_SLEEP);
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend bcopy(start, wc_cpu->wc_saved_stack, stack_size);
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsendi_cpr_restore_stack(kthread_t *t, greg_t *save_stack)
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend caddr_t start = CPR_GET_STACK_START(t); /* stack start */
3d995820f4ce8cd712d97f05aae6d30d9952d298Joseph A Townsend caddr_t end = CPR_GET_STACK_END(t); /* stack end */