pwrnow.c revision 4b3651bda421ca87fe4c05950903b87abb7c8525
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/x86_archext.h>
#include <sys/machsystm.h>
#include <sys/cpu_acpi.h>
/*
* Error returns
*/
#define PWRNOW_RET_SUCCESS 0x00
#define PWRNOW_RET_NO_PM 0x01
#define PWRNOW_RET_UNSUP_STATE 0x02
#define PWRNOW_RET_TRANS_INCOMPLETE 0x03
#define PWRNOW_LATENCY_WAIT 10
/*
* MSR registers for changing and reading processor power state.
*/
#define PWRNOW_PERF_CTL_MSR 0xC0010062
#define PWRNOW_PERF_STATUS_MSR 0xC0010063
/*
* Debugging support
*/
#ifdef DEBUG
volatile int pwrnow_debug = 0;
#else
#define PWRNOW_DEBUG(arglist)
#endif
typedef struct pwrnow_state {
/*
* Read the status register.
*/
static int
{
int ret = 0;
switch (pct_stat->pc_addrspace_id) {
ret = 0;
break;
default:
return (-1);
}
return (ret);
}
/*
* Write the ctrl register.
*/
static int
{
int ret = 0;
switch (pct_ctrl->pc_addrspace_id) {
ret = 0;
break;
default:
return (-1);
}
return (ret);
}
/*
* Transition the current processor to the requested state.
*/
void
{
int i;
/*
* Initiate the processor p-state change.
*/
return;
}
/* Wait until switch is complete, but bound the loop just in case. */
i -= PWRNOW_LATENCY_WAIT) {
break;
}
return;
}
}
int
{
int ret;
return (ret);
}
/*
* Validate that this processor supports PowerNow! and if so,
* get the P-state data from ACPI and cache it.
*/
int
{
struct cpuid_regs cpu_regs;
int domain;
PWRNOW_DEBUG(("pwrnow_init: instance %d\n",
if (x86_vendor != X86_VENDOR_AMD ||
!(x86_feature & X86_CPUID) ||
!(x86_feature & X86_MSR)) {
PWRNOW_DEBUG(("Either not AMD or feature not supported.\n"));
return (PWRNOW_RET_NO_PM);
}
/*
* Get the Advanced Power Management Information.
*/
(void) __cpuid_insn(&cpu_regs);
PWRNOW_DEBUG(("No support for CPUs that are not P-state "
"TSC invariant.\n"));
return (PWRNOW_RET_NO_PM);
}
PWRNOW_DEBUG(("Hardware P-State control is not supported.\n"));
return (PWRNOW_RET_NO_PM);
}
/*
* Just greyhound at this point.
*/
if (family != 0x10) {
PWRNOW_DEBUG(("CPUPM currently only supported for 0x10.\n"));
return (PWRNOW_RET_NO_PM);
}
/*
* PowerNow! requires ACPI support. Get a handle
* to the correct processor object for this dip.
*/
"unable to get ACPI handle",
return (PWRNOW_RET_NO_PM);
}
if (cpu_acpi_cache_data(handle) != 0) {
PWRNOW_DEBUG(("Failed to cache ACPI data\n"));
return (PWRNOW_RET_NO_PM);
}
switch (pct_stat->pc_addrspace_id) {
PWRNOW_DEBUG(("Transitions will use fixed hardware\n"));
break;
default:
return (PWRNOW_RET_NO_PM);
}
else {
}
PWRNOW_DEBUG(("Instance %d succeeded.\n",
return (PWRNOW_RET_SUCCESS);
}
/*
* Free resources allocated by pwrnow_init().
*/
void
{
}