41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * CDDL HEADER START
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * The contents of this file are subject to the terms of the
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * Common Development and Distribution License (the "License").
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * You may not use this file except in compliance with the License.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * or http://www.opensolaris.org/os/licensing.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * See the License for the specific language governing permissions
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * and limitations under the License.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * When distributing Covered Code, include this CDDL HEADER in each
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * If applicable, add the following below this CDDL HEADER, with the
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * fields enclosed by brackets "[]" replaced with your own identifying
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * information: Portions Copyright [yyyy] [name of copyright owner]
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Intel Corporation.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * All rights reserved.
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/time.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/psm_common.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/apic.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/x86_archext.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/archsystm.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/machsystm.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/cpuvar.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/clock.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems#include <sys/apic_timer.h>
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * preferred apic timer mode, allow tuning from the /etc/system file.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsint apic_timer_preferred_mode = APIC_TIMER_MODE_DEADLINE;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsint apic_oneshot = 0;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsuint_t apic_hertz_count;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsuint_t apic_nsec_per_intr = 0;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsuint64_t apic_ticks_per_SFnsecs; /* # of ticks in SF nsecs */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic int apic_min_timer_ticks = 1; /* minimum timer tick */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic hrtime_t apic_nsec_max;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void periodic_timer_enable(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void periodic_timer_disable(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void periodic_timer_reprogram(hrtime_t);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void oneshot_timer_enable(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void oneshot_timer_disable(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void oneshot_timer_reprogram(hrtime_t);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void deadline_timer_enable(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void deadline_timer_disable(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic void deadline_timer_reprogram(hrtime_t);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsextern int apic_clkvect;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsextern uint32_t apic_divide_reg_init;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * apic timer data structure
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemstypedef struct apic_timer {
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems void (*apic_timer_enable_ops)(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems void (*apic_timer_disable_ops)(void);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems void (*apic_timer_reprogram_ops)(hrtime_t);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsstatic apic_timer_t apic_timer;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * apic timer initialization
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * For the one-shot mode request case, the function returns the
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * resolution (in nanoseconds) for the hardware timer interrupt.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * If one-shot mode capability is not available, the return value
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsapic_timer_init(int hertz)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems uint_t apic_ticks = 0;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems int ret, timer_mode;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems uint16_t pit_ticks_adj;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems static int firsttime = 1;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems /* first time calibrate on CPU0 only */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_INIT_COUNT, APIC_MAXVAL);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_ticks = apic_calibrate(apicadr, &pit_ticks_adj);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems /* total number of PIT ticks corresponding to apic_ticks */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems pit_ticks = APIC_TIME_COUNT + pit_ticks_adj;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * Determine the number of nanoseconds per APIC clock tick
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * and then determine how many APIC ticks to interrupt at the
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * desired frequency
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * apic_ticks / (pitticks / PIT_HZ) = apic_ticks_per_s
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * (apic_ticks * PIT_HZ) / pitticks = apic_ticks_per_s
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * apic_ticks_per_ns = (apic_ticks * PIT_HZ) / (pitticks * 10^9)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * pic_ticks_per_SFns =
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * (SF * apic_ticks * PIT_HZ) / (pitticks * 10^9)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_ticks_per_SFnsecs = ((SF * apic_ticks * PIT_HZ) /
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ((uint64_t)pit_ticks * NANOSEC));
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems /* the interval timer initial count is 32 bit max */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_nsec_max = APIC_TICKS_TO_NSECS(APIC_MAXVAL);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems /* requested one_shot */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * return 0 if TSC is not supported.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems if (!tsc_gethrtime_enable)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * return 0 if one_shot is not preferred.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * here, APIC_TIMER_DEADLINE is also an one_shot mode.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems if ((apic_timer_preferred_mode != APIC_TIMER_MODE_ONESHOT) &&
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_timer_preferred_mode != APIC_TIMER_MODE_DEADLINE))
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ret = (int)APIC_TICKS_TO_NSECS(1);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems if ((apic_timer_preferred_mode == APIC_TIMER_MODE_DEADLINE) &&
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems cpuid_deadline_tsc_supported()) {
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems timer_mode = APIC_TIMER_MODE_DEADLINE;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems timer_mode = APIC_TIMER_MODE_ONESHOT;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_nsec_per_intr = NANOSEC / hertz;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_hertz_count = APIC_NSECS_TO_TICKS(apic_nsec_per_intr);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems /* program the local APIC to interrupt at the given frequency */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_INIT_COUNT, apic_hertz_count);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_LOCAL_TIMER,
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_clkvect + APIC_BASE_VECT) | AV_PERIODIC);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems timer_mode = APIC_TIMER_MODE_PERIODIC;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ret = NANOSEC / hertz;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * initialize apic_timer data structure, install the timer ops
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.mode = timer_mode;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems switch (timer_mode) {
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems case APIC_TIMER_MODE_ONESHOT:
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_enable_ops = oneshot_timer_enable;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_disable_ops = oneshot_timer_disable;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_reprogram_ops = oneshot_timer_reprogram;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems case APIC_TIMER_MODE_PERIODIC:
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_enable_ops = periodic_timer_enable;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_disable_ops = periodic_timer_disable;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_reprogram_ops = periodic_timer_reprogram;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems case APIC_TIMER_MODE_DEADLINE:
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_enable_ops = deadline_timer_enable;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_disable_ops = deadline_timer_disable;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_reprogram_ops = deadline_timer_reprogram;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * periodic timer mode ops
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* periodic timer enable */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsperiodic_timer_enable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_LOCAL_TIMER,
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_clkvect + APIC_BASE_VECT) | AV_PERIODIC);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* periodic timer disable */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsperiodic_timer_disable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_LOCAL_TIMER,
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_clkvect + APIC_BASE_VECT) | AV_MASK);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* periodic timer reprogram */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsperiodic_timer_reprogram(hrtime_t time)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems /* time is the interval for periodic mode */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ticks = APIC_NSECS_TO_TICKS(time);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems if (ticks < apic_min_timer_ticks)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ticks = apic_min_timer_ticks;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_INIT_COUNT, ticks);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * oneshot timer mode ops
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* oneshot timer enable */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsoneshot_timer_enable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_LOCAL_TIMER,
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_clkvect + APIC_BASE_VECT));
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* oneshot timer disable */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsoneshot_timer_disable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_LOCAL_TIMER,
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_clkvect + APIC_BASE_VECT) | AV_MASK);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* oneshot timer reprogram */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsoneshot_timer_reprogram(hrtime_t time)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * requested to generate an interrupt in the past
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * generate an interrupt as soon as possible
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ticks = apic_min_timer_ticks;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems } else if (delta > apic_nsec_max) {
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * requested to generate an interrupt at a time
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * further than what we are capable of. Set to max
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * the hardware can handle
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ticks = APIC_MAXVAL;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems cmn_err(CE_CONT, "apic_timer_reprogram, request at"
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems " %lld too far in future, current time"
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems " %lld \n", time, now);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ticks = APIC_NSECS_TO_TICKS(delta);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems if (ticks < apic_min_timer_ticks)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ticks = apic_min_timer_ticks;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_INIT_COUNT, ticks);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * deadline timer mode ops
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* deadline timer enable */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsdeadline_timer_enable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_LOCAL_TIMER,
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_clkvect + APIC_BASE_VECT) | AV_DEADLINE);
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * Now we have to serialize this per the SDM. That is to
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * say, the above enabling can race in the pipeline with
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * changes to the MSR. We need to make sure the above
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * operation is complete before we proceed to reprogram
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * the deadline value in reprogram(). The algorithm
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * recommended by the Intel SDM 3A in 10.5.1.4 is:
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * a) write a big value to the deadline register
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * b) read the register back
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * c) if it reads zero, go back to a and try again
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore /* write a really big value */
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore } while (ticks == 0);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* deadline timer disable */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsdeadline_timer_disable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_LOCAL_TIMER,
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems (apic_clkvect + APIC_BASE_VECT) | AV_MASK);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems/* deadline timer reprogram */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsdeadline_timer_reprogram(hrtime_t time)
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * Note that this entire routine is called with
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore * CBE_HIGH_PIL, so we needn't worry about preemption.
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore /* The unscalehrtime wants unsigned values. */
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore /* Now we shouldn't be interrupted, we can set the deadline */
223b8c65a9498294013b99c37d5b9024433237ecGarrett D'Amore ticks = (uint64_t)tsc_read() + unscalehrtime(delta);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems wrmsr(IA32_DEADLINE_TSC_MSR, ticks);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * This function will reprogram the timer.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * When in oneshot mode the argument is the absolute time in future to
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * generate the interrupt at.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * When in periodic mode, the argument is the interval at which the
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * interrupts should be generated. There is no need to support the periodic
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * mode timer change at this time.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsapic_timer_reprogram(hrtime_t time)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * we should be Called from high PIL context (CBE_HIGH_PIL),
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * so kpreempt is disabled.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_reprogram_ops(time);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * This function will enable timer interrupts.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsapic_timer_enable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * we should be Called from high PIL context (CBE_HIGH_PIL),
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * so kpreempt is disabled.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_enable_ops();
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * This function will disable timer interrupts.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsapic_timer_disable(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * we should be Called from high PIL context (CBE_HIGH_PIL),
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * so kpreempt is disabled.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_timer.apic_timer_disable_ops();
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * Set timer far into the future and return timer
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * current count in nanoseconds.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsapic_timer_stop_count(void)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems int enable_val, count_val;
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * Should be called with interrupts disabled.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ASSERT(!interrupts_enabled());
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems enable_val = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems if ((enable_val & AV_MASK) == AV_MASK)
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems return ((hrtime_t)-1); /* timer is disabled */
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems count_val = apic_reg_ops->apic_read(APIC_CURR_COUNT);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems ns_val = APIC_TICKS_TO_NSECS(count_val);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems apic_reg_ops->apic_write(APIC_INIT_COUNT, APIC_MAXVAL);
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystems * Reprogram timer after Deep C-State.
41afdfa77f9af46beb3aaab2eccc0d9afe660d31Krishnendu Sadhukhan - Sun Microsystemsapic_timer_restart(hrtime_t time)