apic_regops.c revision d23e508cd51e6b3ec3f10a427259d7dd2592fa94
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include <sys/archsystm.h>
#include <sys/ddi_impldefs.h>
#include <sys/mach_intr.h>
#include <sys/sysmacros.h>
#include <sys/x86_archext.h>
#include <sys/privregs.h>
#include <sys/psm_common.h>
/* Function prototypes of local apic and X2APIC */
static int get_local_apic_pri(void);
static int get_local_x2apic_pri(void);
/*
* According to the X2APIC specification:
*
* xAPIC global enable X2APIC enable Description
* (IA32_APIC_BASE[11]) (IA32_APIC_BASE[10])
* -----------------------------------------------------------
* 0 0 APIC is disabled
* 0 1 Invalid
* 1 0 APIC is enabled in xAPIC mode
* 1 1 APIC is enabled in X2APIC mode
* -----------------------------------------------------------
*/
int x2apic_enable = 1;
/* Uses MMIO (Memory Mapped IO) */
static apic_reg_ops_t local_apic_regs_ops = {
};
static apic_reg_ops_t x2apic_regs_ops = {
};
/* The default ops is local APIC (Memory Mapped IO) */
/*
* APIC register ops related data sturctures and functions.
*/
int apic_direct_EOI = 0; /* Directed EOI Support */
void apic_send_EOI();
#define X2APIC_CPUID_BIT 21
#define X2APIC_ENABLE_BIT 10
/*
* Local APIC Implementation
*/
static uint64_t
{
}
static void
{
}
static int
get_local_apic_pri(void)
{
#if defined(__amd64)
return ((int)getcr8());
#else
return (apicadr[APIC_TASK_REG]);
#endif
}
static void
{
#if defined(__amd64)
#else
#endif
}
static void
{
}
/*
* X2APIC Implementation.
*/
static uint64_t
{
uint64_t i;
return (i);
}
static void
{
if (msr != APIC_EOI_REG) {
} else {
tmp = 0;
}
}
static int
get_local_x2apic_pri(void)
{
}
static void
{
}
static void
{
}
/*ARGSUSED*/
void
{
}
/*
* Support for Directed EOI capability is available in both the xAPIC
* and x2APIC mode.
*/
void
{
short intr_index;
/*
* Following the EOI to the local APIC unit, perform a directed
* EOI to the IOxAPIC generating the interrupt by writing to its
* EOI register.
*
* A broadcast EOI is not generated.
*/
while (apic_irq) {
}
}
}
int
apic_detect_x2apic(void)
{
struct cpuid_regs cp;
if (x2apic_enable == 0)
return (0);
(void) __cpuid_insn(&cp);
}
void
apic_enable_x2apic(void)
{
if (apic_local_mode() == LOCAL_X2APIC) {
/* BIOS apparently has enabled X2APIC */
if (apic_mode != LOCAL_X2APIC)
return;
}
/*
* This is the first time we are enabling X2APIC on this CPU
*/
if (apic_mode != LOCAL_X2APIC)
}
/*
* Determine which mode the current CPU is in. See the table above.
* (IA32_APIC_BASE[11]) (IA32_APIC_BASE[10])
*/
int
apic_local_mode(void)
{
(0x1 << X2APIC_ENABLE_BIT));
return (LOCAL_X2APIC);
else
return (LOCAL_APIC);
}
void
{
}
/*
* Change apic_reg_ops depending upon the apic_mode.
*/
void
{
if (apic_mode == LOCAL_APIC)
else if (apic_mode == LOCAL_X2APIC)
}
/*
* Generates an interprocessor interrupt to another CPU when X2APIC mode is
* enabled.
*/
void
{
int vector;
/*
* With X2APIC, Intel relaxed the semantics of the
* WRMSR instruction such that references to the X2APIC
* MSR registers are no longer serializing instructions.
* The code that initiates IPIs assumes that some sort
* of memory serialization occurs. The old APIC code
* did a write to uncachable memory mapped registers.
* Any reference to uncached memory is a serializing
* operation. To mimic those semantics here, we do an
* atomic operation, which translates to a LOCK OR instruction,
* which is serializing.
*/
flag = intr_clear();
/*
* According to X2APIC specification in section '2.3.5.1' of
* Interrupt Command Register Semantics, the semantics of
* programming Interrupt Command Register to dispatch an interrupt
* is simplified. A single MSR write to the 64-bit ICR is required
* for dispatching an interrupt. Specifically with the 64-bit MSR
* interface to ICR, system software is not required to check the
* status of the delivery status bit prior to writing to the ICR
* to send an IPI. With the removal of the Delivery Status bit,
* system software no longer has a reason to read the ICR. It remains
* readable only to aid in debugging.
*/
#ifdef DEBUG
#endif /* DEBUG */
if ((cpun == psm_get_cpu_id()))
else
}
/*
* Generates IPI to another CPU depending on the local APIC mode.
* apic_send_ipi() and x2apic_send_ipi() depends on the configured
* mode of the local APIC, but that may not match the actual mode
* early in CPU startup.
*
* Any changes made to this routine must be accompanied by similar
* changes to apic_send_ipi().
*/
void
{
int vector;
int mode = apic_local_mode();
if (mode == LOCAL_X2APIC) {
return;
}
flag = intr_clear();
apic_ret();
vector);
}