apic.h revision 450d696485d078017a0c7d3eef7384ee79c9f467
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_APIC_APIC_H
#define _SYS_APIC_APIC_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/psm_common.h>
#define APIC_IO_ADDR 0xfec00000
#define APIC_LOCAL_ADDR 0xfee00000
#define APIC_IO_MEMLEN 0xf
#define APIC_LOCAL_MEMLEN 0xfffff
/* Local Unit ID register */
#define APIC_LID_REG 0x8
/* I/o Unit Version Register */
#define APIC_VERS_REG 0xc
/* Task Priority register */
#define APIC_TASK_REG 0x20
/* EOI register */
#define APIC_EOI_REG 0x2c
/* Remote Read register */
#define APIC_REMOTE_READ 0x30
/* Logical Destination register */
#define APIC_DEST_REG 0x34
/* Destination Format rgister */
#define APIC_FORMAT_REG 0x38
/* Spurious Interrupt Vector register */
#define APIC_SPUR_INT_REG 0x3c
/* Error Status Register */
#define APIC_ERROR_STATUS 0xa0
/* Interrupt Command registers */
#define APIC_INT_CMD1 0xc0
#define APIC_INT_CMD2 0xc4
/* Timer Vector Table register */
#define APIC_LOCAL_TIMER 0xc8
/* Local Interrupt Vector registers */
#define APIC_PCINT_VECT 0xd0
#define APIC_INT_VECT0 0xd4
#define APIC_INT_VECT1 0xd8
#define APIC_ERR_VECT 0xdc
/* IPL for performance counter interrupts */
#define APIC_PCINT_IPL 0xe
/* Initial Count register */
#define APIC_INIT_COUNT 0xe0
/* Current Count Register */
#define APIC_CURR_COUNT 0xe4
/* Divider Configuration Register */
#define APIC_DIVIDE_REG 0xf8
/* IRR register */
#define APIC_IRR_REG 0x80
/* ISR register */
#define APIC_ISR_REG 0x40
#define APIC_IO_REG 0x0
#define APIC_IO_DATA 0x4
/* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
#define APIC_ID_BIT_OFFSET 24
#define APIC_ICR_ID_BIT_OFFSET 24
#define APIC_LDR_ID_BIT_OFFSET 24
/*
* Choose between flat and clustered models by writing the following to the
* FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will
* disable logical destination mode.
* Does not seem to be in the docs for local APICs on the processors.
*/
#define APIC_FLAT_MODEL 0xFFFFFFFFUL
#define APIC_CLUSTER_MODEL 0x0FFFFFFF
/*
* The commands which follow are window selectors written to APIC_IO_REG
*/
#define APIC_ID_CMD 0x0
#define APIC_VERS_CMD 0x1
#define APIC_RDT_CMD 0x10
#define APIC_RDT_CMD2 0x11
#define APIC_INT_SPURIOUS -1
/*
* MP floating pointer structure defined in Intel MP Spec 1.1
*/
struct apic_mpfps_hdr {
};
#define APIC_MPS_OEM_ID_LEN 8
#define APIC_MPS_PROD_ID_LEN 12
struct apic_mp_cnf_hdr {
mpcnf_spec: 8,
mpcnf_cksum: 8;
char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN];
mpcnf_entry_cnt: 16;
};
struct apic_procent {
proc_apicid: 8,
proc_version: 8,
proc_cpuflags: 8;
proc_model: 4,
proc_family: 4,
proc_resv1: 18;
};
/*
* proc_cpuflags definitions
*/
struct apic_bus {
};
struct apic_io_entry {
io_apicid: 8,
io_version: 8,
io_flags: 8;
};
struct apic_io_intr {
intr_type: 8,
intr_po: 2,
intr_el: 2,
intr_resv: 12;
intr_irq: 8,
intr_destid: 8,
intr_destintin: 8;
};
/*
* intr_type definitions
*/
#define IO_INTR_INT 0x00
#define IO_INTR_NMI 0x01
#define IO_INTR_SMI 0x02
#define IO_INTR_EXTINT 0x03
/*
* destination APIC ID
*/
#define INTR_ALL_APIC 0xff
/* local vector table */
#define AV_MASK 0x10000
/* interrupt command register 32-63 */
#define AV_TOALL 0x7fffffff
#define AV_HIGH_ORDER 0x40000000
#define AV_IM_OFF 0x40000000
/* interrupt command register 0-31 */
#define AV_FIXED 0x000
#define AV_LOPRI 0x100
#define AV_REMOTE 0x300
#define AV_NMI 0x400
#define AV_RESET 0x500
#define AV_STARTUP 0x600
#define AV_EXTINT 0x700
#define AV_PDEST 0x000
#define AV_LDEST 0x800
/* IO & Local APIC Bit Definitions */
#define AV_PENDING 0x1000
#define AV_LEVEL 0x8000
#define AV_DEASSERT AV_LEVEL
#define AV_ASSERT 0xc000
#define AV_READ_PENDING 0x10000
/* spurious interrupt vector register */
#define AV_UNIT_ENABLE 0x100
/* timer vector table */
#define APIC_MAXVAL 0xffffffffUL
#define APIC_TIME_MIN 0x5000
#define APIC_TIME_COUNT 0x4000
/*
* Range of the low byte value in apic_tick before starting calibration
*/
#define APIC_LB_MIN 0x60
#define APIC_LB_MAX 0xe0
#define APIC_MAX_VECTOR 255
#define APIC_RESV_VECT 0x00
#define APIC_RESV_IRQ 0xfe
#define APIC_VECTOR_MASK 0x0f
#define APIC_IPL_MASK 0xf0
#define APIC_FIRST_FREE_IRQ 0x10
#define APIC_MAX_ISA_IRQ 15
#define APIC_IDLE_IPL 0x00
/* spurious interrupt vector */
#define APIC_SPUR_INTR 0xFF
/* cmos shutdown code for BIOS */
#define BIOS_SHUTDOWN 0x0a
/* define the entry types for BIOS information tables as defined in PC+MP */
#define APIC_CPU_ENTRY 0
#define APIC_BUS_ENTRY 1
#define APIC_IO_ENTRY 2
#define APIC_IO_INTR_ENTRY 3
#define APIC_LOCAL_INTR_ENTRY 4
/*
* The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
* of system base memory or in ROM between 0xF0000 and 0xFFFFF
*/
#define MPFPS_RAM_WIN_LEN 1024
#define MPFPS_ROM_WIN_LEN 0x10000
#define EISA_LEVEL_CNTL 0x4D0
/* definitions for apic_irq_table */
#define DEFAULT_INDEX (short)0x7FFF
/* biggest positive no. to avoid conflict with actual index */
#define APIC_IS_MSI_OR_MSIX_INDEX(index) \
/*
* definitions for MSI Address
*/
#define MSI_ADDR_HDR APIC_LOCAL_ADDR
#define MSI_ADDR_RH_SHIFT 3
#define MSI_ADDR_DM_SHIFT 2
/*
* definitions for MSI Data
*/
#define MSI_DATA_DELIVERY_SMI 0x2
#define MSI_DATA_DELIVERY_NMI 0x4
#define MSI_DATA_DELIVERY_INIT 0x5
#define MSI_DATA_DELIVERY_EXTINT 0x7
#define MSI_DATA_DELIVERY_SHIFT 8
#define MSI_DATA_TM_SHIFT 15
#define MSI_DATA_LEVEL_DEASSERT 0x0
#define MSI_DATA_LEVEL_SHIFT 14
/*
* use to define each irq setup by the apic
*/
typedef struct apic_irq {
short airq_mps_intr_index; /* index into mps interrupt entries */
/* table */
/*
* IRQ could be shared (in H/W) in which case dip & major will be
* for the one that was last added at this level. We cannot keep a
* linked list as delspl does not tell us which device has just
* been unloaded. For most servers where we are worried about
* performance, interrupt should not be shared & should not be
* a problem. This does not cause any correctness issue - dip is
* used only as an optimisation to avoid going thru all the tables
* in translate IRQ (which is always called twice due to brokenness
* in the way IPLs are determined for devices). major is used only
* to bind interrupts corresponding to the same device on the same
* CPU. Not finding major will just cause it to be potentially bound
* to another CPU.
*/
/* us in this */
} apic_irq_t;
/* Macros to help deal with shared interrupts */
typedef struct apic_cpus_info {
/*
* fill to make sure each struct is in seperate cache line.
* Or atleast that ISR_in_progress/curipl is not shared with something
* Given kmem_alloc guarantees alignment to 8 bytes, having 8
* bytes on each side will isolate us in a 16 byte cache line.
*/
#define APIC_CPU_ONLINE 1
#define APIC_CPU_INTR_ENABLE 2
/*
* Various poweroff methods and ports & bits for them
*/
#define APIC_POWEROFF_NONE 0
#define APIC_POWEROFF_VIA_RTC 1
#define APIC_POWEROFF_VIA_ASPEN_BMC 2
#define APIC_POWEROFF_VIA_SITKA_BMC 3
/* For RTC */
#define RTC_REGA 0x0a
#define PAB_CBIT 0x08
#define WF_FLAG 0x02
#define KS_FLAG 0x01
#define EXT_BANK 0x10
#define CC_SMS_GET_STATUS 0x40
#define CC_SMS_WR_START 0x41
#define CC_SMS_WR_NEXT 0x42
#define CC_SMS_WR_END 0x43
#define MISMIC_DATA_REGISTER 0x0ca9
#define MISMIC_CNTL_REGISTER 0x0caa
#define MISMIC_FLAG_REGISTER 0x0cab
#define MISMIC_BUSY_MASK 0x01
#define SMS_GET_STATUS 0x60
#define SMS_WRITE_START 0x61
#define SMS_WRITE_END 0x62
#define SMS_DATA_REGISTER 0x0ca2
#define SMS_STATUS_REGISTER 0x0ca3
#define SMS_COMMAND_REGISTER 0x0ca3
#define SMS_IBF_MASK 0x02
#define SMS_STATE_MASK 0xc0
#define SMS_IDLE_STATE 0x00
#define SMS_READ_STATE 0x40
#define SMS_WRITE_STATE 0x80
#define SMS_ERROR_STATE 0xc0
(addr)[APIC_IO_DATA])
(addr)[APIC_IO_DATA])
#ifdef __cplusplus
}
#endif
#endif /* _SYS_APIC_APIC_H */