apic.c revision f34a71784df3fbc5d1227a7b6201fd318ad1667e
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* PSMI 1.1 extensions are supported only in 2.6 and later versions.
* PSMI 1.2 extensions are supported only in 2.7 and later versions.
* PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
* PSMI 1.5 extensions are supported in Solaris Nevada.
* PSMI 1.6 extensions are supported in Solaris Nevada.
*/
#define PSMI_1_6
#include <sys/processor.h>
#include <sys/smp_impldefs.h>
#include <sys/psm_common.h>
#include <sys/ddi_impldefs.h>
#include <sys/x86_archext.h>
#include <sys/cpc_impl.h>
#include <sys/archsystm.h>
#include <sys/machsystm.h>
#include <sys/sysmacros.h>
#include <sys/rm_platter.h>
#include <sys/privregs.h>
#include <sys/pci_intr_lib.h>
#include <sys/dditypes.h>
/*
* Local Function Prototypes
*/
static void apic_init_intr();
/*
* standard MP entries
*/
static int apic_probe();
static int apic_clkinit();
static int apic_getclkirq(int ipl);
static hrtime_t apic_gettime();
static hrtime_t apic_gethrtime();
static void apic_init();
static void apic_picinit(void);
static int apic_post_cpu_start(void);
static void apic_setspl(int ipl);
static void x2apic_setspl(int ipl);
static void apic_timer_enable(void);
static void apic_timer_disable(void);
static void apic_post_cyclic_setup(void *arg);
static void apic_intrr_init(int apic_mode);
static int apic_oneshot = 0;
/* Now the ones for Dynamic Interrupt distribution */
int apic_enable_dynamic_migration = 0;
/*
* These variables are frequently accessed in apic_intr_enter(),
* apic_intr_exit and apic_setspl, so group them together
*/
int apic_clkvect;
/* vector at which error interrupts come in */
int apic_errvect;
int apic_enable_error_intr = 1;
int apic_error_display_delay = 100;
/* vector at which performance counter overflow interrupts come in */
int apic_cpcovf_vect;
int apic_enable_cpcovf_intr = 1;
/* vector at which CMCI interrupts come in */
int apic_cmci_vect;
extern int cmi_enable_cmci;
extern void cmi_cmci_trap(void);
static int cmci_cpu_setup_registered;
/*
* The following vector assignments influence the value of ipltopri and
* vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
* idle to 0 and IPL 0 to 0xf to differentiate idle in case
* we care to do so in future. Note some IPLs which are rarely used
* will share the vector ranges and heavily used IPLs (5 and 6) have
* a wide range.
*
* This array is used to initialize apic_ipls[] (in apic_init()).
*
* IPL Vector range. as passed to intr_enter
* 0 none.
* 1,2,3 0x20-0x2f 0x0-0xf
* 4 0x30-0x3f 0x10-0x1f
* 5 0x40-0x5f 0x20-0x3f
* 6 0x60-0x7f 0x40-0x5f
* 7,8,9 0x80-0x8f 0x60-0x6f
* 10 0x90-0x9f 0x70-0x7f
* 11 0xa0-0xaf 0x80-0x8f
* ... ...
* 15 0xe0-0xef 0xc0-0xcf
* 15 0xf0-0xff 0xd0-0xdf
*/
3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
};
/*
* The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
* NOTE that this is vector as passed into intr_enter which is
* programmed vector - 0x20 (APIC_BASE_VECT)
*/
/* The taskpri to be programmed into apic to mask given ipl */
#if defined(__amd64)
#endif
/*
* Correlation of the hardware vector to the IPL in use, initialized
* from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
* to the IPLs in apic_vectortoipl on some systems that share interrupt lines
* connected to errata-stricken IOAPICs
*/
/*
* Patchable global variables.
*/
int apic_forceload = 0;
/* 1 - use gettime() for performance */
int apic_flat_model = 0; /* 0 - clustered. 1 - flat */
int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
int apic_panic_on_nmi = 0;
int apic_panic_on_apic_error = 0;
int apic_verbose = 0;
/* minimum number of timer ticks to program to */
int apic_min_timer_ticks = 1;
/*
* Local static data
*/
(int (*)(int))NULL, /* psm_softlvl_to_irq */
(void (*)(int))NULL, /* psm_set_softintr */
(void (*)(void))NULL, /* psm_hrtimeinit */
(void (*)(int, char *))NULL, /* psm_notify_error */
(void (*)(int))NULL, /* psm_notify_func */
apic_intr_ops, /* Advanced DDI Interrupt framework */
apic_state, /* save, restore apic state for S3 */
};
static struct psm_info apic_psm_info = {
PSM_INFO_VER01_6, /* version */
PSM_OWN_EXCLUSIVE, /* ownership */
APIC_PCPLUSMP_NAME, /* machine name */
"pcplusmp v1.4 compatible",
};
static void *apic_hdlp;
#ifdef DEBUG
int apic_debug = 0;
int apic_restrict_vector = 0;
int apic_debug_msgbufindex = 0;
#endif /* DEBUG */
/* Flag to indicate that we need to shut down all processors */
static uint_t apic_shutdown_processors;
uint_t apic_nsec_per_intr = 0;
/*
* apic_let_idle_redistribute can have the following values:
* 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
* apic_redistribute_lock prevents multiple idle cpus from redistributing
*/
int apic_num_idle_redistributions = 0;
static int apic_let_idle_redistribute = 0;
static uint_t apic_nticks = 0;
static uint_t apic_skipped_redistribute = 0;
/* to gather intr data and redistribute */
static void apic_redistribute_compute(void);
static uint_t last_count_read = 0;
static lock_t apic_gethrtime_lock;
volatile int apic_hrtime_stamp = 0;
volatile hrtime_t apic_nsec_since_boot = 0;
static uint_t apic_hertz_count;
static hrtime_t apic_nsec_max;
static hrtime_t apic_last_hrtime = 0;
int apic_hrtime_error = 0;
int apic_remote_hrterr = 0;
int apic_num_nmis = 0;
int apic_apic_error = 0;
int apic_num_apic_errors = 0;
int apic_num_cksum_errors = 0;
int apic_error = 0;
static int apic_cmos_ssb_set = 0;
/* use to make sure only one cpu handles the nmi */
static lock_t apic_nmi_lock;
/* use to make sure only one cpu handles the error interrupt */
static lock_t apic_error_lock;
static struct {
} aspen_bmc[] = {
};
static struct {
int port;
} sitka_bmc[] = {
};
/* Patchable global variables. */
int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */
/* default apic ops without interrupt remapping */
static apic_intrr_ops_t apic_nointrr_ops = {
(int (*)(int))return_instr,
(void (*)(void))return_instr,
(void (*)(apic_irq_t *))return_instr,
(void (*)(apic_irq_t *, void *))return_instr,
(void (*)(apic_irq_t *))return_instr,
};
/*
* This is the loadable module wrapper
*/
int
_init(void)
{
if (apic_coarse_hrtime)
}
int
_fini(void)
{
}
int
{
}
static int
{
}
void
{
int i;
int j = 1;
for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
/* get to highest vector at the same ipl */
continue;
for (; j <= apic_vectortoipl[i]; j++) {
apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
}
}
for (; j < MAXIPL + 1; j++)
/* fill up any empty ipltopri slots */
#if defined(__amd64)
/*
* Make cpu-specific interrupt info point to cr8pri vector
*/
for (i = 0; i <= MAXIPL; i++)
#endif /* __amd64 */
/*
* initialize interrupt remapping before apic
* hardware initialization
*/
}
/*
* handler for APIC Error interrupt. Just print a warning and continue
*/
static int
{
uint_t i;
/*
* We need to write before read as per 7.4.17 of system prog manual.
* We do both and or the results to be safe
*/
/*
* Clear the APIC error status (do this on all cpus that enter here)
* (two writes are required due to the semantics of accessing the
* error status register.)
*/
/*
* Prevent more than 1 CPU from handling error interrupt causing
* double printing (interleave of characters from multiple
* CPU's when using prom_printf)
*/
if (lock_try(&apic_error_lock) == 0)
if (error) {
#if DEBUG
if (apic_debug)
debug_enter("pcplusmp: APIC Error interrupt received");
#endif /* DEBUG */
"APIC Error interrupt on CPU %d. Status = %x\n",
psm_get_cpu_id(), error);
else {
if ((error & ~APIC_CS_ERRORS) == 0) {
/* cksum error only */
apic_apic_error |= error;
} else {
/*
* prom_printf is the best shot we have of
* something which is problem free from
*/
prom_printf("APIC Error interrupt on CPU %d. "
"Status 0 = %x, Status 1 = %x\n",
apic_apic_error |= error;
for (i = 0; i < apic_error_display_delay; i++) {
tenmicrosec();
}
/*
* provide more delay next time limited to
* roughly 1 clock tick time
*/
if (apic_error_display_delay < 500)
apic_error_display_delay *= 2;
}
}
return (DDI_INTR_CLAIMED);
} else {
return (DDI_INTR_UNCLAIMED);
}
/* NOTREACHED */
}
/*
* Turn off the mask bit in the performance counter Local Vector Table entry.
*/
static void
apic_cpcovf_mask_clear(void)
{
}
/*ARGSUSED*/
static int
{
return (0);
}
/*ARGSUSED*/
static int
{
return (0);
}
/*ARGSUSED*/
static int
{
switch (what) {
case CPU_ON:
break;
case CPU_OFF:
break;
default:
break;
}
return (0);
}
static void
{
if (apic_mode == LOCAL_APIC) {
/*
* We are running APIC in MMIO mode.
*/
if (apic_flat_model) {
} else {
}
AV_HIGH_ORDER >> cpun);
}
if (apic_direct_EOI) {
/*
* Set 12th bit in Spurious Interrupt Vector
* Register to support level triggered interrupt
* directed EOI.
*/
}
/* need to enable APIC before unmasking NMI */
/*
* Presence of an invalid vector with delivery mode AV_FIXED can
* cause an error interrupt, even if the entry is masked...so
* write a valid vector to LVT entries along with the mask bit
*/
/* All APICs have timer and LINT0/1 */
/*
* On integrated APICs, the number of LVT entries is
* 'Max LVT entry' + 1; on 82489DX's (non-integrated
* APICs), nlvt is "3" (LINT0, LINT1, and timer)
*/
nlvt = 3;
} else {
0xFF) + 1;
}
if (nlvt >= 5) {
/* Enable performance counter overflow interrupt */
if (apic_enable_cpcovf_intr) {
if (apic_cpcovf_vect == 0) {
int ipl = APIC_PCINT_IPL;
}
}
}
if (nlvt >= 6) {
/* Only mask TM intr if the BIOS apparently doesn't use it */
}
}
/* Enable error interrupt */
if (apic_errvect == 0) {
/*
* Not PSMI compliant, but we are going to merge
* with ON anyway
*/
}
}
/* Enable CMCI interrupt */
if (cmi_enable_cmci) {
if (cmci_cpu_setup_registered == 0) {
}
if (apic_cmci_vect == 0) {
int ipl = 0x2;
}
}
}
static void
{
/* local intr reg 0 */
/* disable NMI */
/* and error interrupt */
/* and perf counter intr */
}
static void
apic_picinit(void)
{
int i, j;
/*
* On UniSys Model 6520, the BIOS leaves vector 0x20 isr
* bit on without clearing it with EOI. Since softint
* uses vector 0x20 to interrupt itself, so softint will
* not work on this machine. In order to fix this problem
* a check is made to verify all the isr bits are clear.
* If not, EOIs are issued to clear the bits.
*/
for (i = 7; i >= 1; i--) {
if (isr != 0)
for (j = 0; ((j < 32) && (isr != 0)); j++)
if (isr & (1 << j)) {
APIC_EOI_REG, 0);
isr &= ~(1 << j);
}
}
/* set a flag so we know we have run apic_picinit() */
apic_picinit_called = 1;
picsetup(); /* initialise the 8259 */
/* add nmi handler - least priority nmi handler */
/*
* In order to determine support for Directed EOI capability,
* we check for 24th bit in Local APIC Version Register.
*/
apic_direct_EOI = 1;
}
/* enable apic mode if imcr present */
if (apic_imcrp) {
}
}
/*ARGSUSED1*/
static int
{
int loop_count;
apic_cmos_ssb_set = 1;
/*
* Interrupts on BSP cpu will be disabled during these startup
* steps in order to avoid unwanted side effects from
* executing interrupt handlers on a problematic BIOS.
*/
iflag = intr_clear();
/*
* According to X2APIC specification in section '2.3.5.1' of
* Interrupt Command Register Semantics, the semantics of
* programming the Interrupt Command Register to dispatch an interrupt
* is simplified. A single MSR write to the 64-bit ICR is required
* for dispatching an interrupt. Specifically, with the 64-bit MSR
* interface to ICR, system software is not required to check the
* status of the delivery status bit prior to writing to the ICR
* to send an IPI. With the removal of the Delivery Status bit,
* system software no longer has a reason to read the ICR. It remains
* readable only to aid in debugging.
*/
#ifdef DEBUG
#else
if (apic_mode == LOCAL_APIC) {
}
#endif /* DEBUG */
/* for integrated - make sure there is one INIT IPI in buffer */
/* for external - it will wake up the cpu */
/* If only 1 CPU is installed, PENDING bit will not go low */
if (apic_mode == LOCAL_APIC &&
apic_ret();
else
break;
}
/* integrated apic */
/* to offset the INIT IPI queue up in the buffer */
}
return (0);
}
#ifdef DEBUG
int apic_break_on_cpu = 9;
int apic_stretch_interrupts = 0;
void
{
}
#endif /* DEBUG */
/*
* platform_intr_enter
*
* Called at the beginning of the interrupt service routine to
* mask all level equal to and below the interrupt priority
* of the interrupting vector. An EOI should be given to
* the interrupt controller to enable other HW interrupts.
*
* Return -1 for spurious interrupts
*
*/
/*ARGSUSED*/
static int
{
int nipl;
int irq;
/*
* The real vector delivered is (*vectorp + 0x20), but our caller
* subtracts 0x20 from the vector before passing it to us.
* (That's why APIC_BASE_VECT is 0x20.)
*/
/* if interrupted by the clock, increment apic_nsec_since_boot */
if (vector == apic_clkvect) {
if (!apic_oneshot) {
/* NOTE: this is not MT aware */
}
/* We will avoid all the book keeping overhead for clock */
if (apic_mode == LOCAL_APIC) {
#if defined(__amd64)
#else
#endif
} else {
X2APIC_WRITE(APIC_EOI_REG, 0);
}
return (nipl);
}
return (APIC_INT_SPURIOUS);
}
/* Check if the vector we got is really what we need */
if (apic_revector_pending) {
/*
* Disable interrupts for the duration of
* the vector translation to prevent a self-race for
* the apic_revector_lock. This cannot be done
* in apic_xlate_vector because it is recursive and
* we want the vector translation to be atomic with
* respect to other (higher-priority) interrupts.
*/
iflag = intr_clear();
}
if (apic_mode == LOCAL_APIC) {
#if defined(__amd64)
#else
#endif
} else {
}
/*
* apic_level_intr could have been assimilated into the irq struct.
* but, having it as a character array is more efficient in terms of
* cache usage. So, we leave it as is.
*/
if (!apic_level_intr[irq]) {
if (apic_mode == LOCAL_APIC) {
} else {
X2APIC_WRITE(APIC_EOI_REG, 0);
}
}
#ifdef DEBUG
if (apic_break_on_cpu == psm_get_cpu_id())
apic_break();
#endif /* DEBUG */
return (nipl);
}
/*
* This macro is a common code used by MMIO local apic and X2APIC
* local apic.
*/
#define APIC_INTR_EXIT() \
{ \
if (apic_level_intr[irq]) \
/* ISR above current pri could not be in progress */ \
}
/*
* Any changes made to this function must also change X2APIC
* version of intr_exit.
*/
void
{
#if defined(__amd64)
#else
#endif
}
/*
* Same as apic_intr_exit() except it uses MSR rather than MMIO
* to access local apic registers.
*/
void
{
}
psm_intr_exit_fn(void)
{
if (apic_mode == LOCAL_X2APIC)
return (x2apic_intr_exit);
return (apic_intr_exit);
}
/*
* Mask all interrupts below or equal to the given IPL.
* Any changes made to this function must also change X2APIC
* version of setspl.
*/
static void
apic_setspl(int ipl)
{
#if defined(__amd64)
#else
#endif
/* interrupts at ipl above this cannot be in progress */
/*
* this is a patch fix for the ALR QSMP P5 machine, so that interrupts
* have enough time to come in before the priority is raised again
* during the idle() loop.
*/
if (apic_setspl_delay)
(void) apic_reg_ops->apic_get_pri();
}
/*
* X2APIC version of setspl.
* Mask all interrupts below or equal to the given IPL
*/
static void
x2apic_setspl(int ipl)
{
/* interrupts at ipl above this cannot be in progress */
}
/*
* generates an interprocessor interrupt to another CPU. Any changes made to
* this routine must be accompanied by similar changes to
* apic_common_send_ipi().
*/
static void
{
int vector;
flag = intr_clear();
vector);
}
/*ARGSUSED*/
static void
{
}
/*ARGSUSED*/
static void
{
}
void
apic_ret()
{
}
/*
* If apic_coarse_time == 1, then apic_gettime() is used instead of
* apic_gethrtime(). This is used for performance instead of accuracy.
*/
static hrtime_t
{
int old_hrtime_stamp;
/*
* In one-shot mode, we do not keep time, so if anyone
* calls psm_gettime() directly, we vector over to
* gethrtime().
* one-shot mode MUST NOT be enabled if this psm is the source of
* hrtime.
*/
if (apic_oneshot)
return (gethrtime());
apic_ret();
goto gettime_again;
}
return (temp);
}
/*
* Here we return the number of nanoseconds since booting. Note every
* clock interrupt increments apic_nsec_since_boot by the appropriate
* amount.
*/
static hrtime_t
{
int old_hrtime_stamp, status;
/*
* In one-shot mode, we do not keep time, so if anyone
* calls psm_gethrtime() directly, we vector over to
* gethrtime().
* one-shot mode MUST NOT be enabled if this psm is the source of
* hrtime.
*/
if (apic_oneshot)
return (gethrtime());
if (apic_mode == LOCAL_APIC)
cpun >>= APIC_ID_BIT_OFFSET;
apic_ret();
/*
* Check to see which CPU we are on. Note the time is kept on
* the local APIC of CPU 0. If on CPU 0, simply read the current
* counter. If on another CPU, issue a remote read command to CPU 0.
*/
} else {
#ifdef DEBUG
#else
if (apic_mode == LOCAL_APIC)
#endif /* DEBUG */
& AV_READ_PENDING) {
apic_ret();
}
else { /* 0 = invalid */
/*
* return last hrtime right now, will need more
* testing if change to retry
*/
return (temp);
}
}
if (countval > last_count_read)
countval = 0;
else
/* we might have clobbered last_count_read. Restore it */
goto gethrtime_again;
}
if (temp < apic_last_hrtime) {
/* return last hrtime if error occurs */
}
else
return (temp);
}
/* apic NMI handler */
/*ARGSUSED*/
static void
{
if (apic_shutdown_processors) {
return;
}
if (!lock_try(&apic_nmi_lock))
return;
if (apic_kmdb_on_nmi && psm_debugger()) {
debug_enter("NMI received: entering kmdb\n");
} else if (apic_panic_on_nmi) {
/* Keep panic from entering kmdb. */
nopanicdebug = 1;
panic("NMI received\n");
} else {
/*
* prom_printf is the best shot we have of something which is
*/
prom_printf("NMI received\n");
}
}
/*ARGSUSED*/
static int
{
}
static int
{
}
static int
{
int cpun;
static int cpus_started = 1;
/* We know this CPU + BSP started successfully. */
cpus_started++;
/*
* On BSP we would have enabled X2APIC, if supported by processor,
* in acpi_probe(), but on AP we do it here.
*
* We enable X2APIC mode only if BSP is running in X2APIC & the
* local APIC mode of the current CPU is MMIO (xAPIC).
*/
apic_local_mode() == LOCAL_APIC) {
}
/*
* We change psm_send_ipi and send_dirintf only if Solaris
* is booted in kmdb & the current CPU is the last CPU being
* brought up. We don't need to do anything if Solaris is running
* in MMIO mode (xAPIC).
*/
apic_mode == LOCAL_X2APIC) {
/*
* We no longer need help from apic_common_send_ipi()
* since we will not start any more CPUs.
*
* We will need to revisit this if we start supporting
* hot-plugging of CPUs.
*/
}
/*
* since some systems don't enable the internal cache on the non-boot
* cpus, so we have to enable them here
*/
#ifdef DEBUG
#else
if (apic_mode == LOCAL_APIC)
#endif /* DEBUG */
/*
* We may be booting, or resuming from suspend; aci_status will
* be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
* APIC_CPU_ONLINE flag here rather than setting aci_status completely.
*/
cpun = psm_get_cpu_id();
return (PSM_SUCCESS);
}
{
int i;
if (cpu_id == -1)
return ((processorid_t)0);
if (CPU_IN_SET(apic_cpumask, i))
return (i);
}
return ((processorid_t)-1);
}
/*
* type == -1 indicates it is an internal request. Do not change
* resv_vector for these requests
*/
static int
{
int irq;
if (type != -1) {
}
return (irq);
}
}
return (-1); /* shouldn't happen */
}
static int
apic_getclkirq(int ipl)
{
int irq;
return (-1);
/*
* Note the vector in apic_clkvect for per clock handling.
*/
apic_clkvect));
return (irq);
}
/*
* Return the number of APIC clock ticks elapsed for 8245 to decrement
* (APIC_TIME_COUNT + pit_ticks_adj) ticks.
*/
static uint_t
{
iflag = intr_clear();
do {
} while (pit_tick < APIC_TIME_MIN ||
/*
* Wait for the 8254 to decrement by 5 ticks to ensure
* we didn't start in the middle of a tick.
* Compare with 0x10 for the wrap around case.
*/
do {
/*
* Wait for the 8254 to decrement by
* (APIC_TIME_COUNT + pit_ticks_adj) ticks
*/
do {
return (start_apic_tick - end_apic_tick);
}
/*
* Initialise the APIC timer on the local APIC of CPU 0 to the desired
* frequency. Note at this stage in the boot sequence, the boot processor
* is the only active processor.
* hertz value of 0 indicates a one-shot mode request. In this case
* the function returns the resolution (in nanoseconds) for the hardware
* timer interrupt. If one-shot mode capability is not available,
* the return value will be 0. apic_enable_oneshot is a global switch
* for disabling the functionality.
* A non-zero positive value for hertz indicates a periodic mode request.
* In this case the hardware will be programmed to generate clock interrupts
* at hertz frequency and returns the resolution of interrupts in
* nanosecond.
*/
static int
apic_clkinit(int hertz)
{
uint_t apic_ticks = 0;
int ret;
static int firsttime = 1;
if (firsttime) {
/* first time calibrate on CPU0 only */
/* total number of PIT ticks corresponding to apic_ticks */
/*
* Determine the number of nanoseconds per APIC clock tick
* and then determine how many APIC ticks to interrupt at the
* desired frequency
* apic_ticks / (pitticks / PIT_HZ) = apic_ticks_per_s
* (apic_ticks * PIT_HZ) / pitticks = apic_ticks_per_s
* apic_ticks_per_ns = (apic_ticks * PIT_HZ) / (pitticks * 10^9)
* pic_ticks_per_SFns =
* (SF * apic_ticks * PIT_HZ) / (pitticks * 10^9)
*/
/* the interval timer initial count is 32 bit max */
firsttime = 0;
}
if (hertz != 0) {
/* periodic */
}
if (hertz == 0) {
/* requested one_shot */
if (!tsc_gethrtime_enable || !apic_oneshot_enable)
return (0);
apic_oneshot = 1;
} else {
/* program the local APIC to interrupt at the given frequency */
apic_oneshot = 0;
}
return (ret);
}
/*
* apic_preshutdown:
* Called early in shutdown whilst we can still access filesystems to do
* things like loading modules which will be required to complete shutdown
* after filesystems are all unmounted.
*/
static void
{
APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n",
return;
}
}
static void
{
int i;
/* Send NMI to all CPUs except self to do per processor shutdown */
iflag = intr_clear();
#ifdef DEBUG
#else
if (apic_mode == LOCAL_APIC)
#endif /* DEBUG */
/* restore cmos shutdown byte before reboot */
if (apic_cmos_ssb_set) {
}
/* disable apic mode if imcr present */
if (apic_imcrp) {
}
/* remainder of function is for shutdown cases only */
if (cmd != A_SHUTDOWN)
return;
/*
* Switch system back into Legacy-Mode if using ACPI and
* not powering-off. Some BIOSes need to remain in ACPI-mode
* for power-off to succeed (Dell Dimension 4600)
* Do not disable ACPI while doing fastreboot
*/
(void) AcpiDisable();
if (fcn == AD_FASTREBOOT) {
}
/* remainder of function is for shutdown+poweroff case only */
if (fcn != AD_POWEROFF)
return;
switch (apic_poweroff_method) {
case APIC_POWEROFF_VIA_RTC:
/* select the extended NVRAM bank in the RTC */
/* for Predator must toggle the PAB bit */
/*
* clear power active bar, wakeup alarm and
* kickstart
*/
/* delay before next write */
drv_usecwait(1000);
/* for S40 the following would suffice */
/* power active bar control bit */
break;
restarts = 0;
if (++restarts == 3)
break;
attempts = 0;
do {
byte &= MISMIC_BUSY_MASK;
if (byte != 0) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_aspen_bmc;
++attempts;
}
} while (byte != 0);
byte |= 0x1;
i = 0;
i++) {
attempts = 0;
do {
byte &= MISMIC_BUSY_MASK;
if (byte != 0) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_aspen_bmc;
++attempts;
}
} while (byte != 0);
byte |= 0x1;
}
break;
restarts = 0;
if (++restarts == 3)
break;
attempts = 0;
do {
byte &= SMS_STATE_MASK;
if ((byte == SMS_READ_STATE) ||
(byte == SMS_WRITE_STATE)) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_sitka_bmc;
++attempts;
}
} while ((byte == SMS_READ_STATE) ||
(byte == SMS_WRITE_STATE));
i = 0;
i++) {
attempts = 0;
do {
byte &= SMS_IBF_MASK;
if (byte != 0) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_sitka_bmc;
++attempts;
}
} while (byte != 0);
}
break;
case APIC_POWEROFF_NONE:
/* If no APIC direct method, we will try using ACPI */
if (apic_enable_acpi) {
if (acpi_poweroff() == 1)
return;
} else
return;
break;
}
/*
* Wait a limited time here for power to go off.
* If the power does not go off, then there was a
* problem and we should continue to the halt which
* prints a message for the user to press a key to
* reboot.
*/
}
/*
* Try and disable all interrupts. We just assign interrupts to other
* processors based on policy. If any were bound by user request, we
* let them continue and return failure. We do not bother to check
* for cache affinity while rebinding.
*/
static int
{
iflag = intr_clear();
for (i = 0; i <= APIC_MAX_VECTOR; i++) {
/*
* CPU is busy -- it's the target of
* a pending reprogramming attempt
*/
return (PSM_FAILURE);
}
}
}
i = apic_min_device_irq;
for (; i <= apic_max_device_irq; i++) {
/*
* If there are bound interrupts on this cpu, then
* rebind them to other processors.
*/
apic_nproc));
hardbound = 1;
continue;
}
do {
if (bind_cpu >= apic_nproc) {
apic_next_bind_cpu = 1;
bind_cpu = 0;
}
}
}
}
if (hardbound) {
"due to user bound interrupts", cpun);
return (PSM_FAILURE);
}
else
return (PSM_SUCCESS);
}
/*
* Bind interrupts to the CPU's local APIC.
* Interrupts should not be bound to a CPU's local APIC until the CPU
* is ready to receive interrupts.
*/
static void
{
int i;
iflag = intr_clear();
i = apic_min_device_irq;
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
(void) apic_rebind_all(irq_ptr,
}
}
}
}
/*
* This function will reprogram the timer.
*
* When in oneshot mode the argument is the absolute time in future to
* generate the interrupt at.
*
* When in periodic mode, the argument is the interval at which the
* interrupts should be generated. There is no need to support the periodic
* mode timer change at this time.
*/
static void
{
/*
* We should be called from high PIL context (CBE_HIGH_PIL),
* so kpreempt is disabled.
*/
if (!apic_oneshot) {
/* time is the interval for periodic mode */
} else {
/* one shot mode */
if (delta <= 0) {
/*
* requested to generate an interrupt in the past
* generate an interrupt as soon as possible
*/
} else if (delta > apic_nsec_max) {
/*
* requested to generate an interrupt at a time
* further than what we are capable of. Set to max
* the hardware can handle
*/
ticks = APIC_MAXVAL;
#ifdef DEBUG
" %lld too far in future, current time"
#endif
} else
}
if (ticks < apic_min_timer_ticks)
}
/*
* This function will enable timer interrupts.
*/
static void
apic_timer_enable(void)
{
/*
* We should be Called from high PIL context (CBE_HIGH_PIL),
* so kpreempt is disabled.
*/
if (!apic_oneshot) {
} else {
/* one shot */
(apic_clkvect + APIC_BASE_VECT));
}
}
/*
* This function will disable timer interrupts.
*/
static void
apic_timer_disable(void)
{
/*
* We should be Called from high PIL context (CBE_HIGH_PIL),
* so kpreempt is disabled.
*/
}
/*
* Set timer far into the future and return timer
* current Count in nanoseconds.
*/
apic_timer_stop_count(void)
{
int enable_val, count_val;
/*
* Should be called with interrupts disabled.
*/
ASSERT(!interrupts_enabled());
return (ns_val);
}
/*
* Reprogram timer after Deep C-State.
*/
void
{
}
/*
* If this module needs a periodic handler for the interrupt distribution, it
* can be added here. The argument to the periodic handler is not currently
* used, but is reserved for future.
*/
static void
apic_post_cyclic_setup(void *arg)
{
/* cpu_lock is held */
/* set up a periodic handler for intr redistribution */
/*
* In peridoc mode intr redistribution processing is done in
* apic_intr_enter during clk intr processing
*/
if (!apic_oneshot)
return;
/*
* Register a periodical handler for the redistribution processing.
* On X86, CY_LOW_LEVEL is mapped to the level 2 interrupt, so
* DDI_IPL_2 should be passed to ddi_periodic_add() here.
*/
(void (*)(void *))apic_redistribute_compute, NULL,
}
static void
{
int i, j, max_busy;
if (++apic_nticks == apic_sample_factor_redistribution) {
/*
* Time to call apic_intr_redistribute().
* reset apic_nticks. This will cause max_busy
* to be calculated below and if it is more than
* apic_int_busy, we will do the whole thing
*/
apic_nticks = 0;
}
max_busy = 0;
for (i = 0; i < apic_nproc; i++) {
/*
* Check if curipl is non zero & if ISR is in
* progress
*/
if (((j = apic_cpus[i].aci_curipl) != 0) &&
int irq;
}
if (!apic_nticks &&
}
if (!apic_nticks) {
if (max_busy > apic_int_busy_mark) {
/*
* We could make the following check be
* skipped > 1 in which case, we get a
* redistribution at half the busy mark (due to
* double interval). Need to be able to collect
* more empirical data to decide if that is a
* good strategy. Punt for now.
*/
if (apic_skipped_redistribute) {
} else {
}
} else
}
}
}
/*
* The following functions are in the platform specific file so that they
* can be different functions depending on whether we are running on
* bare metal or a hypervisor.
*/
/*
* map an apic for memory-mapped access
*/
uint32_t *
{
/*LINTED: pointer cast may result in improper alignment */
}
uint32_t *
{
}
/*
* unmap an apic
*/
void
{
}
void
{
}
/*
* Check to make sure there are enough irq slots
*/
int
{
int i, avail;
avail = 0;
for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
if ((apic_irq_table[i] == NULL) ||
return (PSM_SUCCESS);
}
}
return (PSM_FAILURE);
}
/*
*/
int
int behavior)
{
int rcount, i;
"inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
if (count > 1) {
if (behavior == DDI_INTR_ALLOC_STRICT &&
apic_multi_msi_enable == 0)
return (0);
if (apic_multi_msi_enable == 0)
count = 1;
}
return (0);
/* if not ISP2, then round it down */
break;
}
if (start == 0) {
/* no vector available */
return (0);
}
/* not enough free irq slots available */
return (0);
}
for (i = 0; i < rcount; i++) {
(uchar_t)-1) {
/*
* shouldn't happen because of the
* apic_check_free_irqs() check earlier
*/
"apic_allocate_irq failed\n"));
return (i);
}
#ifdef DEBUG
"apic_vector_to_irq is not APIC_RESV_IRQ\n"));
#endif
irqptr->airq_share_id = 0;
if (i == 0) /* they all bound to the same cpu */
0xff, 0xff);
else
"dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
}
return (rcount);
}
/*
*/
int
int behavior)
{
int rcount, i;
behavior == DDI_INTR_ALLOC_STRICT)) {
rcount = 0;
goto out;
}
/* not enough free irq slots available */
rcount = 0;
goto out;
}
for (i = 0; i < rcount; i++) {
(uchar_t)-1) {
/*
* shouldn't happen because of the
* apic_check_free_irqs() check earlier
*/
"apic_allocate_irq failed\n"));
rcount = i;
goto out;
}
/*
* shouldn't happen because of the
* apic_navail_vector() call earlier
*/
"apic_allocate_vector failed\n"));
rcount = i;
goto out;
}
irqptr->airq_share_id = 0;
}
out:
return (rcount);
}
/*
* Allocate a free vector for irq at ipl. Takes care of merging of multiple
* IPLs into a single APIC level as well as stretching some IPLs onto multiple
* levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
* requests and allocated only when pri is set.
*/
{
#ifdef DEBUG
if (apic_restrict_vector) /* for testing shared interrupt logic */
#endif /* DEBUG */
if (pri == 0)
if (APIC_CHECK_RESERVE_VECTORS(i))
continue;
if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
return (i);
}
}
return (0);
}
/* Mark vector as not being used by any irq */
void
{
}
{
return (ioapic[APIC_IO_DATA]);
}
void
{
}
void
{
}
static processorid_t
apic_find_cpu(int flag)
{
processorid_t acid = 0;
int i;
/* Find the first CPU with the passed-in flag set */
for (i = 0; i < apic_nproc; i++) {
acid = i;
break;
}
}
return (acid);
}
/*
* Call rebind to do the actual programming.
* Must be called with interrupts disabled and apic_ioapic_lock held
* 'p' is polymorphic -- if this function is called to process a deferred
* reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
* the irq pointer is retrieved. If not doing deferred reprogramming,
* p is of the type 'apic_irq_t *'.
*
* apic_ioapic_lock must be held across this call, as it protects apic_rebind
* and it protects apic_find_cpu() from a race in which a CPU can be taken
* offline after a cpu is selected, but before apic_rebind is called to
* bind interrupts to it.
*/
int
{
int rv;
if (deferred) {
drep = (struct ioapic_reprogram_data *)p;
} else
irqptr = (apic_irq_t *)p;
if (rv) {
/*
* CPU is not up or interrupts are disabled. Fall back to
* the first available CPU
*/
drep);
}
return (rv);
}
{
return (vector);
}
char *
{
return (apic_psm_info.p_mach_idstring);
}
void
{
/*
* We don't need to do any magic if one of the following
* conditions is true :
* - Not being run under kernel debugger.
* - MP is not set.
* - Booted with one CPU only.
* - One CPU configured.
*
* We set apic_common_send_ipi() since kernel debuggers
* attempt to send IPIs to other slave CPUs during
* entry (exit) from (to) debugger.
*/
} else {
}
}
static void
apic_intrr_init(int apic_mode)
{
if (psm_vt_ops != NULL) {
== DDI_SUCCESS) {
}
}
}
/*ARGSUSED*/
static void
{
}
/*ARGSUSED*/
static void
{
}