apic.c revision a833a696f1726fd5d95ded0820612f465a2dad8d
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
* Copyright (c) 2013, Joyent, Inc. All rights reserved.
*/
/*
* To understand how the pcplusmp module interacts with the interrupt subsystem
*/
/*
* PSMI 1.1 extensions are supported only in 2.6 and later versions.
* PSMI 1.2 extensions are supported only in 2.7 and later versions.
* PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
* PSMI 1.5 extensions are supported in Solaris Nevada.
* PSMI 1.6 extensions are supported in Solaris Nevada.
* PSMI 1.7 extensions are supported in Solaris Nevada.
*/
#define PSMI_1_7
#include <sys/processor.h>
#include <sys/smp_impldefs.h>
#include <sys/psm_common.h>
#include <sys/ddi_impldefs.h>
#include <sys/x86_archext.h>
#include <sys/cpc_impl.h>
#include <sys/archsystm.h>
#include <sys/machsystm.h>
#include <sys/sysmacros.h>
#include <sys/rm_platter.h>
#include <sys/privregs.h>
#include <sys/pci_intr_lib.h>
#include <sys/dditypes.h>
#include <sys/apic_common.h>
#include <sys/apic_timer.h>
/*
* Local Function Prototypes
*/
static void apic_init_intr(void);
/*
* standard MP entries
*/
static int apic_probe(void);
static int apic_getclkirq(int ipl);
static void apic_init(void);
static void apic_picinit(void);
static int apic_post_cpu_start(void);
static void apic_setspl(int ipl);
static void x2apic_setspl(int ipl);
static void apic_post_cyclic_setup(void *arg);
/*
* The following vector assignments influence the value of ipltopri and
* vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
* idle to 0 and IPL 0 to 0xf to differentiate idle in case
* we care to do so in future. Note some IPLs which are rarely used
* will share the vector ranges and heavily used IPLs (5 and 6) have
* a wide range.
*
* This array is used to initialize apic_ipls[] (in apic_init()).
*
* IPL Vector range. as passed to intr_enter
* 0 none.
* 1,2,3 0x20-0x2f 0x0-0xf
* 4 0x30-0x3f 0x10-0x1f
* 5 0x40-0x5f 0x20-0x3f
* 6 0x60-0x7f 0x40-0x5f
* 7,8,9 0x80-0x8f 0x60-0x6f
* 10 0x90-0x9f 0x70-0x7f
* 11 0xa0-0xaf 0x80-0x8f
* ... ...
* 15 0xe0-0xef 0xc0-0xcf
* 15 0xf0-0xff 0xd0-0xdf
*/
3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
};
/*
* The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
* NOTE that this is vector as passed into intr_enter which is
* programmed vector - 0x20 (APIC_BASE_VECT)
*/
/* The taskpri to be programmed into apic to mask given ipl */
/*
* Correlation of the hardware vector to the IPL in use, initialized
* from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
* to the IPLs in apic_vectortoipl on some systems that share interrupt lines
* connected to errata-stricken IOAPICs
*/
/*
* Patchable global variables.
*/
int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
/*
* Local static data
*/
(int (*)(int))NULL, /* psm_softlvl_to_irq */
(void (*)(int))NULL, /* psm_set_softintr */
(void (*)(void))NULL, /* psm_hrtimeinit */
(void (*)(int, char *))NULL, /* psm_notify_error */
(void (*)(int))NULL, /* psm_notify_func */
apic_intr_ops, /* Advanced DDI Interrupt framework */
apic_state, /* save, restore apic state for S3 */
apic_cpu_ops, /* CPU control interface. */
};
static struct psm_info apic_psm_info = {
PSM_INFO_VER01_7, /* version */
PSM_OWN_EXCLUSIVE, /* ownership */
APIC_PCPLUSMP_NAME, /* machine name */
"pcplusmp v1.4 compatible",
};
static void *apic_hdlp;
/* to gather intr data and redistribute */
static void apic_redistribute_compute(void);
/*
* This is the loadable module wrapper
*/
int
_init(void)
{
if (apic_coarse_hrtime)
}
int
_fini(void)
{
}
int
{
}
static int
apic_probe(void)
{
/* check if apix is initialized */
if (apix_enable && apix_loaded())
return (PSM_FAILURE);
else
apix_enable = 0; /* continue using pcplusmp PSM */
}
static uchar_t
{
return (0);
}
void
apic_init(void)
{
int i;
int j = 1;
for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
/* get to highest vector at the same ipl */
continue;
for (; j <= apic_vectortoipl[i]; j++) {
apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
}
}
for (; j < MAXIPL + 1; j++)
/* fill up any empty ipltopri slots */
#if !defined(__amd64)
if (cpuid_have_cr8access(CPU))
apic_have_32bit_cr8 = 1;
#endif
}
static void
apic_init_intr(void)
{
if (apic_mode == LOCAL_APIC) {
/*
* We are running APIC in MMIO mode.
*/
if (apic_flat_model) {
} else {
}
AV_HIGH_ORDER >> cpun);
}
if (apic_directed_EOI_supported()) {
/*
* Setting the 12th bit in the Spurious Interrupt Vector
* Register suppresses broadcast EOIs generated by the local
* APIC. The suppression of broadcast EOIs happens only when
* interrupts are level-triggered.
*/
}
/* need to enable APIC before unmasking NMI */
/*
* Presence of an invalid vector with delivery mode AV_FIXED can
* cause an error interrupt, even if the entry is masked...so
* write a valid vector to LVT entries along with the mask bit
*/
/* All APICs have timer and LINT0/1 */
/*
* On integrated APICs, the number of LVT entries is
* 'Max LVT entry' + 1; on 82489DX's (non-integrated
* APICs), nlvt is "3" (LINT0, LINT1, and timer)
*/
nlvt = 3;
} else {
0xFF) + 1;
}
if (nlvt >= 5) {
/* Enable performance counter overflow interrupt */
if (apic_enable_cpcovf_intr) {
if (apic_cpcovf_vect == 0) {
int ipl = APIC_PCINT_IPL;
}
}
}
if (nlvt >= 6) {
/* Only mask TM intr if the BIOS apparently doesn't use it */
}
}
/* Enable error interrupt */
if (apic_errvect == 0) {
/*
* Not PSMI compliant, but we are going to merge
* with ON anyway
*/
}
}
/* Enable CMCI interrupt */
if (cmi_enable_cmci) {
if (cmci_cpu_setup_registered == 0) {
}
if (apic_cmci_vect == 0) {
int ipl = 0x2;
}
}
}
static void
apic_picinit(void)
{
int i, j;
/*
* Initialize and enable interrupt remapping before apic
* hardware initialization
*/
/*
* On UniSys Model 6520, the BIOS leaves vector 0x20 isr
* bit on without clearing it with EOI. Since softint
* uses vector 0x20 to interrupt itself, so softint will
* not work on this machine. In order to fix this problem
* a check is made to verify all the isr bits are clear.
* If not, EOIs are issued to clear the bits.
*/
for (i = 7; i >= 1; i--) {
if (isr != 0)
for (j = 0; ((j < 32) && (isr != 0)); j++)
if (isr & (1 << j)) {
APIC_EOI_REG, 0);
isr &= ~(1 << j);
}
}
/* set a flag so we know we have run apic_picinit() */
apic_picinit_called = 1;
picsetup(); /* initialise the 8259 */
/* add nmi handler - least priority nmi handler */
/*
* Check for directed-EOI capability in the local APIC.
*/
if (apic_directed_EOI_supported() == 1) {
}
/* enable apic mode if imcr present */
if (apic_imcrp) {
}
}
#ifdef DEBUG
void
apic_break(void)
{
}
#endif /* DEBUG */
/*
* platform_intr_enter
*
* Called at the beginning of the interrupt service routine to
* mask all level equal to and below the interrupt priority
* of the interrupting vector. An EOI should be given to
* the interrupt controller to enable other HW interrupts.
*
* Return -1 for spurious interrupts
*
*/
/*ARGSUSED*/
static int
{
int nipl;
int irq;
/*
* The real vector delivered is (*vectorp + 0x20), but our caller
* subtracts 0x20 from the vector before passing it to us.
* (That's why APIC_BASE_VECT is 0x20.)
*/
/* if interrupted by the clock, increment apic_nsec_since_boot */
if (vector == apic_clkvect) {
if (!apic_oneshot) {
/* NOTE: this is not MT aware */
}
/* We will avoid all the book keeping overhead for clock */
return (nipl);
}
return (APIC_INT_SPURIOUS);
}
/* Check if the vector we got is really what we need */
if (apic_revector_pending) {
/*
* Disable interrupts for the duration of
* the vector translation to prevent a self-race for
* the apic_revector_lock. This cannot be done
* in apic_xlate_vector because it is recursive and
* we want the vector translation to be atomic with
* respect to other (higher-priority) interrupts.
*/
iflag = intr_clear();
}
/*
* apic_level_intr could have been assimilated into the irq struct.
* but, having it as a character array is more efficient in terms of
* cache usage. So, we leave it as is.
*/
if (!apic_level_intr[irq]) {
}
#ifdef DEBUG
if (apic_break_on_cpu == psm_get_cpu_id())
apic_break();
#endif /* DEBUG */
return (nipl);
}
/*
* This macro is a common code used by MMIO local apic and X2APIC
* local apic.
*/
#define APIC_INTR_EXIT() \
{ \
if (apic_level_intr[irq]) \
/* ISR above current pri could not be in progress */ \
}
/*
* Any changes made to this function must also change X2APIC
* version of intr_exit.
*/
void
{
}
/*
* Same as apic_intr_exit() except it uses MSR rather than MMIO
* to access local apic registers.
*/
void
{
}
psm_intr_exit_fn(void)
{
if (apic_mode == LOCAL_X2APIC)
return (x2apic_intr_exit);
return (apic_intr_exit);
}
/*
* Mask all interrupts below or equal to the given IPL.
* Any changes made to this function must also change X2APIC
* version of setspl.
*/
static void
apic_setspl(int ipl)
{
/* interrupts at ipl above this cannot be in progress */
/*
* this is a patch fix for the ALR QSMP P5 machine, so that interrupts
* have enough time to come in before the priority is raised again
* during the idle() loop.
*/
if (apic_setspl_delay)
(void) apic_reg_ops->apic_get_pri();
}
/*
* X2APIC version of setspl.
* Mask all interrupts below or equal to the given IPL
*/
static void
x2apic_setspl(int ipl)
{
/* interrupts at ipl above this cannot be in progress */
}
/*ARGSUSED*/
static int
{
}
static int
{
}
static int
apic_post_cpu_start(void)
{
int cpun;
static int cpus_started = 1;
/* We know this CPU + BSP started successfully. */
cpus_started++;
/*
* On BSP we would have enabled X2APIC, if supported by processor,
* in acpi_probe(), but on AP we do it here.
*
* We enable X2APIC mode only if BSP is running in X2APIC & the
* local APIC mode of the current CPU is MMIO (xAPIC).
*/
apic_local_mode() == LOCAL_APIC) {
}
/*
* Switch back to x2apic IPI sending method for performance when target
* CPU has entered x2apic mode.
*/
if (apic_mode == LOCAL_X2APIC) {
}
/*
* since some systems don't enable the internal cache on the non-boot
* cpus, so we have to enable them here
*/
#ifdef DEBUG
#else
if (apic_mode == LOCAL_APIC)
#endif /* DEBUG */
/*
* We may be booting, or resuming from suspend; aci_status will
* be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
* APIC_CPU_ONLINE flag here rather than setting aci_status completely.
*/
cpun = psm_get_cpu_id();
return (PSM_SUCCESS);
}
/*
* type == -1 indicates it is an internal request. Do not change
* resv_vector for these requests
*/
static int
{
int irq;
if (type != -1) {
}
return (irq);
}
}
return (-1); /* shouldn't happen */
}
static int
apic_getclkirq(int ipl)
{
int irq;
return (-1);
/*
* Note the vector in apic_clkvect for per clock handling.
*/
apic_clkvect));
return (irq);
}
/*
* Try and disable all interrupts. We just assign interrupts to other
* processors based on policy. If any were bound by user request, we
* let them continue and return failure. We do not bother to check
* for cache affinity while rebinding.
*/
static int
{
iflag = intr_clear();
for (i = 0; i <= APIC_MAX_VECTOR; i++) {
/*
* CPU is busy -- it's the target of
* a pending reprogramming attempt
*/
return (PSM_FAILURE);
}
}
}
i = apic_min_device_irq;
for (; i <= apic_max_device_irq; i++) {
/*
* If there are bound interrupts on this cpu, then
* rebind them to other processors.
*/
hardbound = 1;
continue;
}
do {
bind_cpu =
}
}
}
if (hardbound) {
"due to user bound interrupts", cpun);
return (PSM_FAILURE);
}
else
return (PSM_SUCCESS);
}
/*
* Bind interrupts to the CPU's local APIC.
* Interrupts should not be bound to a CPU's local APIC until the CPU
* is ready to receive interrupts.
*/
static void
{
int i;
iflag = intr_clear();
i = apic_min_device_irq;
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
(void) apic_rebind_all(irq_ptr,
}
}
}
}
/*
* If this module needs a periodic handler for the interrupt distribution, it
* can be added here. The argument to the periodic handler is not currently
* used, but is reserved for future.
*/
static void
apic_post_cyclic_setup(void *arg)
{
/* cpu_lock is held */
/* set up a periodic handler for intr redistribution */
/*
* In peridoc mode intr redistribution processing is done in
* apic_intr_enter during clk intr processing
*/
if (!apic_oneshot)
return;
/*
* Register a periodical handler for the redistribution processing.
* Though we would generally prefer to use the DDI interface for
* periodic handler invocation, ddi_periodic_add(9F), we are
* unfortunately already holding cpu_lock, which ddi_periodic_add will
* attempt to take for us. Thus, we add our own cyclic directly:
*/
}
static void
{
int i, j, max_busy;
if (++apic_nticks == apic_sample_factor_redistribution) {
/*
* Time to call apic_intr_redistribute().
* reset apic_nticks. This will cause max_busy
* to be calculated below and if it is more than
* apic_int_busy, we will do the whole thing
*/
apic_nticks = 0;
}
max_busy = 0;
for (i = 0; i < apic_nproc; i++) {
if (!apic_cpu_in_range(i))
continue;
/*
* Check if curipl is non zero & if ISR is in
* progress
*/
if (((j = apic_cpus[i].aci_curipl) != 0) &&
int irq;
}
if (!apic_nticks &&
}
if (!apic_nticks) {
if (max_busy > apic_int_busy_mark) {
/*
* We could make the following check be
* skipped > 1 in which case, we get a
* redistribution at half the busy mark (due to
* double interval). Need to be able to collect
* more empirical data to decide if that is a
* good strategy. Punt for now.
*/
if (apic_skipped_redistribute) {
} else {
}
} else
}
}
}
/*
* The following functions are in the platform specific file so that they
* can be different functions depending on whether we are running on
* bare metal or a hypervisor.
*/
/*
* Check to make sure there are enough irq slots
*/
int
{
int i, avail;
avail = 0;
for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
if ((apic_irq_table[i] == NULL) ||
return (PSM_SUCCESS);
}
}
return (PSM_FAILURE);
}
/*
*/
int
int behavior)
{
int rcount, i;
"inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
if (count > 1) {
if (behavior == DDI_INTR_ALLOC_STRICT &&
apic_multi_msi_enable == 0)
return (0);
if (apic_multi_msi_enable == 0)
count = 1;
}
return (0);
/* if not ISP2, then round it down */
break;
}
if (start == 0) {
/* no vector available */
return (0);
}
/* not enough free irq slots available */
return (0);
}
for (i = 0; i < rcount; i++) {
(uchar_t)-1) {
/*
* shouldn't happen because of the
* apic_check_free_irqs() check earlier
*/
"apic_allocate_irq failed\n"));
return (i);
}
#ifdef DEBUG
"apic_vector_to_irq is not APIC_RESV_IRQ\n"));
#endif
irqptr->airq_share_id = 0;
if (i == 0) /* they all bound to the same cpu */
0xff, 0xff);
else
"dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
}
return (rcount);
}
/*
*/
int
int behavior)
{
int rcount, i;
behavior == DDI_INTR_ALLOC_STRICT)) {
rcount = 0;
goto out;
}
/* not enough free irq slots available */
rcount = 0;
goto out;
}
for (i = 0; i < rcount; i++) {
(uchar_t)-1) {
/*
* shouldn't happen because of the
* apic_check_free_irqs() check earlier
*/
"apic_allocate_irq failed\n"));
rcount = i;
goto out;
}
/*
* shouldn't happen because of the
* apic_navail_vector() call earlier
*/
"apic_allocate_vector failed\n"));
rcount = i;
goto out;
}
irqptr->airq_share_id = 0;
}
out:
return (rcount);
}
/*
* Allocate a free vector for irq at ipl. Takes care of merging of multiple
* IPLs into a single APIC level as well as stretching some IPLs onto multiple
* levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
* requests and allocated only when pri is set.
*/
{
#ifdef DEBUG
if (apic_restrict_vector) /* for testing shared interrupt logic */
#endif /* DEBUG */
if (pri == 0)
if (APIC_CHECK_RESERVE_VECTORS(i))
continue;
if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
return (i);
}
}
return (0);
}
/* Mark vector as not being used by any irq */
void
{
}
/*
* Call rebind to do the actual programming.
* Must be called with interrupts disabled and apic_ioapic_lock held
* 'p' is polymorphic -- if this function is called to process a deferred
* reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
* the irq pointer is retrieved. If not doing deferred reprogramming,
* p is of the type 'apic_irq_t *'.
*
* apic_ioapic_lock must be held across this call, as it protects apic_rebind
* and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
* taken offline after a cpu is selected, but before apic_rebind is called to
* bind interrupts to it.
*/
int
{
int rv;
if (deferred) {
drep = (struct ioapic_reprogram_data *)p;
} else
irqptr = (apic_irq_t *)p;
if (rv) {
/*
* CPU is not up or interrupts are disabled. Fall back to
* the first available CPU
*/
drep);
}
return (rv);
}
{
return (vector);
}
char *
apic_get_apic_type(void)
{
return (apic_psm_info.p_mach_idstring);
}
void
x2apic_update_psm(void)
{
}