apic.c revision 70025d765b044c6d8594bb965a2247a61e991a99
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PSMI 1.1 extensions are supported only in 2.6 and later versions.
* PSMI 1.2 extensions are supported only in 2.7 and later versions.
* PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
* PSMI 1.5 extensions are supported in Solaris Nevada.
*/
#define PSMI_1_5
#include <sys/processor.h>
#include <sys/smp_impldefs.h>
#include <sys/psm_common.h>
#include "apic.h"
#include <sys/ddi_impldefs.h>
#include <sys/x86_archext.h>
#include <sys/cpc_impl.h>
#include <sys/archsystm.h>
#include <sys/machsystm.h>
#include <sys/rm_platter.h>
#include <sys/privregs.h>
#include <sys/pci_intr_lib.h>
/*
* Local Function Prototypes
*/
static void apic_init_intr();
static void apic_ret();
static int apic_handle_defconf();
static int get_apic_cmd1();
static int get_apic_pri();
static int apic_find_bus_type(char *bus);
static int apic_find_bus(int busid);
static int apic_find_bus_id(int bustype);
int apic_allocate_irq(int irq);
static void apic_xlate_vector_free_timeout_handler(void *arg);
static void apic_reprogram_timeout_handler(void *arg);
int type);
int when);
static void apic_intr_redistribute();
static void apic_cleanup_busy();
/* ACPI support routines */
static int acpi_probe(void);
/*
* standard MP entries
*/
static int apic_probe();
static int apic_clkinit();
static int apic_getclkirq(int ipl);
static hrtime_t apic_gettime();
static hrtime_t apic_gethrtime();
static void apic_init();
static void apic_picinit(void);
static int apic_post_cpu_start(void);
static void apic_set_softintr(int softintr);
static int apic_softlvl_to_irq(int ipl);
static void apic_setspl(int ipl);
static void apic_timer_enable(void);
static void apic_timer_disable(void);
static void apic_post_cyclic_setup(void *arg);
psm_intr_op_t, int *);
static int apic_oneshot = 0;
/*
* These variables are frequently accessed in apic_intr_enter(),
* apic_intr_exit and apic_setspl, so group them together
*/
int apic_clkvect;
/* ACPI SCI interrupt configuration; -1 if SCI not used */
int apic_sci_vect = -1;
/* vector at which error interrupts come in */
int apic_errvect;
int apic_enable_error_intr = 1;
int apic_error_display_delay = 100;
/* vector at which performance counter overflow interrupts come in */
int apic_cpcovf_vect;
int apic_enable_cpcovf_intr = 1;
/* Max wait time (in microsecs) for flags to clear in an RDT entry. */
static int apic_max_usecs_clear_pending = 1000;
/* Amt of usecs to wait before checking if RDT flags have reset. */
#define APIC_USECS_PER_WAIT_INTERVAL 100
/* Maximum number of times to retry reprogramming via the timeout */
#define APIC_REPROGRAM_MAX_TIMEOUTS 10
/* timeout delay for IOAPIC delayed reprogramming */
/* Parameter to apic_rebind(): Should reprogramming be done now or later? */
#define DEFERRED 1
#define IMMEDIATE 0
/*
*/
/*
* The following vector assignments influence the value of ipltopri and
* vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
* idle to 0 and IPL 0 to 0x10 to differentiate idle in case
* we care to do so in future. Note some IPLs which are rarely used
* will share the vector ranges and heavily used IPLs (5 and 6) have
* a wide range.
* IPL Vector range. as passed to intr_enter
* 0 none.
* 1,2,3 0x20-0x2f 0x0-0xf
* 4 0x30-0x3f 0x10-0x1f
* 5 0x40-0x5f 0x20-0x3f
* 6 0x60-0x7f 0x40-0x5f
* 7,8,9 0x80-0x8f 0x60-0x6f
* 10 0x90-0x9f 0x70-0x7f
* 11 0xa0-0xaf 0x80-0x8f
* ... ...
* 16 0xf0-0xff 0xd0-0xdf
*/
3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 16
};
/*
* The ipl of an ISR at vector X is apic_vectortoipl[X<<4]
* NOTE that this is vector as passed into intr_enter which is
* programmed vector - 0x20 (APIC_BASE_VECT)
*/
/* The taskpri to be programmed into apic to mask given ipl */
#if defined(__amd64)
#endif
/*
* Patchable global variables.
*/
int apic_forceload = 0;
#define INTR_ROUND_ROBIN_WITH_AFFINITY 0
#define INTR_ROUND_ROBIN 1
#define INTR_LOWEST_PRIORITY 2
/* start with cpu 1 */
/* 1 - use gettime() for performance */
int apic_flat_model = 0; /* 0 - clustered. 1 - flat */
int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
int apic_panic_on_nmi = 0;
int apic_panic_on_apic_error = 0;
int apic_verbose = 0;
/* Flag definitions for apic_verbose */
#define APIC_VERBOSE_IOAPIC_FLAG 0x00000001
#define APIC_VERBOSE_IRQ_FLAG 0x00000002
#define APIC_VERBOSE_POWEROFF_FLAG 0x00000004
#define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008
#define APIC_VERBOSE_IOAPIC(fmt) \
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \
#define APIC_VERBOSE_IRQ(fmt) \
if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \
#define APIC_VERBOSE_POWEROFF(fmt) \
if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \
/* Now the ones for Dynamic Interrupt distribution */
int apic_enable_dynamic_migration = 1;
/*
* If enabled, the distribution works as follows:
* On every interrupt entry, the current ipl for the CPU is set in cpu_info
* and the irq corresponding to the ipl is also set in the aci_current array.
* interrupt exit and setspl (due to soft interrupts) will cause the current
* ipl to be be changed. This is cache friendly as these frequently used
* paths write into a per cpu structure.
*
* Sampling is done by checking the structures for all CPUs and incrementing
* the busy field of the irq (if any) executing on each CPU and the busy field
* of the corresponding CPU.
* In periodic mode this is done on every clock interrupt.
* In one-shot mode, this is done thru a cyclic with an interval of
* apic_redistribute_sample_interval (default 10 milli sec).
*
* Every apic_sample_factor_redistribution times we sample, we do computations
* to decide which interrupt needs to be migrated (see comments
* before apic_intr_redistribute().
*/
/*
* Following 3 variables start as % and can be patched or set using an
* API to be defined in future. They will be scaled to
* sample_factor_redistribution which is in turn set to hertz+1 (in periodic
* mode), or 101 in one-shot mode to stagger it away from one sec processing
*/
int apic_int_busy_mark = 60;
int apic_int_free_mark = 20;
int apic_diff_for_redistribution = 10;
/* sampling interval for interrupt redistribution for dynamic migration */
/*
* number of times we sample before deciding to redistribute interrupts
* for dynamic migration
*/
int apic_sample_factor_redistribution = 101;
/* timeout for xlate_vector, mark_vector */
int apic_redist_cpu_skip = 0;
int apic_num_imbalance = 0;
int apic_num_rebind = 0;
int apic_nproc = 0;
int apic_defconf = 0;
int apic_irq_translate = 0;
int apic_spec_rev = 0;
int apic_imcrp = 0;
int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
/*
* For interrupt link devices, if apic_unconditional_srs is set, an irq resource
* will be assigned (via _SRS). If it is not set, use the current
* irq setting (via _CRS), but only if that irq is in the set of possible
* irqs (returned by _PRS) for the device.
*/
int apic_unconditional_srs = 1;
/*
* For interrupt link devices, if apic_prefer_crs is set when we are
* assigning an IRQ resource to a device, prefer the current IRQ setting
* over other possible irq settings under same conditions.
*/
int apic_prefer_crs = 1;
/* minimum number of timer ticks to program to */
int apic_min_timer_ticks = 1;
/*
* Local static data
*/
(void (*)(void))NULL, /* psm_hrtimeinit */
(void (*)(int, char *))NULL, /* psm_notify_error */
(void (*)(int))NULL, /* psm_notify_func */
apic_intr_ops /* Advanced DDI Interrupt framework */
};
static struct psm_info apic_psm_info = {
PSM_INFO_VER01_5, /* version */
PSM_OWN_EXCLUSIVE, /* ownership */
"pcplusmp", /* machine name */
"pcplusmp v1.4 compatible %I%",
};
static void *apic_hdlp;
#ifdef DEBUG
#define DENT 0x0001
int apic_debug = 0;
/*
* set apic_restrict_vector to the # of vectors we want to allow per range
* useful in testing shared interrupt logic by setting it to 2 or 3
*/
int apic_restrict_vector = 0;
#define APIC_DEBUG_MSGBUFSIZE 2048
int apic_debug_msgbufindex = 0;
/*
* Put "int" info into debug buffer. No MP consistency, but light weight.
* Good enough for most debugging.
*/
#define APIC_DEBUG_BUF_PUT(x) \
apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \
#endif /* DEBUG */
static uint_t apic_cpumask = 0;
/* Flag to indicate that we need to shut down all processors */
static uint_t apic_shutdown_processors;
uint_t apic_nsec_per_intr = 0;
/*
* apic_let_idle_redistribute can have the following values:
* 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
* apic_redistribute_lock prevents multiple idle cpus from redistributing
*/
int apic_num_idle_redistributions = 0;
static int apic_let_idle_redistribute = 0;
static uint_t apic_nticks = 0;
static uint_t apic_skipped_redistribute = 0;
/* to gather intr data and redistribute */
static void apic_redistribute_compute(void);
static uint_t last_count_read = 0;
static lock_t apic_gethrtime_lock;
volatile int apic_hrtime_stamp = 0;
volatile hrtime_t apic_nsec_since_boot = 0;
static hrtime_t apic_nsec_max;
static hrtime_t apic_last_hrtime = 0;
int apic_hrtime_error = 0;
int apic_remote_hrterr = 0;
int apic_num_nmis = 0;
int apic_apic_error = 0;
int apic_num_apic_errors = 0;
int apic_num_cksum_errors = 0;
/*
* First available slot to be used as IRQ index into the apic_irq_table
* for those interrupts (like MSI/X) that don't have a physical IRQ.
*/
/*
* apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
* and bound elements of cpus_info and the temp_cpu element of irq_struct
*/
/*
* apic_ioapic_reprogram_lock prevents a CPU from exiting
* apic_intr_exit before IOAPIC reprogramming information
* is collected.
*/
static lock_t apic_ioapic_reprogram_lock;
static int apic_io_max = 0; /* no. of i/o apics enabled */
static struct apic_io_intr *apic_io_intrp = 0;
static int apic_error = 0;
/* values which apic_error can take. Not catastrophic, but may help debug */
#define APIC_ERR_BOOT_EOI 0x1
#define APIC_ERR_GET_IPIVECT_FAIL 0x2
#define APIC_ERR_INVALID_INDEX 0x4
#define APIC_ERR_MARK_VECTOR_FAIL 0x8
#define APIC_ERR_APIC_ERROR 0x40000000
#define APIC_ERR_NMI 0x80000000
static int apic_cmos_ssb_set = 0;
static uint32_t eisa_level_intr_mask = 0;
/* At least MSB will be set if EISA bus */
static int apic_pci_bus_total = 0;
static uchar_t apic_single_pci_busid = 0;
/*
* airq_mutex protects additions to the apic_irq_table - the first
* pointer and any airq_nexts off of that one. It also protects
* apic_max_device_irq & apic_min_device_irq. It also guarantees
* that share_id is unique as new ids are generated only when new
* irq_t structs are linked in. Once linked in the structs are never
* deleted. temp_cpu & mps_intr_index field indicate if it is programmed
* or allocated. Note that there is a slight gap between allocating in
* apic_introp_xlate and programming in addspl.
*/
int apic_max_device_irq = 0;
/* use to make sure only one cpu handles the nmi */
static lock_t apic_nmi_lock;
/* use to make sure only one cpu handles the error interrupt */
static lock_t apic_error_lock;
/*
* Following declarations are for revectoring; used when ISRs at different
* IPLs share an irq.
*/
static lock_t apic_revector_lock;
static int apic_revector_pending = 0;
static uchar_t *apic_oldvec_to_newvec;
static uchar_t *apic_newvec_to_oldvec;
/* Ensures that the IOAPIC-reprogramming timeout is not reentrant */
static kmutex_t apic_reprogram_timeout_mutex;
static struct ioapic_reprogram_data {
int valid; /* This entry is valid */
int bindcpu; /* The CPU to which the int will be bound */
unsigned timeouts; /* # times the reprogram timeout was called */
/*
* APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. apic_reprogram_info
* is indexed by IRQ number, NOT by vector number.
*/
/*
* The following added to identify a software poweroff method if available.
*/
static struct {
int poweroff_method;
} apic_mps_ids[] = {
};
static struct {
} aspen_bmc[] = {
};
static struct {
int port;
} sitka_bmc[] = {
};
/* Patchable global variables. */
int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */
int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
/*
* ACPI definitions
*/
/* _PIC method arguments */
#define ACPI_PIC_MODE 0
#define ACPI_APIC_MODE 1
/* APIC error flags we care about */
#define APIC_SEND_CS_ERROR 0x01
#define APIC_RECV_CS_ERROR 0x02
/*
* ACPI variables
*/
/* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
static int apic_enable_acpi = 0;
/* ACPI Multiple APIC Description Table ptr */
/* ACPI Interrupt Source Override Structure ptr */
static int acpi_iso_cnt = 0;
/* ACPI Non-maskable Interrupt Sources ptr */
static int acpi_nmi_scnt = 0;
static int acpi_nmi_ccnt = 0;
/*
* extern declarations
*/
extern int intr_clear(void);
extern void intr_restore(uint_t);
#if defined(__amd64)
extern int intpri_use_cr8;
#endif /* __amd64 */
extern int apic_pci_msi_enable_vector(dev_info_t *, int, int,
int, int, int);
/*
* This is the loadable module wrapper
*/
int
_init(void)
{
if (apic_coarse_hrtime)
}
int
_fini(void)
{
}
int
{
}
/*
* Auto-configuration routines
*/
/*
* Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
* May work with 1.1 - but not guaranteed.
* According to the MP Spec, the MP floating pointer structure
* will be searched in the order described below:
* 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
* 2. Within the last kilobyte of system base memory
* 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
* Once we find the right signature with proper checksum, we call
* either handle_defconf or parse_mpct to get all info necessary for
* subsequent operations.
*/
static int
{
struct apic_mpfps_hdr *fpsp;
struct apic_mp_cnf_hdr *hdrp;
int acpi_user_options;
if (apic_forceload < 0)
return (retval);
/* Allow override for MADT-only mode */
"acpi-user-options", 0);
/* Allow apic_use_acpi to override MADT-only mode */
if (!apic_use_acpi)
retval = acpi_probe();
/*
* mapin the bios data area 40:0
* 40:13h - two-byte location reports the base memory size
* 40:0Eh - two-byte location for the exact starting address of
* the EBDA segment for EISA
*/
if (!biosdatap)
return (retval);
/*LINTED: pointer cast may result in improper alignment */
/* check the 1k of EBDA */
if (ebda_seg) {
if (fptr) {
if (!(fpsp =
}
}
/* If not in EBDA, check the last k of system base memory */
if (!fpsp) {
/*LINTED: pointer cast may result in improper alignment */
if (base_mem_size > 512)
else
/* if ebda == last k of base mem, skip to check BIOS ROM */
if (base_mem_end != ebda_start) {
if (fptr) {
}
}
}
/* If still cannot find it, check the BIOS ROM space */
if (!fpsp) {
if (fptr) {
if (!(fpsp =
return (retval);
}
}
}
return (retval);
}
return (retval);
}
/* check IMCR is present or not */
/* check default configuration (dual CPUs) */
return (apic_handle_defconf());
}
/* MP Configuration Table */
/*
* Map in enough memory for the MP Configuration Table Header.
* Use this table to read the total length of the BIOS data and
* map in all the info
*/
/*LINTED: pointer cast may result in improper alignment */
sizeof (struct apic_mp_cnf_hdr), PROT_READ);
if (!hdrp)
return (retval);
/* check mp configuration table signature PCMP */
return (retval);
}
/* This is an ACPI machine No need for further checks */
return (retval);
}
/*
* Map in the entries for this machine, ie. Processor
* Entry Tables, Bus Entry Tables, etc.
* They are in fixed order following one another
*/
if (!mpct)
return (retval);
goto apic_fail1;
/*LINTED: pointer cast may result in improper alignment */
/*LINTED: pointer cast may result in improper alignment */
if (!apicadr)
goto apic_fail1;
/* Parse all information in the tables */
return (PSM_SUCCESS);
for (i = 0; i < apic_io_max; i++)
if (apic_cpus)
if (apicadr)
return (retval);
}
static void
{
int i;
for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
i++) {
break;
}
}
if (apic_debug_mps_id != 0) {
"Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
hdrp->mpcnf_oem_str[0],
hdrp->mpcnf_prod_str[0],
}
}
static int
acpi_probe(void)
{
int acpi_verboseflags = 0;
int sci;
if (!apic_use_acpi)
return (PSM_FAILURE);
return (PSM_FAILURE);
if (!apicadr)
return (PSM_FAILURE);
apic_io_max = 0;
madt_seen = sizeof (*acpi_mapic_dtp);
case APIC_PROCESSOR:
if (mpa->ProcessorEnabled) {
else if (apic_nproc < NCPU) {
index++;
apic_nproc++;
} else
"maximum no. of CPUs (= %d)", NCPU);
}
break;
case APIC_IO:
if (apic_io_max < MAX_IO_APIC) {
(int32_t *)psm_map_phys(
if (!ioapic)
goto cleanup;
apic_io_max++;
}
break;
case APIC_XRUPT_OVERRIDE:
acpi_iso_cnt++;
break;
case APIC_NMI:
/* UNIMPLEMENTED */
if (acpi_nmi_sp == NULL)
acpi_nmi_sp = mns;
mns->TriggerMode);
break;
case APIC_LOCAL_NMI:
/* UNIMPLEMENTED */
if (acpi_nmi_cp == NULL)
acpi_nmi_cp = mlan;
break;
case APIC_ADDRESS_OVERRIDE:
/* UNIMPLEMENTED */
break;
case APIC_IO_SAPIC:
/* UNIMPLEMENTED */
break;
case APIC_XRUPT_SOURCE:
/* UNIMPLEMENTED */
"!apic: irq source: %d %d %d %d %d %d %d\n",
mis->IoSapicVector);
break;
case APIC_RESERVED:
default:
goto cleanup;
}
/* advance to next entry */
}
KM_NOSLEEP)) == NULL)
goto cleanup;
/*
* ACPI doesn't provide the local apic ver, get it directly from the
* local apic
*/
for (i = 0; i < apic_nproc; i++) {
}
for (i = 0; i < apic_io_max; i++) {
/*
* need to check Sitka on the following acpi problem
* On the Sitka, the ioapic's apic_id field isn't reporting
* the actual io apic id. We have reported this problem
* to Intel. Until they fix the problem, we will get the
* actual id directly from the ioapic.
*/
if (hid != apic_io_id[i]) {
if (apic_io_id[i] == 0)
apic_io_id[i] = hid;
else { /* set ioapic id to whatever reported by ACPI */
}
}
if (apic_first_avail_irq <= apic_io_vectend[i])
}
/*
* Process SCI configuration here
* An error may be returned here if
* acpi-user-options specifies legacy mode
* (no SCI, no ACPI mode)
*/
sci = -1;
/*
* Now call acpi_init() to generate namespaces
* If this fails, we don't attempt to use ACPI
* even if we were able to get a MADT above
*/
if (acpica_init() != AE_OK)
goto cleanup;
/*
* Squirrel away the SCI and flags for later on
* in apic_picinit() when we're ready
*/
apic_sci_vect = sci;
goto cleanup;
/* Enable ACPI APIC interrupt routing */
apic_enable_acpi = 1;
if (apic_use_acpi_madt_only) {
}
return (PSM_SUCCESS);
}
/* if setting APIC mode failed above, we fall through to cleanup */
}
apic_nproc = 0;
for (i = 0; i < apic_io_max; i++) {
}
apic_io_max = 0;
acpi_iso_cnt = 0;
acpi_nmi_sp = NULL;
acpi_nmi_scnt = 0;
acpi_nmi_cp = NULL;
acpi_nmi_ccnt = 0;
return (PSM_FAILURE);
}
/*
* Handle default configuration. Fill in reqd global variables & tables
* Fill all details as MP table does not give any more info
*/
static int
{
/*LINTED: pointer cast may result in improper alignment */
/*LINTED: pointer cast may result in improper alignment */
apic_cpus = (apic_cpus_info_t *)
goto apic_handle_defconf_fail;
apic_cpumask = 3;
apic_nproc = 2;
/*
* According to the PC+MP spec 1.1, the local ids
* for the default configuration has to be 0 or 1
*/
else if (apic_cpus[0].aci_local_id == 0)
else
goto apic_handle_defconf_fail;
apic_io_id[0] = 2;
apic_io_max = 1;
if (apic_defconf >= 5) {
} else {
apic_io_ver[0] = 0;
}
return (PSM_SUCCESS);
if (apic_cpus)
if (apicadr)
if (apicioadr[0])
return (PSM_FAILURE);
}
/* Parse the entries in MP configuration table and collect info that we need */
static int
{
struct apic_procent *procp;
struct apic_io_entry *ioapicp;
struct apic_io_intr *intrp;
int id;
/*LINTED: pointer cast may result in improper alignment */
/* No need to count cpu entries if we won't use them */
if (!bypass_cpus_and_ioapics) {
/* Find max # of CPUS and allocate structure accordingly */
apic_nproc = 0;
apic_nproc++;
}
procp++;
}
if (apic_nproc > NCPU)
"maximum no. of CPUs (= %d)", NCPU);
return (PSM_FAILURE);
}
/*LINTED: pointer cast may result in improper alignment */
/*
* start with index 1 as 0 needs to be filled in with Boot CPU, but
* if we're bypassing this information, it has already been filled
* in by acpi_probe(), so don't overwrite it.
*/
if (!bypass_cpus_and_ioapics)
apic_nproc = 1;
/* check whether the cpu exists or not */
if (!bypass_cpus_and_ioapics &&
if (apic_cpus[0].aci_local_id !=
return (PSM_FAILURE);
}
apic_cpus[0].aci_local_ver =
} else {
apic_nproc++;
}
}
procp++;
}
if (!bypass_cpus_and_ioapics) {
/* convert the number of processors into a cpumask */
}
/*
* Save start of bus entries for later use.
* Get EISA level cntrl if EISA bus is present.
* Also get the CPI bus id for single CPI bus case
*/
/*
* apic_single_pci_busid will be used only if
* apic_pic_bus_total is equal to 1
*/
}
busp++;
}
if (!bypass_cpus_and_ioapics)
apic_io_max = 0;
do {
/*LINTED: pointer cast may result in improper alignment */
(int32_t *)psm_map_phys(
if (!apicioadr[apic_io_max])
return (PSM_FAILURE);
if (apic_io_id[apic_io_max] == 0)
else {
/*
* set ioapic id to whatever
* reported by MPS
*
* may not need to set index
* again ???
* take it out and try
*/
apic_io_id[apic_io_max]) <<
24;
}
}
apic_io_max++;
}
}
ioapicp++;
apic_irq_translate = 1;
break;
}
intrp++;
}
return (PSM_SUCCESS);
}
static struct apic_mpfps_hdr *
{
int i;
/* Look for the pattern "_MP_" */
for (i = 0; i < len; i += 16) {
if ((*(cptr+i) == '_') &&
/*LINTED: pointer cast may result in improper alignment */
return ((struct apic_mpfps_hdr *)(cptr + i));
}
return (NULL);
}
static int
{
int i;
cksum = 0;
for (i = 0; i < len; i++)
return ((int)cksum);
}
/*
* Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable
* are also set to NULL. vector->irq is set to a value which cannot map
* to a real irq to show that it is free.
*/
void
{
int i;
int *iptr;
int j = 1;
for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
/* get to highest vector at the same ipl */
continue;
for (; j <= apic_vectortoipl[i]; j++) {
apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
}
}
for (; j < MAXIPL + 1; j++)
/* fill up any empty ipltopri slots */
/* cpu 0 is always up */
iptr = (int *)&apic_irq_table[0];
for (i = 0; i <= APIC_MAX_VECTOR; i++) {
apic_level_intr[i] = 0;
apic_reprogram_info[i].valid = 0;
apic_reprogram_info[i].bindcpu = 0;
apic_reprogram_info[i].timeouts = 0;
}
/*
* Allocate a dummy irq table entry for the reserved entry.
* This takes care of the race between removing an irq and
* clock detecting a CPU in that irq during interrupt load
* sampling.
*/
#if defined(__amd64)
/*
* Make cpu-specific interrupt info point to cr8pri vector
*/
for (i = 0; i <= MAXIPL; i++)
intpri_use_cr8 = 1;
#endif /* __amd64 */
}
/*
* handler for APIC Error interrupt. Just print a warning and continue
*/
static int
{
uint_t i;
/*
* We need to write before read as per 7.4.17 of system prog manual.
* We do both and or the results to be safe
*/
apicadr[APIC_ERROR_STATUS] = 0;
/*
* Clear the APIC error status (do this on all cpus that enter here)
* (two writes are required due to the semantics of accessing the
* error status register.)
*/
apicadr[APIC_ERROR_STATUS] = 0;
apicadr[APIC_ERROR_STATUS] = 0;
/*
* Prevent more than 1 CPU from handling error interrupt causing
* double printing (interleave of characters from multiple
* CPU's when using prom_printf)
*/
if (lock_try(&apic_error_lock) == 0)
if (error) {
#if DEBUG
if (apic_debug)
debug_enter("pcplusmp: APIC Error interrupt received");
#endif /* DEBUG */
"APIC Error interrupt on CPU %d. Status = %x\n",
psm_get_cpu_id(), error);
else {
if ((error & ~APIC_CS_ERRORS) == 0) {
/* cksum error only */
apic_apic_error |= error;
} else {
/*
* prom_printf is the best shot we have of
* something which is problem free from
*/
prom_printf("APIC Error interrupt on CPU %d. "
"Status 0 = %x, Status 1 = %x\n",
apic_apic_error |= error;
for (i = 0; i < apic_error_display_delay; i++) {
tenmicrosec();
}
/*
* provide more delay next time limited to
* roughly 1 clock tick time
*/
if (apic_error_display_delay < 500)
apic_error_display_delay *= 2;
}
}
return (DDI_INTR_CLAIMED);
} else {
return (DDI_INTR_UNCLAIMED);
}
/* NOTREACHED */
}
/*
* Turn off the mask bit in the performance counter Local Vector Table entry.
*/
static void
apic_cpcovf_mask_clear(void)
{
}
static void
{
#if defined(__amd64)
#else
#endif
if (apic_flat_model)
else
/* need to enable APIC before unmasking NMI */
return;
/* Enable performance counter overflow interrupt */
if (apic_enable_cpcovf_intr) {
if (apic_cpcovf_vect == 0) {
int ipl = APIC_PCINT_IPL;
}
}
/* Enable error interrupt */
if (apic_enable_error_intr) {
if (apic_errvect == 0) {
/*
* Not PSMI compliant, but we are going to merge
* with ON anyway
*/
}
apicadr[APIC_ERROR_STATUS] = 0;
apicadr[APIC_ERROR_STATUS] = 0;
}
}
static void
{
}
static void
apic_picinit(void)
{
int i, j;
/*
* On UniSys Model 6520, the BIOS leaves vector 0x20 isr
* bit on without clearing it with EOI. Since softint
* uses vector 0x20 to interrupt itself, so softint will
* not work on this machine. In order to fix this problem
* a check is made to verify all the isr bits are clear.
* If not, EOIs are issued to clear the bits.
*/
for (i = 7; i >= 1; i--) {
for (j = 0; ((j < 32) && (isr != 0)); j++)
if (isr & (1 << j)) {
apicadr[APIC_EOI_REG] = 0;
isr &= ~(1 << j);
}
}
/* set a flag so we know we have run apic_picinit() */
apic_flag = 1;
picsetup(); /* initialise the 8259 */
/* add nmi handler - least priority nmi handler */
/* enable apic mode if imcr present */
if (apic_imcrp) {
}
/* mask interrupt vectors */
for (j = 0; j < apic_io_max; j++) {
int intin_max;
/* Bits 23-16 define the maximum redirection entries */
for (i = 0; i < intin_max; i++) {
}
}
/*
*/
if (apic_sci_vect > 0) {
/*
* acpica has already done add_avintr(); we just
* to finish the job by mimicing translate_irq()
*
* Fake up an intrspec and setup the tables
*/
return;
}
/* Program I/O APIC */
}
}
static void
{
int loop_count;
apic_cmos_ssb_set = 1;
/*
* Interrupts on BSP cpu will be disabled during these startup
* steps in order to avoid unwanted side effects from
* executing interrupt handlers on a problematic BIOS.
*/
iflag = intr_clear();
while (get_apic_cmd1() & AV_PENDING)
apic_ret();
/* for integrated - make sure there is one INIT IPI in buffer */
/* for external - it will wake up the cpu */
/* If only 1 CPU is installed, PENDING bit will not go low */
if (get_apic_cmd1() & AV_PENDING)
apic_ret();
else
break;
/* integrated apic */
/* to offset the INIT IPI queue up in the buffer */
}
}
#ifdef DEBUG
int apic_break_on_cpu = 9;
int apic_stretch_interrupts = 0;
void
{
}
#endif /* DEBUG */
/*
* platform_intr_enter
*
* Called at the beginning of the interrupt service routine to
* mask all level equal to and below the interrupt priority
* of the interrupting vector. An EOI should be given to
* the interrupt controller to enable other HW interrupts.
*
* Return -1 for spurious interrupts
*
*/
/*ARGSUSED*/
static int
{
int nipl;
/*
* The real vector programmed in APIC is *vectorp + 0x20
* But, cmnint code subtracts 0x20 before pushing it.
* Hence APIC_BASE_VECT is 0x20.
*/
/* if interrupted by the clock, increment apic_nsec_since_boot */
if (vector == apic_clkvect) {
if (!apic_oneshot) {
/* NOTE: this is not MT aware */
}
/* We will avoid all the book keeping overhead for clock */
#if defined(__amd64)
#else
#endif
apicadr[APIC_EOI_REG] = 0;
return (nipl);
}
return (APIC_INT_SPURIOUS);
}
/* Check if the vector we got is really what we need */
if (apic_revector_pending) {
/*
* Disable interrupts for the duration of
* the vector translation to prevent a self-race for
* the apic_revector_lock. This cannot be done
* in apic_xlate_vector because it is recursive and
* we want the vector translation to be atomic with
* respect to other (higher-priority) interrupts.
*/
iflag = intr_clear();
}
#if defined(__amd64)
#else
#endif
/*
* apic_level_intr could have been assimilated into the irq struct.
* but, having it as a character array is more efficient in terms of
* cache usage. So, we leave it as is.
*/
if (!apic_level_intr[irq])
apicadr[APIC_EOI_REG] = 0;
#ifdef DEBUG
if (apic_break_on_cpu == psm_get_cpu_id())
apic_break();
#endif /* DEBUG */
return (nipl);
}
static void
{
#if defined(__amd64)
#else
#endif
if (apic_level_intr[irq])
apicadr[APIC_EOI_REG] = 0;
/* ISR above current pri could not be in progress */
}
/*
* Mask all interrupts below or equal to the given IPL
*/
static void
apic_setspl(int ipl)
{
#if defined(__amd64)
#else
#endif
/* interrupts at ipl above this cannot be in progress */
/*
* this is a patch fix for the ALR QSMP P5 machine, so that interrupts
* have enough time to come in before the priority is raised again
* during the idle() loop.
*/
if (apic_setspl_delay)
(void) get_apic_pri();
}
/*
* trigger a software interrupt at the given IPL
*/
static void
apic_set_softintr(int ipl)
{
int vector;
flag = intr_clear();
while (get_apic_cmd1() & AV_PENDING)
apic_ret();
/* generate interrupt at vector on itself only */
}
/*
* generates an interprocessor interrupt to another CPU
*/
static void
{
int vector;
flag = intr_clear();
while (get_apic_cmd1() & AV_PENDING)
apic_ret();
}
/*ARGSUSED*/
static void
{
}
/*ARGSUSED*/
static void
{
}
static void
apic_ret()
{
}
static int
{
return (apicadr[APIC_INT_CMD1]);
}
static int
{
#if defined(__amd64)
return ((int)getcr8());
#else
return (apicadr[APIC_TASK_REG]);
#endif
}
/*
* If apic_coarse_time == 1, then apic_gettime() is used instead of
* apic_gethrtime(). This is used for performance instead of accuracy.
*/
static hrtime_t
{
int old_hrtime_stamp;
/*
* In one-shot mode, we do not keep time, so if anyone
* calls psm_gettime() directly, we vector over to
* gethrtime().
* one-shot mode MUST NOT be enabled if this psm is the source of
* hrtime.
*/
if (apic_oneshot)
return (gethrtime());
apic_ret();
goto gettime_again;
}
return (temp);
}
/*
* Here we return the number of nanoseconds since booting. Note every
* clock interrupt increments apic_nsec_since_boot by the appropriate
* amount.
*/
static hrtime_t
{
int old_hrtime_stamp, status;
/*
* In one-shot mode, we do not keep time, so if anyone
* calls psm_gethrtime() directly, we vector over to
* gethrtime().
* one-shot mode MUST NOT be enabled if this psm is the source of
* hrtime.
*/
if (apic_oneshot)
return (gethrtime());
apic_ret();
/*
* Check to see which CPU we are on. Note the time is kept on
* the local APIC of CPU 0. If on CPU 0, simply read the current
* counter. If on another CPU, issue a remote read command to CPU 0.
*/
} else {
while (get_apic_cmd1() & AV_PENDING)
apic_ret();
apic_ret();
else { /* 0 = invalid */
/*
* return last hrtime right now, will need more
* testing if change to retry
*/
return (temp);
}
}
if (countval > last_count_read)
countval = 0;
else
/* we might have clobbered last_count_read. Restore it */
goto gethrtime_again;
}
if (temp < apic_last_hrtime) {
/* return last hrtime if error occurs */
}
else
return (temp);
}
/* apic NMI handler */
/*ARGSUSED*/
static void
{
if (apic_shutdown_processors) {
return;
}
if (lock_try(&apic_nmi_lock)) {
if (apic_kmdb_on_nmi) {
if (psm_debugger() == 0) {
"NMI detected, kmdb is not available.");
} else {
debug_enter("\nNMI detected, entering kmdb.\n");
}
} else {
if (apic_panic_on_nmi) {
/* Keep panic from entering kmdb. */
nopanicdebug = 1;
} else {
/*
* prom_printf is the best shot we have
* of something which is problem free from
*/
prom_printf("pcplusmp: NMI received\n");
}
}
}
}
/*
* Add mask bits to disable interrupt vector from happening
* at or above IPL. In addition, it should remove mask bits
* to enable interrupt vectors below the given IPL.
*
* Both add and delspl are complicated by the fact that different interrupts
* may share IRQs. This can happen in two ways.
* 1. The same H/W line is shared by more than 1 device
* 1a. with interrupts at different IPLs
* 1b. with interrupts at same IPL
* 2. We ran out of vectors at a given IPL and started sharing vectors.
* 1b and 2 should be handled gracefully, except for the fact some ISRs
* will get called often when no interrupt is pending for the device.
* For 1a, we just hope that the machine blows up with the person who
* set it up that way!. In the meantime, we handle it at the higher IPL.
*/
/*ARGSUSED*/
static int
{
int iflag;
int irqindex;
return (PSM_FAILURE);
while (irqptr) {
break;
}
irqptr->airq_share++;
/* return if it is not hardware interrupt */
return (PSM_SUCCESS);
/* Or if there are more interupts at a higher IPL */
return (PSM_SUCCESS);
/*
* if apic_picinit() has not been called yet, just return.
* At the end of apic_picinit(), we will call setup_io_intr().
*/
if (!apic_flag)
return (PSM_SUCCESS);
iflag = intr_clear();
/*
* Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate,
* return failure. Not very elegant, but then we hope the
* machine will blow up with ...
*/
if (vector == 0) {
irqptr->airq_share--;
return (PSM_FAILURE);
}
irqptr = irqheadptr;
while (irqptr) {
/*
* reprogram irq being added and every one else
* who is not in the UNINIT state
*/
}
}
return (PSM_SUCCESS);
}
return (PSM_SUCCESS);
}
/*
* Recompute mask bits for the given interrupt vector.
* If there is no interrupt servicing routine for this
* vector, this function should disable interrupt vector
* from happening at all IPLs. If there are still
* handlers using the given vector, this function should
* disable the given vector from happening below the lowest
* IPL of the remaining hadlers.
*/
/*ARGSUSED*/
static int
{
while (irqptr) {
break;
}
irqptr->airq_share--;
return (PSM_SUCCESS);
/* return if it is not hardware interrupt */
return (PSM_SUCCESS);
if (!apic_flag) {
/*
* Clear irq_struct. If two devices shared an intpt
* line & 1 unloaded before picinit, we are hosed. But, then
* we hope the machine will ...
*/
return (PSM_SUCCESS);
}
/*
* Downgrade vector to new max_ipl if needed.If we cannot allocate,
* use old IPL. Not very elegant, but then we hope ...
*/
irqp = irqheadptr;
while (irqp) {
(void) apic_setup_io_intr(irqp,
irqindex);
}
}
}
}
if (irqptr->airq_share)
return (PSM_SUCCESS);
iflag = intr_clear();
/* Disable the MSI/X vector */
/*
* Make sure we only disable on the last
* of the multi-MSI support
*/
}
}
if (max_ipl == PSM_INVALID_IPL) {
if (bind_cpu & IRQ_USER_BOUND) {
/* If hardbound, temp_cpu == cpu */
bind_cpu &= ~IRQ_USER_BOUND;
} else
}
return (PSM_SUCCESS);
}
/* Move valid irq entry to the head */
while (irqptr) {
break;
}
/* remove all invalid ones from the beginning */
/*
* and link them back after the head. The invalid ones
* begin with irqheadptr and end at oldirqptr
*/
}
return (PSM_SUCCESS);
}
/*
* Return HW interrupt number corresponding to the given IPL
*/
/*ARGSUSED*/
static int
apic_softlvl_to_irq(int ipl)
{
/*
* Do not use apic to trigger soft interrupt.
* It will cause the system to hang when 2 hardware interrupts
* at the same priority with the softint are already accepted
* by the apic. Cause the AV_PENDING bit will not be cleared
* until one of the hardware interrupt is eoi'ed. If we need
* to send an ipi at this time, we will end up looping forever
* to wait for the AV_PENDING bit to clear.
*/
return (PSM_SV_SOFTWARE);
}
static int
{
int i, cpun;
/*
* since some systems don't enable the internal cache on the non-boot
* cpus, so we have to enable them here
*/
while (get_apic_cmd1() & AV_PENDING)
apic_ret();
cpun = psm_get_cpu_id();
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
irq_ptr = apic_irq_table[i];
continue;
while (irq_ptr) {
}
}
return (PSM_SUCCESS);
}
{
int i;
if (cpu_id == -1)
return ((processorid_t)0);
if (apic_cpumask & (1 << i))
return (i);
}
return ((processorid_t)-1);
}
/*
* type == -1 indicates it is an internal request. Do not change
* resv_vector for these requests
*/
static int
{
int irq;
if (type != -1) {
}
return (irq);
}
}
return (-1); /* shouldn't happen */
}
static int
apic_getclkirq(int ipl)
{
int irq;
return (-1);
/*
* Note the vector in apic_clkvect for per clock handling.
*/
apic_clkvect));
return (irq);
}
/*
* Return the number of APIC clock ticks elapsed for 8245 to decrement
* (APIC_TIME_COUNT + pit_ticks_adj) ticks.
*/
static uint_t
{
int iflag;
addr += APIC_CURR_COUNT;
iflag = intr_clear();
do {
} while (pit_tick < APIC_TIME_MIN ||
/*
* Wait for the 8254 to decrement by 5 ticks to ensure
* we didn't start in the middle of a tick.
* Compare with 0x10 for the wrap around case.
*/
do {
start_apic_tick = *addr;
/*
* Wait for the 8254 to decrement by
* (APIC_TIME_COUNT + pit_ticks_adj) ticks
*/
do {
end_apic_tick = *addr;
return (start_apic_tick - end_apic_tick);
}
/*
* Initialise the APIC timer on the local APIC of CPU 0 to the desired
* frequency. Note at this stage in the boot sequence, the boot processor
* is the only active processor.
* hertz value of 0 indicates a one-shot mode request. In this case
* the function returns the resolution (in nanoseconds) for the hardware
* timer interrupt. If one-shot mode capability is not available,
* the return value will be 0. apic_enable_oneshot is a global switch
* for disabling the functionality.
* A non-zero positive value for hertz indicates a periodic mode request.
* In this case the hardware will be programmed to generate clock interrupts
* at hertz frequency and returns the resolution of interrupts in
* nanosecond.
*/
static int
apic_clkinit(int hertz)
{
uint_t apic_ticks = 0;
int ret;
static int firsttime = 1;
if (firsttime) {
/* first time calibrate */
/* set periodic interrupt based on CLKIN */
tenmicrosec();
/*
* pit time is the amount of real time (in nanoseconds ) it took
* the 8254 to decrement (APIC_TIME_COUNT + pit_ticks_adj) ticks
*/
/*
* Determine the number of nanoseconds per APIC clock tick
* and then determine how many APIC ticks to interrupt at the
* desired frequency
*/
if (apic_nsec_per_tick == 0)
apic_nsec_per_tick = 1;
/* the interval timer initial count is 32 bit max */
firsttime = 0;
}
if (hertz != 0) {
/* periodic */
}
if (hertz == 0) {
/* requested one_shot */
if (!apic_oneshot_enable)
return (0);
apic_oneshot = 1;
ret = (int)apic_nsec_per_tick;
} else {
/* program the local APIC to interrupt at the given frequency */
apic_oneshot = 0;
}
return (ret);
}
/*
* apic_preshutdown:
* Called early in shutdown whilst we can still access filesystems to do
* things like loading modules which will be required to complete shutdown
* after filesystems are all unmounted.
*/
static void
{
APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n",
return;
}
}
static void
{
int i, j;
/* Send NMI to all CPUs except self to do per processor shutdown */
iflag = intr_clear();
while (get_apic_cmd1() & AV_PENDING)
apic_ret();
/* restore cmos shutdown byte before reboot */
if (apic_cmos_ssb_set) {
}
/* Disable the I/O APIC redirection entries */
for (j = 0; j < apic_io_max; j++) {
int intin_max;
/* Bits 23-16 define the maximum redirection entries */
for (i = 0; i < intin_max; i++) {
}
}
/* disable apic mode if imcr present */
if (apic_imcrp) {
}
return;
}
switch (apic_poweroff_method) {
case APIC_POWEROFF_VIA_RTC:
/* select the extended NVRAM bank in the RTC */
/* for Predator must toggle the PAB bit */
/*
* clear power active bar, wakeup alarm and
* kickstart
*/
/* delay before next write */
drv_usecwait(1000);
/* for S40 the following would suffice */
/* power active bar control bit */
break;
restarts = 0;
if (++restarts == 3)
break;
attempts = 0;
do {
byte &= MISMIC_BUSY_MASK;
if (byte != 0) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_aspen_bmc;
++attempts;
}
} while (byte != 0);
byte |= 0x1;
i = 0;
i++) {
attempts = 0;
do {
byte &= MISMIC_BUSY_MASK;
if (byte != 0) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_aspen_bmc;
++attempts;
}
} while (byte != 0);
byte |= 0x1;
}
break;
restarts = 0;
if (++restarts == 3)
break;
attempts = 0;
do {
byte &= SMS_STATE_MASK;
if ((byte == SMS_READ_STATE) ||
(byte == SMS_WRITE_STATE)) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_sitka_bmc;
++attempts;
}
} while ((byte == SMS_READ_STATE) ||
(byte == SMS_WRITE_STATE));
i = 0;
i++) {
attempts = 0;
do {
byte &= SMS_IBF_MASK;
if (byte != 0) {
drv_usecwait(1000);
if (attempts >= 3)
goto restart_sitka_bmc;
++attempts;
}
} while (byte != 0);
}
break;
case APIC_POWEROFF_NONE:
/* If no APIC direct method, we will try using ACPI */
if (apic_enable_acpi) {
if (acpi_poweroff() == 1)
return;
} else
return;
break;
}
/*
* Wait a limited time here for power to go off.
* If the power does not go off, then there was a
* problem and we should continue to the halt which
* prints a message for the user to press a key to
* reboot.
*/
}
/*
* Try and disable all interrupts. We just assign interrupts to other
* processors based on policy. If any were bound by user request, we
* let them continue and return failure. We do not bother to check
* for cache affinity while rebinding.
*/
static int
{
if (cpun == 0)
return (PSM_FAILURE);
iflag = intr_clear();
i = apic_min_device_irq;
for (; i <= apic_max_device_irq; i++) {
/*
* If there are bound interrupts on this cpu, then
* rebind them to other processors.
*/
apic_nproc));
hardbound = 1;
continue;
}
do {
apic_next_bind_cpu += 2;
if (bind_cpu >= apic_nproc) {
apic_next_bind_cpu = 1;
bind_cpu = 0;
}
}
}
}
if (hardbound) {
"due to user bound interrupts", cpun);
return (PSM_FAILURE);
}
else
return (PSM_SUCCESS);
}
static void
{
int i, iflag;
iflag = intr_clear();
i = apic_min_device_irq;
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
(void) apic_rebind_all(irq_ptr,
}
}
}
}
/*
* apic_introp_xlate() replaces apic_translate_irq() and is
* called only from apic_intr_ops(). With the new ADII framework,
* the priority can no longer be retrived through i_ddi_get_intrspec().
* It has to be passed in from the caller.
*/
int
{
char dev_type[16];
struct apic_io_intr *intrp;
irqno));
if (DDI_INTR_IS_MSI_OR_MSIX(type)) {
}
bustype = 0;
/* check if we have already translated this irq */
while (airqp) {
}
}
}
if (apic_defconf)
goto defconf;
goto nonpci;
&dev_len) != DDI_PROP_SUCCESS) {
goto nonpci;
}
/* pci device */
goto nonpci;
busid = (int)apic_single_pci_busid;
goto nonpci;
if (apic_enable_acpi && !apic_use_acpi_madt_only) {
goto nonpci;
goto nonpci;
return (newirq);
} else {
== NULL) {
goto nonpci;
}
goto nonpci;
return (newirq);
}
if (apic_enable_acpi && !apic_use_acpi_madt_only) {
/* search iso entries first */
if (acpi_iso_cnt != 0) {
i = 0;
while (i < acpi_iso_cnt) {
return (apic_setup_irq_table(
}
i++;
}
}
}
} else {
if (bustype == 0)
for (i = 0; i < 2; i++) {
!= NULL)) {
return (newirq);
}
goto defconf;
}
}
}
/* MPS default configuration */
if (newirq == -1)
return (newirq);
return (newirq);
}
/*
* On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
* needs special handling. We may need to chase up the device tree,
* using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
* to find the IPIN at the root bus that relates to the IPIN on the
* subsidiary bus (for ACPI or MP). We may, however, have an entry
* in the MP table or the ACPI namespace for this device itself.
* We handle both cases in the search below.
*/
/* this is the non-acpi version */
static int
struct apic_io_intr **intrp)
{
int pci_irq;
int bridge_devno, bridge_bus;
int ipin;
/*CONSTCOND*/
while (1) {
return (-1);
PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
NULL) != 0)
return (-1);
/*
* This is the rotating scheme that Compaq is using
* and documented in the pci to pci spec. Also, if
* the pci to pci bridge is behind another pci to
* pci bridge, then it need to keep transversing
* up until an interrupt entry is found or reach
* the top of the tree
*/
bridge_bus = (int)apic_single_pci_busid;
(ipin & 0x3);
bridge_bus)) != NULL) {
return (pci_irq);
}
child_ipin = ipin;
} else
return (-1);
}
/*LINTED: function will not fall off the bottom */
}
static uchar_t
acpi_find_ioapic(int irq)
{
int i;
for (i = 0; i < apic_io_max; i++) {
return (i);
}
return (0xFF); /* shouldn't happen */
}
/*
* See if two irqs are compatible for sharing a vector.
* Currently we only support sharing of PCI devices.
*/
static int
{
/* Assume active high by default */
po1 = 0;
po2 = 0;
return (0);
else
po1 = AV_ACTIVE_LOW;
else
po2 = AV_ACTIVE_LOW;
return (1);
return (0);
}
/*
* Attempt to share vector with someone else
*/
static int
{
#ifdef DEBUG
#endif /* DEBUG */
if (intr_flagp)
newirq = apic_vector_to_irq[i];
if (newirq == APIC_RESV_IRQ)
continue;
/* not compatible */
continue;
chosen_irq = newirq;
}
}
if (chosen_irq != -1) {
/*
* Assign a share id which is free or which is larger
* than the largest one.
*/
share_id = 1;
while (irqptr) {
break;
}
#ifdef DEBUG
#endif /* DEBUG */
}
if (!irqptr) {
#ifdef DEBUG
#endif /* DEBUG */
}
if (intr_flagp)
#ifdef DEBUG
/* shuffle the pointers to test apic_delspl path */
if (tmpirqp) {
}
#endif /* DEBUG */
}
return (-1);
}
/*
*
*/
static int
{
int newirq, intr_index;
if (DDI_INTR_IS_MSI_OR_MSIX(type)) {
/* MSI/X doesn't need to setup ioapic stuffs */
ioapicindex = 0xff;
ioapic = 0xff;
/* need an irq for MSI/X to index into autovect[] */
return (-1);
}
/* Find ioapicindex. If destid was ALL, we will exit with 0. */
break;
(ioapic == INTR_ALL_APIC));
/* check whether this intin# has been used by another irqno */
return (newirq);
}
} else if (intr_flagp != NULL) {
/* ACPI case */
if (apic_irq_table[irqno] &&
return (irqno);
}
} else {
/* default configuration */
ioapicindex = 0;
}
irqno));
/* This is OK to do really */
" instance %d and SCI",
} else {
" instance %d and %s instance %d",
}
return (newirq);
}
/* try high priority allocation now that share has failed */
return (-1);
}
}
} else {
/*
* The slot is used by another irqno, so allocate
* a free irqno for this interrupt
*/
if (newirq == -1) {
return (-1);
}
KM_SLEEP);
}
}
}
irqptr->airq_share_id = 0;
if (intr_flagp)
if (!DDI_INTR_IS_MSI_OR_MSIX(type)) {
/* setup I/O APIC entry for non-MSI/X interrupts */
}
return (irqno);
}
/*
* return the cpu to which this intr should be bound.
* Check properties or any other mechanism to see if user wants it
* bound to a specific CPU. If so, return the cpu id with high bit set.
* If not, use the policy to choose a cpu and return the id.
*/
{
char prop_name[32];
if (apic_intr_policy == INTR_LOWEST_PRIORITY)
return (IRQ_UNBOUND);
i = apic_min_device_irq;
for (; i <= apic_max_device_irq; i++) {
== FREE_INDEX))
continue;
(!(apic_irq_table[i]->airq_cpu &
IRQ_USER_BOUND))) {
"!pcplusmp: %s (%s) instance #%d "
"vector 0x%x ioapic 0x%x "
"intin 0x%x is bound to cpu %d\n",
return (cpu);
}
}
}
/*
* search for "drvname"_intpt_bind_cpus property first, the
* syntax of the property should be "a[,b,c,...]" where
* instance 0 binds to cpu a, instance 1 binds to cpu b,
* instance 3 binds to cpu c...
* ddi_getlongprop() will search /option first, then /
* if "drvname"_intpt_bind_cpus doesn't exist, then find
* intpt_bind_cpus property. The syntax is the same, and
* it applies to all the devices if its "drvname" specific
* property doesn't exist
*/
if (rc != DDI_PROP_SUCCESS) {
}
}
if (rc == DDI_PROP_SUCCESS) {
if (prop_val[i] == ',')
count++;
count++;
/*
* if somehow the binding instances defined in the
* property are not enough for this instno., then
* reuse the pattern for the next instance until
* it reaches the requested instno
*/
i = 0;
while (i < instno)
if (*cptr++ == ',')
i++;
/* if specific cpu is bogus, then default to cpu 0 */
if (bind_cpu >= apic_nproc) {
bind_cpu = 0;
} else {
/* indicate that we are bound at user request */
}
/*
* no need to check apic_cpus[].aci_status, if specific cpu is
* not up, then post_cpu_start will handle it.
*/
} else {
/*
* We change bind_cpu only for every two calls
* as most drivers still do 2 add_intrs for every
* interrupt
*/
if (bind_cpu >= apic_nproc) {
apic_next_bind_cpu = 1;
bind_cpu = 0;
}
}
"vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n",
else
"vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n",
}
static struct apic_io_intr *
{
struct apic_io_intr *intrp;
/*
* It can have more than 1 entry with same source bus IRQ,
* but unique with the source bus id
*/
return (intrp);
intrp++;
}
}
return ((struct apic_io_intr *)NULL);
}
struct mps_bus_info {
char *bus_name;
int bus_id;
} bus_info_array[] = {
"ISA ", BUS_ISA,
"PCI ", BUS_PCI,
"EISA ", BUS_EISA,
"XPRESS", BUS_XPRESS,
"PCMCIA", BUS_PCMCIA,
"VL ", BUS_VL,
"CBUS ", BUS_CBUS,
"CBUSII", BUS_CBUSII,
"FUTURE", BUS_FUTURE,
"INTERN", BUS_INTERN,
"MBI ", BUS_MBI,
"MBII ", BUS_MBII,
"MPI ", BUS_MPI,
"MPSA ", BUS_MPSA,
"NUBUS ", BUS_NUBUS,
"TC ", BUS_TC,
"VME ", BUS_VME
};
static int
apic_find_bus_type(char *bus)
{
int i = 0;
for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
return (bus_info_array[i].bus_id);
return (0);
}
static int
apic_find_bus(int busid)
{
busp++;
}
return (0);
}
static int
apic_find_bus_id(int bustype)
{
busp++;
}
bustype));
return (-1);
}
/*
* Check if a particular irq need to be reserved for any io_intr
*/
static struct apic_io_intr *
apic_find_io_intr(int irqno)
{
struct apic_io_intr *intrp;
return (intrp);
intrp++;
}
}
return ((struct apic_io_intr *)NULL);
}
/*
* Check if the given ioapicindex intin combination has already been assigned
* an irq. If so return irqno. Else -1
*/
static int
{
int i;
/* find ioapic and intin in the apic_irq_table[] and return the index */
for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
irqptr = apic_irq_table[i];
while (irqptr) {
if ((irqptr->airq_mps_intr_index >= 0) &&
"entry for ioapic:intin %x:%x "
return (i);
}
}
}
return (-1);
}
int
apic_allocate_irq(int irq)
{
int freeirq, i;
/*
* if BIOS really defines every single irq in the mps
* table, then don't worry about conflicting with
* them, just use any free slot in apic_irq_table
*/
for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
if ((apic_irq_table[i] == NULL) ||
FREE_INDEX) {
freeirq = i;
break;
}
}
if (freeirq == -1) {
/* This shouldn't happen, but just in case */
return (-1);
}
}
return (-1);
}
}
return (freeirq);
}
static int
{
int i;
/* Check if any I/O entry needs this IRQ */
if (apic_find_io_intr(i) == NULL) {
/* Then see if it is free */
if ((apic_irq_table[i] == NULL) ||
(apic_irq_table[i]->airq_mps_intr_index ==
FREE_INDEX)) {
return (i);
}
}
return (-1);
}
/*
* Allocate a free vector for irq at ipl. Takes care of merging of multiple
* IPLs into a single APIC level as well as stretching some IPLs onto multiple
* levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
* requests and allocated only when pri is set.
*/
static uchar_t
{
#ifdef DEBUG
if (apic_restrict_vector) /* for testing shared interrupt logic */
#endif /* DEBUG */
if (pri == 0)
if ((i == T_FASTTRAP) || (i == APIC_SPUR_INTR) ||
(i == T_SYSCALLINT) || (i == T_DTRACE_PROBE) ||
(i == T_DTRACE_RET))
continue;
if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
return (i);
}
}
return (0);
}
static void
{
}
/*
* Mark vector as being in the process of being deleted. Interrupts
* may still come in on some CPU. The moment an interrupt comes with
* the new vector, we know we can free the old one. Called only from
* addspl and delspl with interrupts disabled. Because an interrupt
* can be shared, but no interrupt from either device may come in,
* we also use a timeout mechanism, which we arbitrarily set to
* apic_revector_timeout microseconds.
*/
static void
{
int iflag = intr_clear();
if (!apic_oldvec_to_newvec) {
if (!apic_oldvec_to_newvec) {
/*
* This failure is not catastrophic.
* But, the oldvec will never be freed.
*/
return;
}
}
/* See if we already did this for drivers which do double addintrs */
}
}
/*
* xlate_vector is called from intr_enter if revector_pending is set.
* It will xlate it if needed and mark the old vector as free.
*/
static uchar_t
{
/* Do we really need to do this ? */
if (!apic_revector_pending) {
return (vector);
}
else {
/*
* The incoming vector is new . See if a stale entry is
* remaining
*/
}
if (oldvector) {
/* There could have been more than one reprogramming! */
return (apic_xlate_vector(newvector));
}
return (vector);
}
void
{
int iflag;
iflag = intr_clear();
}
}
/* Mark vector as not being used by any irq */
static void
{
}
/*
* compute the polarity, trigger mode and vector for programming into
* the I/O apic and record in airq_rdt_entry.
*/
static void
{
short intr_index;
struct apic_io_intr *iointrp;
if (intr_index == RESERVE_INDEX) {
return;
} else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
return;
}
/* Assume edge triggered by default */
level = 0;
/* Assume active high by default */
po = 0;
} else if (intr_index == ACPI_INDEX) {
} else
AV_LEVEL : 0;
if (level &&
po = AV_ACTIVE_LOW;
} else {
} else
AV_LEVEL : 0;
po = AV_ACTIVE_LOW;
}
if (level)
/*
* The 82489DX External APIC cannot do active low polarity interrupts.
*/
else
io_po = 0;
printf("setio: ioapic=%x intin=%x level=%x po=%x vector=%x\n",
}
/*
* Call rebind to do the actual programming.
*/
static int
{
int rv;
/* CPU is not up or interrupt is disabled. Fall back to 0 */
return (rv);
}
/*
* Deferred reprogramming: Call apic_rebind to do the real work.
*/
static int
{
int rv;
DEFERRED))
/* CPU is not up or interrupt is disabled. Fall back to 0 */
return (rv);
}
/*
* Bind interrupt corresponding to irq_ptr to bind_cpu. acquire_lock
* if false (0) means lock is already held (e.g: in rebind_all).
*/
static int
{
int intin_no;
int iflag;
if (airq_temp_cpu & IRQ_USER_BOUND)
/* Mask off high bit so it can be used as array index */
}
iflag = intr_clear();
if (acquire_lock)
/*
* Can't bind to a CPU that's not online:
*/
if (acquire_lock)
return (1);
}
/*
* If this is a deferred reprogramming attempt, ensure we have
* not been passed stale data:
*/
/* stale info, so just return */
if (acquire_lock)
return (0);
}
/*
* If this interrupt has been delivered to a CPU and that CPU
* has not handled it yet, we cannot reprogram the IOAPIC now:
*/
if (acquire_lock)
return (0);
}
/*
* NOTE: We do not unmask the RDT here, as an interrupt MAY still
* come in before we have a chance to reprogram it below. The
* reprogramming below will simultaneously change and unmask the
* RDT entry.
*/
/* Write the RDT entry -- no specific CPU binding */
/* Write the vector, trigger, and polarity portion of the RDT */
if (acquire_lock)
return (0);
}
if (bind_cpu & IRQ_USER_BOUND) {
} else {
}
/* Write the RDT entry -- bind to a specific CPU: */
}
}
/* Write the vector, trigger, and polarity portion of the RDT */
} else {
/* first one */
"apic_pci_msi_enable_vector\n"));
"apic_pci_msi_enable_vector "
"returned PSM_FAILURE");
}
}
"pci_msi_enable_mode\n"));
which_irq) != DDI_SUCCESS) {
"pci_msi_enable failed\n"));
}
}
}
if (acquire_lock)
return (0);
}
/*
* Checks to see if the IOAPIC interrupt entry specified has its Remote IRR
* bit set. Sets up a timeout to perform the reprogramming at a later time
* if it cannot wait for the Remote IRR bit to clear (or if waiting did not
* result in the bit's clearing).
*
* This function will mask the RDT entry if the Remote IRR bit is set.
*
* Returns non-zero if the caller should defer IOAPIC reprogramming.
*/
static int
{
int waited;
/* Mask the RDT entry, but only if it's a level-triggered interrupt */
/* Mask it */
}
/*
* Wait for the delivery pending bit to clear.
*/
/*
* If we're still waiting on the delivery of this interrupt,
* continue to wait here until it is delivered (this should be
* a very small amount of time, but include a timeout just in
* case).
*/
& AV_PENDING) == 0) {
break;
}
}
AV_PENDING) != 0) {
"deliver interrupt to local APIC within "
}
}
/*
* If the remote IRR bit is set, then the interrupt has been sent
* to a CPU for processing. We have no choice but to wait for
* that CPU to process the interrupt, at which point the remote IRR
* bit will be cleared.
*/
/*
* If the CPU that this RDT is bound to is NOT the current
* CPU, wait until that CPU handles the interrupt and ACKs
* it. If this interrupt is not bound to any CPU (that is,
* if it's bound to the logical destination of "anyone"), it
* may have been delivered to the current CPU so handle that
* case by deferring the reprogramming (below).
*/
if ((old_bind_cpu != IRQ_UNBOUND) &&
(old_bind_cpu != IRQ_UNINIT) &&
(old_bind_cpu != psm_get_cpu_id())) {
intin_no) & AV_REMOTE_IRR) == 0) {
/* Clear the reprogramming state: */
= 0;
= 0;
= 0;
/* Remote IRR has cleared! */
return (0);
}
}
}
/*
* If we waited and the Remote IRR bit is still not cleared,
* AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
* times for this interrupt, try the last-ditch workarounds:
*/
& AV_REMOTE_IRR) != 0) {
/*
* Trying to clear the bit through normal
* channels has failed. So as a last-ditch
* effort, try to set the trigger mode to
* edge, then to level. This has been
* observed to work on many systems.
*/
/*
* If the bit's STILL set, declare total and
* utter failure
*/
intin_no) & AV_REMOTE_IRR) != 0) {
"Remote IRR failed to reset "
"within %d usecs. Interrupts to "
"this pin may cease to function.",
}
}
/* Clear the reprogramming state: */
} else {
#ifdef DEBUG
#endif /* DEBUG */
/*
* If waiting for the Remote IRR bit (above) didn't
* allow it to clear, defer the reprogramming:
*/
/* Fire up a timeout to handle this later */
(void *) 0,
/* Inform caller to defer IOAPIC programming: */
return (1);
}
}
return (0);
}
/*
* Timeout handler that performs the APIC reprogramming
*/
/*ARGSUSED*/
static void
{
/*LINTED: set but not used in function*/
int i, result;
/* Serialize access to this function */
/*
* For each entry in the reprogramming state that's valid,
* try the reprogramming again:
*/
for (i = 0; i < APIC_MAX_VECTOR; i++) {
if (apic_reprogram_info[i].valid == 0)
continue;
/*
* Though we can't really do anything about errors
* at this point, keep track of them for reporting.
* Note that it is very possible for apic_setup_io_intr
* to re-register this very timeout if the Remote IRR bit
* has not yet cleared.
*/
#ifdef DEBUG
if (result)
"apic_setup_io_intr returned nonzero for "
"irq=%d!", i);
#endif /* DEBUG */
}
}
/*
* Called to migrate all interrupts at an irq to another cpu. safe
* if true means we are not being called from an interrupt
* context and hence it is safe to do a lock_set. If false
* do only a lock_try and return failure ( non 0 ) if we cannot get it
*/
static int
{
int retval = 0;
int iflag;
iflag = intr_clear();
if (!safe) {
if (lock_try(&apic_ioapic_lock) == 0) {
return (1);
}
} else
while (irqptr) {
}
return (retval);
}
/*
* apic_intr_redistribute does all the messy computations for identifying
* which interrupt to move to which CPU. Currently we do just one interrupt
* at a time. This reduces the time we spent doing all this within clock
* interrupt. When it is done in idle, we could do more than 1.
* First we find the most busy and the most free CPU (time in ISR only)
* skipping those CPUs that has been identified as being ineligible (cpu_skip)
* Then we look for IRQs which are closest to the difference between the
* most busy CPU and the average ISR load. We try to find one whose load
* is less than difference.If none exists, then we chose one larger than the
* difference, provided it does not make the most idle CPU worse than the
* most busy one. In the end, we clear all the busy fields for CPUs. For
* IRQs, they are cleared as they are scanned.
*/
static void
{
int busiest_cpu, most_free_cpu;
int average_busy, cpus_online;
int i, busy;
cpus_online = 0;
/*
* Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu
* without ioapic_lock. That is OK as we are just doing statistical
* sampling anyway and any inaccuracy now will get corrected next time
* The call to rebind which actually changes things will make sure
* we are consistent.
*/
for (i = 0; i < apic_nproc; i++) {
if (!(apic_redist_cpu_skip & (1 << i)) &&
/*
* If no unbound interrupts or only 1 total on this
* CPU, skip
*/
if (!cpu_infop->aci_temp_bound ||
== 1) {
apic_redist_cpu_skip |= 1 << i;
continue;
}
average_busy += busy;
cpus_online++;
busiest_cpu = i;
}
most_free_cpu = i;
}
if (busy > apic_int_busy_mark) {
cpu_busy |= 1 << i;
} else {
if (busy < apic_int_free_mark)
cpu_free |= 1 << i;
}
}
}
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
"redistribute busy=%x free=%x max=%x min=%x",
}
#endif /* DEBUG */
max_busy = 0;
i = apic_min_device_irq;
for (; i < apic_max_device_irq; i++) {
/* Change to linked list per CPU ? */
continue;
/* Check for irq_busy & decide which one to move */
/* Also zero them for next round */
/*
* Check for least busy CPU,
* best fit or what ?
*/
/*
* Most busy within the
* required differential
*/
}
} else {
/*
* least busy, but more than
* the reqd diff
*/
if (min_busy <
(diff + average_busy -
min_free)) {
/*
* Making sure new cpu
* will not end up
* worse
*/
min_busy =
}
}
}
}
}
if (max_busy_irq != NULL) {
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
prom_printf("rebinding %x to %x",
}
#endif /* DEBUG */
== 0)
/* Make change permenant */
} else if (min_busy_irq != NULL) {
#ifdef DEBUG
if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) {
prom_printf("rebinding %x to %x",
}
#endif /* DEBUG */
0)
/* Make change permenant */
} else {
/*
* We leave cpu_skip set so that next time we
* can choose another cpu
*/
}
}
} else {
/*
* found nothing. Could be that we skipped over valid CPUs
* or we have balanced everything. If we had a variable
* ticks_for_redistribution, it could be increased here.
* apic_int_busy, int_free etc would also need to be
* changed.
*/
if (apic_redist_cpu_skip)
apic_redist_cpu_skip = 0;
}
for (i = 0; i < apic_nproc; i++) {
}
}
static void
{
int i;
for (i = 0; i < apic_nproc; i++) {
}
for (i = apic_min_device_irq; i < apic_max_device_irq; i++) {
}
}
/*
* This function will reprogram the timer.
*
* When in oneshot mode the argument is the absolute time in future to
* generate the interrupt at.
*
* When in periodic mode, the argument is the interval at which the
* interrupts should be generated. There is no need to support the periodic
* mode timer change at this time.
*/
static void
{
/*
* We should be called from high PIL context (CBE_HIGH_PIL),
* so kpreempt is disabled.
*/
if (!apic_oneshot) {
/* time is the interval for periodic mode */
} else {
/* one shot mode */
/*
* requested to generate an interrupt in the past
* generate an interrupt as soon as possible
*/
/*
* requested to generate an interrupt at a time
* further than what we are capable of. Set to max
* the hardware can handle
*/
ticks = APIC_MAXVAL;
#ifdef DEBUG
" %lld too far in future, current time"
#endif /* DEBUG */
} else
}
if (ticks < apic_min_timer_ticks)
}
/*
* This function will enable timer interrupts.
*/
static void
apic_timer_enable(void)
{
/*
* We should be Called from high PIL context (CBE_HIGH_PIL),
* so kpreempt is disabled.
*/
if (!apic_oneshot)
else {
/* one shot */
}
}
/*
* This function will disable timer interrupts.
*/
static void
apic_timer_disable(void)
{
/*
* We should be Called from high PIL context (CBE_HIGH_PIL),
* so kpreempt is disabled.
*/
}
/*
* If this module needs to be a consumer of cyclic subsystem, they
* can be added here, since at this time kernel cyclic subsystem is initialized
* argument is not currently used, and is reserved for future.
*/
static void
apic_post_cyclic_setup(void *arg)
{
/* cpu_lock is held */
/* set up cyclics for intr redistribution */
/*
* In peridoc mode intr redistribution processing is done in
* apic_intr_enter during clk intr processing
*/
if (!apic_oneshot)
return;
}
static void
{
int i, j, max_busy;
if (++apic_nticks == apic_sample_factor_redistribution) {
/*
* Time to call apic_intr_redistribute().
* reset apic_nticks. This will cause max_busy
* to be calculated below and if it is more than
* apic_int_busy, we will do the whole thing
*/
apic_nticks = 0;
}
max_busy = 0;
for (i = 0; i < apic_nproc; i++) {
/*
* Check if curipl is non zero & if ISR is in
* progress
*/
if (((j = apic_cpus[i].aci_curipl) != 0) &&
int irq;
}
if (!apic_nticks &&
}
if (!apic_nticks) {
if (max_busy > apic_int_busy_mark) {
/*
* We could make the following check be
* skipped > 1 in which case, we get a
* redistribution at half the busy mark (due to
* double interval). Need to be able to collect
* more empirical data to decide if that is a
* good strategy. Punt for now.
*/
else
} else
}
}
}
static int
{
int status;
intr_flagp)) == ACPI_PSM_SUCCESS) {
"from cache for device %s, instance #%d\n", *pci_irqp,
return (status);
}
&acpipsmlnk)) == ACPI_PSM_FAILURE) {
" acpi_translate_pci_irq failed for device %s, instance"
return (status);
}
if (status != ACPI_PSM_SUCCESS) {
}
}
if (status == ACPI_PSM_SUCCESS) {
intr_flagp, &acpipsmlnk);
"new irq %d for device %s, instance #%d\n",
}
return (status);
}
/*
* Configures the irq for the interrupt link device identified by
* acpipsmlnkp.
*
* Gets the current and the list of possible irq settings for the
* device. If apic_unconditional_srs is not set, and the current
* resource setting is in the list of possible irq settings,
* current irq resource setting is passed to the caller.
*
* Otherwise, picks an irq number from the list of possible irq
* settings, and sets the irq of the device to this value.
* If prefer_crs is set, among a set of irq numbers in the list that have
* the least number of devices sharing the interrupt, we pick current irq
* resource setting if it is a member of this set.
*
* Passes the irq number in the value pointed to by pci_irqp, and
* polarity and sensitivity in the structure pointed to by dipintrflagp
* to the caller.
*
* Note that if setting the irq resource failed, but successfuly obtained
* the current irq resource settings, passes the current irq resources
* and considers it a success.
*
* Returns:
* ACPI_PSM_SUCCESS on success.
*
* ACPI_PSM_FAILURE if an error occured during the configuration or
* if a suitable irq was not found for this device, or if setting the
* irq resource and obtaining the current resource fails.
*
*/
static int
{
int cur_irq = -1;
== ACPI_PSM_FAILURE) {
"or assign IRQ for device %s, instance #%d: The system was "
"unable to get the list of potential IRQs from ACPI.",
return (ACPI_PSM_FAILURE);
}
(cur_irq > 0)) {
/*
* If an IRQ is set in CRS and that IRQ exists in the set
* returned from _PRS, return that IRQ, otherwise print
* a warning
*/
== ACPI_PSM_SUCCESS) {
return (ACPI_PSM_SUCCESS);
}
"current irq %d for device %s, instance #%d in ACPI's "
"list of possible irqs for this device. Picking one from "
ddi_get_instance(dip)));
}
min_share = 255;
while (irqlistent != NULL) {
continue;
if (irq == 0) {
/* invalid irq number */
continue;
}
chosen_irq = irq;
foundnow = 1;
/*
* If we do not prefer current irq from crs
* or if we do and this irq is the same as
* current irq from crs, this is the one
* to pick.
*/
done = 1;
break;
}
continue;
}
continue;
continue;
foundnow = 1;
}
}
/*
* If we found an IRQ in the inner loop this time, save the
* details from the irqlist for later use.
*/
/*
* Copy the acpi_prs_private_t and flags from this
* irq list entry, since we found an irq from this
* entry.
*/
}
if (done)
break;
/* Go to the next irqlist entry */
}
if (chosen_irq != -1)
irq = chosen_irq;
else if (share_irq != -1)
else {
"suitable irq from the list of possible irqs for device "
"%s, instance #%d in ACPI's list of possible irqs",
return (ACPI_PSM_FAILURE);
}
/*
* setting irq was successful, check to make sure CRS
* reflects that. If CRS does not agree with what we
* set, return the irq that was set.
*/
dipintr_flagp) == ACPI_PSM_SUCCESS) {
"IRQ resource set (irqno %d) for device %s "
"instance #%d, differs from current "
"setting irqno %d",
}
/*
* return the irq that was set, and not what CRS reports,
* since CRS has been seen to be bogus on some systems
*/
} else {
"failed for device %s instance #%d",
if (cur_irq == -1)
return (ACPI_PSM_FAILURE);
}
return (ACPI_PSM_SUCCESS);
}