pcie_ck804_boot.c revision 7a23d1009aa28ea040052630547929b9c5eb6ab4
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml/*
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * CDDL HEADER START
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml *
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * The contents of this file are subject to the terms of the
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Common Development and Distribution License (the "License").
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * You may not use this file except in compliance with the License.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml *
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * or http://www.opensolaris.org/os/licensing.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * See the License for the specific language governing permissions
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * and limitations under the License.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml *
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * When distributing Covered Code, include this CDDL HEADER in each
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * If applicable, add the following below this CDDL HEADER, with the
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * fields enclosed by brackets "[]" replaced with your own identifying
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * information: Portions Copyright [yyyy] [name of copyright owner]
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml *
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * CDDL HEADER END
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml */
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml/*
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Use is subject to license terms.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml */
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#pragma ident "%Z%%M% %I% %E% SMI"
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml/*
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Library file that has code for PCIe booting
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#include <sys/conf.h>
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#include <sys/pci.h>
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#include <sys/sunndi.h>
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#include <sys/pcie.h>
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#include <sys/pci_cfgspace.h>
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#include <io/pciex/pcie_ck804_boot.h>
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml/*
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * PCI Configuration (ck804, PCIe) related library functions
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5mlstatic boolean_t look_for_any_pciex_device(uchar_t);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml/* Globals */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5mlextern int pci_boot_debug;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5mlboolean_t
6f45ec7b0b964c3be967c4880e8867ac1e7763a5mlcheck_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev,
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml uchar_t func, ushort_t *slot_number, ushort_t *is_pci_bridge)
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml{
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml boolean_t found_pciex = B_FALSE;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml ushort_t cap;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml ushort_t capsp;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml ushort_t cap_count = PCI_CAP_MAX_PTR;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml ushort_t status;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml uint32_t slot_cap;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml *slot_number = 0;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml if (!(status & PCI_STAT_CAP))
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml return (B_FALSE);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) {
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml capsp &= PCI_CAP_PTR_MASK;
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml cap = (*pci_getb_func)(bus, dev, func, capsp);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml if (cap == PCI_CAP_ID_PCIX && cdip)
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml "pcix-capid-pointer", capsp);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml if (cap == PCI_CAP_ID_PCI_E) {
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#ifdef DEBUG
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml if (pci_boot_debug)
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) "
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml "capability found\n", bus, dev, func);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#endif /* DEBUG */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml status = (*pci_getw_func)(bus, dev, func, capsp + 2);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml /*
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * See section 7.8.2 of PCI-Express Base Spec v1.0a
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * for Device/Port Type.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * device is a PCIe2PCI bridge
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml *is_pci_bridge =
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml ((status & PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ==
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ? 1 : 0;
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe /*
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe * Check for "Slot Implemented" bit
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe * PCIE_PCIECAP_SLOT_IMPL implies that.
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe */
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe if (status & PCIE_PCIECAP_SLOT_IMPL) {
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml /* offset 14h is Slot Cap Register */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml slot_cap = (*pci_getl_func)(bus, dev, func,
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml capsp + PCIE_SLOTCAP);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml *slot_number =
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml PCIE_SLOTCAP_PHY_SLOT_NUM(slot_cap);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml if (cdip)
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml (void) ndi_prop_update_int(
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml DDI_DEV_T_NONE, cdip,
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml "pcie-slotcap-reg", slot_cap);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml /* Is PCI Express HotPlug capability set? */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml if (cdip &&
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml (slot_cap & PCIE_SLOTCAP_HP_CAPABLE)) {
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml (void) ndi_prop_update_int(
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml DDI_DEV_T_NONE, cdip,
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml "pci-hotplug-type",
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml INBAND_HPC_PCIE);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml }
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml }
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml /*
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Can only do I/O based config space access at
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * this early stage. Meaning, one cannot access
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * extended config space i.e. > 256 bytes.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * So, AER cap_id property will be created much later.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml if (cdip) {
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml "pcie-capid-reg",
(*pci_getw_func)(bus, dev, func,
capsp + PCIE_PCIECAP));
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
"pcie-capid-pointer", capsp);
}
found_pciex = B_TRUE;
}
if (cdip && (cap == PCI_CAP_ID_PCI_HOTPLUG)) {
(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
"pci-hotplug-type", INBAND_HPC_SHPC);
}
capsp = (*pci_getb_func)(bus, dev, func,
capsp + PCI_CAP_NEXT_PTR);
}
return (found_pciex);
}
/*
* scan all buses, devices, functions to look for any
* PCI-Express device in the system.
* If found, return B_TRUE else B_FALSE
*/
static boolean_t
look_for_any_pciex_device(uchar_t bus)
{
uchar_t dev, func;
uchar_t nfunc, header;
ushort_t venid, slot_num, is_pci_bridge = 0;
for (dev = 0; dev < 32; dev++) {
nfunc = 1;
for (func = 0; func < nfunc; func++) {
#ifdef DEBUG
if (pci_boot_debug)
cmn_err(CE_NOTE, "pciex dev 0x%x, func 0x%x",
dev, func);
#endif /* DEBUG */
venid = (*pci_getw_func)(bus, dev, func,
PCI_CONF_VENID);
/* no function at this address */
if ((venid == 0xffff) || (venid == 0))
continue;
header = (*pci_getb_func)(bus, dev, func,
PCI_CONF_HEADER);
if (header == 0xff)
continue; /* illegal value */
/*
* according to some mail from Microsoft posted to
* the pci-drivers alias, their only requirement for
* a multifunction device is for the 1st function to
* have to PCI_HEADER_MULTI bit set.
*/
if ((func == 0) && (header & PCI_HEADER_MULTI))
nfunc = 8;
if (check_if_device_is_pciex(NULL, bus, dev, func,
&slot_num, &is_pci_bridge) == B_TRUE)
return (B_TRUE);
} /* end of func */
} /* end of dev */
return (B_FALSE);
}
boolean_t
create_pcie_root_bus(uchar_t bus, dev_info_t *dip)
{
/*
* Currently this is being hard-coded.
* We need to figure out if the root bus does indeed
* have PCI-Ex in the path by looking for MCFG in
* the ACPI tables
*/
if (look_for_any_pciex_device(bus) == B_FALSE)
return (B_FALSE);
#ifdef DEBUG
if (pci_boot_debug)
cmn_err(CE_CONT, "Found PCI-Ex in the system\n");
#endif /* DEBUG */
(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
"device_type", "pciex");
(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
"compatible", "pciex_root_complex");
return (B_TRUE);
}
/*
* Only for Nvidia's CrushK 8-04 chipsets:
* To enable hotplug; we need to map in two I/O BARs
* from ISA bridge's config space
*/
void
add_ck804_isa_bridge_props(dev_info_t *dip, uchar_t bus, uchar_t dev,
uchar_t func)
{
uint_t devloc, base;
pci_regspec_t regs[2] = {{0}};
pci_regspec_t assigned[2] = {{0}};
devloc = (uint_t)bus << PCI_REG_BUS_SHIFT |
(uint_t)dev << PCI_REG_DEV_SHIFT |
(uint_t)func << PCI_REG_FUNC_SHIFT;
regs[0].pci_phys_hi = devloc;
/* System Control BAR i/o space */
base = (*pci_getl_func)(bus, dev, func,
NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF);
regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE;
assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B |
PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF);
assigned[0].pci_phys_low = regs[0].pci_phys_low =
base & PCI_BASE_IO_ADDR_M;
/* Analog BAR i/o space */
base = (*pci_getl_func)(bus, dev, func,
NVIDIA_CK804_ISA_ANALOG_BAR_OFF);
regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE;
assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B |
PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_ANALOG_BAR_OFF);
assigned[1].pci_phys_low = regs[1].pci_phys_low =
base & PCI_BASE_IO_ADDR_M;
(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
(int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int));
(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
"assigned-addresses",
(int *)assigned, 2 * sizeof (pci_regspec_t) / sizeof (int));
}