pcie_ck804_boot.c revision 7a23d1009aa28ea040052630547929b9c5eb6ab4
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * CDDL HEADER START
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * The contents of this file are subject to the terms of the
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Common Development and Distribution License (the "License").
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * You may not use this file except in compliance with the License.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * See the License for the specific language governing permissions
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * and limitations under the License.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * When distributing Covered Code, include this CDDL HEADER in each
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * If applicable, add the following below this CDDL HEADER, with the
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6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * CDDL HEADER END
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Use is subject to license terms.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#pragma ident "%Z%%M% %I% %E% SMI"
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Library file that has code for PCIe booting
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * PCI Configuration (ck804, PCIe) related library functions
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml/* Globals */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5mlcheck_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev,
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml uchar_t func, ushort_t *slot_number, ushort_t *is_pci_bridge)
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR);
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml#endif /* DEBUG */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * See section 7.8.2 of PCI-Express Base Spec v1.0a
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * for Device/Port Type.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * device is a PCIe2PCI bridge
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe * Check for "Slot Implemented" bit
7014882c6a3672fd0e5d60200af8643ae53c5928Richard Lowe * PCIE_PCIECAP_SLOT_IMPL implies that.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml /* offset 14h is Slot Cap Register */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml /* Is PCI Express HotPlug capability set? */
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml "pci-hotplug-type",
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * Can only do I/O based config space access at
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * this early stage. Meaning, one cannot access
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * extended config space i.e. > 256 bytes.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml * So, AER cap_id property will be created much later.
6f45ec7b0b964c3be967c4880e8867ac1e7763a5ml "pcie-capid-reg",
return (found_pciex);
static boolean_t
#ifdef DEBUG
if (pci_boot_debug)
return (B_TRUE);
return (B_FALSE);
return (B_FALSE);
#ifdef DEBUG
if (pci_boot_debug)
return (B_TRUE);