npe_misc.c revision c1381f4429cde25f5ee926dfa005545a7f220ba9
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Library file that has miscellaneous support for npe(7d)
*/
#include <sys/pcie_impl.h>
#include <sys/x86_archext.h>
/*
* Prototype declaration
*/
/*
* Default ecfga base address
*/
extern uint32_t npe_aer_uce_mask;
extern boolean_t pcie_full_scan;
/* AMD's northbridges vendor-id and device-ids */
#define AMD_K10_NTBRIDGE_DID_0 0x1200
#define AMD_K10_NTBRIDGE_DID_1 0x1201
#define AMD_K10_NTBRIDGE_DID_2 0x1202
#define AMD_K10_NTBRIDGE_DID_3 0x1203
#define AMD_K10_NTBRIDGE_DID_4 0x1204
/*
* Check if the given device is an AMD northbridge
*/
(((vid) == AMD_NTBRDIGE_VID) && \
(((did) == AMD_HT_NTBRIDGE_DID) || \
((did) == AMD_AM_NTBRIDGE_DID) || \
((did) == AMD_DC_NTBRIDGE_DID) || \
((did) == AMD_MC_NTBRIDGE_DID)))
(((vid) == AMD_NTBRDIGE_VID) && \
(((did) == AMD_K10_NTBRIDGE_DID_0) || \
((did) == AMD_K10_NTBRIDGE_DID_1) || \
((did) == AMD_K10_NTBRIDGE_DID_2) || \
((did) == AMD_K10_NTBRIDGE_DID_3) || \
((did) == AMD_K10_NTBRIDGE_DID_4)))
#define MSR_AMD_NB_MMIO_CFG_BADDR 0xc0010058
#define AMD_MMIO_CFG_BADDR_ADDR_MASK 0xFFFFFFF00000ULL
#define AMD_MMIO_CFG_BADDR_ENA_MASK 0x000000000001ULL
#define AMD_MMIO_CFG_BADDR_ENA_ON 0x000000000001ULL
#define AMD_MMIO_CFG_BADDR_ENA_OFF 0x000000000000ULL
/*
* Query the MCFG table using ACPI. If MCFG is found, setup the
* 'ecfg' property accordingly. Otherwise, set the values
* to the default values.
*/
void
{
char *cfg_baa_endp;
int ecfg_found = 0;
/* Query the MCFG table using ACPI */
while ((char *)cfg_baap < cfg_baa_endp) {
/*
* Set up the 'ecfg' property to hold
* We only do the first entry that maps
* segment 0; nonzero segments are not yet
* known, or handled. If they appear,
* we'll need to figure out which bus node
* should have which entry by examining the
* ACPI _SEG method on each bus node.
*/
(void) ndi_prop_update_int64_array(
ecfginfo, 4);
ecfg_found = 1;
break;
}
cfg_baap++;
}
}
if (ecfg_found)
return;
/*
* If MCFG is not found or ecfga_base is not found in MCFG table,
* set the property to the default values.
*/
}
/*
* Enable reporting of AER capability next pointer.
* This needs to be done only for CK8-04 devices
* by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13
* NOTE: BIOS is disabling this, it needs to be enabled temporarily
*/
void
{
if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK))
(void) pci_config_put16(cfg_hdl,
}
}
/*
* If the bridge is empty, disable it
*/
int
{
/*
* Do not bind drivers to empty bridges.
* Fail above, if the bridge is found to be hotplug capable
*/
return (1);
return (0);
}
void
/* Disable ECRC for all devices */
/*
* Turn full scan on since the Error Source ID register may not
* have the correct ID.
*/
}
}
void
if (vendor_id == INTEL_VENDOR_ID) {
/*
* Due to an errata in Intel's ESB2 southbridge, all ECRCs
* generation/checking need to be disabled. There is a
* workaround by setting a proprietary bit in the ESB2, but it
* is not well documented or understood. If that bit is set in
* the future, then ECRC generation/checking should be enabled
* again.
*
* Disable ECRC generation/checking by masking ECRC in the AER
* UE Mask. The pcie misc module would then automatically
* disable ECRC generation/checking in the AER Control register.
*/
}
}
/*
* Check's if this child is a PCI device.
* Child is a PCI device if:
* parent has a dev_type of "pci"
* -and-
* child does not have a dev_type of "pciex"
*
* If the parent is not of dev_type "pci", then assume it is "pciex" and all
* children should support using PCIe style MMCFG access.
*
* If parent's dev_type is "pci" and child is "pciex", then also enable using
* PCIe style MMCFG access. This covers the case where NPE is "pci" and a PCIe
* RP is beneath.
*/
char *dev_type;
} else {
}
} else {
}
return (parent_is_pci && !child_is_pciex);
}
/*
* Checks to see if MMCFG is supported.
* Returns: TRUE if MMCFG is supported, FALSE if not.
*
* If a device is attached to a parent whose "dev_type" is "pciex",
* the device will support MMCFG access. Otherwise, use legacy IOCFG access.
*
* Enable Legacy PCI config space access for AMD K8 north bridges.
* Host bridge: AMD HyperTransport Technology Configuration
* Host bridge: AMD Address Map
* Host bridge: AMD DRAM Controller
* Host bridge: AMD Miscellaneous Control
* These devices do not support MMCFG access.
*/
{
"vendor-id", -1);
"device-id", -1);
return !(npe_child_is_pci(dip) ||
}