npe_misc.c revision eae2e508a8e70b1ec407b10bd068c080651bbe5c
70025d765b044c6d8594bb965a2247a61e991a99johnny * CDDL HEADER START
70025d765b044c6d8594bb965a2247a61e991a99johnny * The contents of this file are subject to the terms of the
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * Common Development and Distribution License (the "License").
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * You may not use this file except in compliance with the License.
70025d765b044c6d8594bb965a2247a61e991a99johnny * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
70025d765b044c6d8594bb965a2247a61e991a99johnny * See the License for the specific language governing permissions
70025d765b044c6d8594bb965a2247a61e991a99johnny * and limitations under the License.
70025d765b044c6d8594bb965a2247a61e991a99johnny * When distributing Covered Code, include this CDDL HEADER in each
70025d765b044c6d8594bb965a2247a61e991a99johnny * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
70025d765b044c6d8594bb965a2247a61e991a99johnny * If applicable, add the following below this CDDL HEADER, with the
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70025d765b044c6d8594bb965a2247a61e991a99johnny * information: Portions Copyright [yyyy] [name of copyright owner]
70025d765b044c6d8594bb965a2247a61e991a99johnny * CDDL HEADER END
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
70025d765b044c6d8594bb965a2247a61e991a99johnny * Use is subject to license terms.
70025d765b044c6d8594bb965a2247a61e991a99johnny#pragma ident "%Z%%M% %I% %E% SMI"
70025d765b044c6d8594bb965a2247a61e991a99johnny * Library file that has miscellaneous support for npe(7d)
70025d765b044c6d8594bb965a2247a61e991a99johnny * Prototype declaration
7a23d1009aa28ea040052630547929b9c5eb6ab4anishint npe_disable_empty_bridges_workaround(dev_info_t *child);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnaevoid npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl);
70025d765b044c6d8594bb965a2247a61e991a99johnny * Default ecfga base address
70025d765b044c6d8594bb965a2247a61e991a99johnny * Query the MCFG table using ACPI. If MCFG is found, setup the
70025d765b044c6d8594bb965a2247a61e991a99johnny * 'ecfga-base-address' (Enhanced Configuration Access base address)
70025d765b044c6d8594bb965a2247a61e991a99johnny * property accordingly. Otherwise, set the value of the property
70025d765b044c6d8594bb965a2247a61e991a99johnny * to the default value.
70025d765b044c6d8594bb965a2247a61e991a99johnny /* Query the MCFG table using ACPI */
70025d765b044c6d8594bb965a2247a61e991a99johnny if (AcpiGetFirmwareTable(MCFG_SIG, 1, ACPI_LOGICAL_ADDRESSING,
70025d765b044c6d8594bb965a2247a61e991a99johnny cfg_baap = (CFG_BASE_ADDR_ALLOC *)mcfgp->CfgBaseAddrAllocList;
70025d765b044c6d8594bb965a2247a61e991a99johnny * Setup the 'ecfga-base-address' property to
70025d765b044c6d8594bb965a2247a61e991a99johnny * the base_addr found in the MCFG and return.
70025d765b044c6d8594bb965a2247a61e991a99johnny * If MCFG is not found or ecfga_base is not found in MCFG table,
70025d765b044c6d8594bb965a2247a61e991a99johnny * set the 'ecfga-base-address' property to the default value.
70025d765b044c6d8594bb965a2247a61e991a99johnny * Enable reporting of AER capability next pointer.
70025d765b044c6d8594bb965a2247a61e991a99johnny * This needs to be done only for CK8-04 devices
70025d765b044c6d8594bb965a2247a61e991a99johnny * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13
70025d765b044c6d8594bb965a2247a61e991a99johnny * NOTE: BIOS is disabling this, it needs to be enabled temporarily
2f15eac90d333799a61f99c8b0f11a8524a716b9anish if ((pci_config_get16(cfg_hdl, PCI_CONF_VENID) == NVIDIA_VENDOR_ID) &&
2f15eac90d333799a61f99c8b0f11a8524a716b9anish cya1 = pci_config_get16(cfg_hdl, NVIDIA_CK804_VEND_CYA1_OFF);
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * If the bridge is empty, disable it
7a23d1009aa28ea040052630547929b9c5eb6ab4anishnpe_disable_empty_bridges_workaround(dev_info_t *child)
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * Do not bind drivers to empty bridges.
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * Fail above, if the bridge is found to be hotplug capable
7a23d1009aa28ea040052630547929b9c5eb6ab4anish if (ddi_driver_major(child) == ddi_name_to_major("pcie_pci") &&
7a23d1009aa28ea040052630547929b9c5eb6ab4anish ddi_prop_get_int(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
7a23d1009aa28ea040052630547929b9c5eb6ab4anish "pci-hotplug-type", INBAND_HPC_NONE) == INBAND_HPC_NONE)
7a23d1009aa28ea040052630547929b9c5eb6ab4anish return (1);
7a23d1009aa28ea040052630547929b9c5eb6ab4anish return (0);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae uint16_t dev_id = pci_config_get16(cfg_hdl, PCI_CONF_DEVID);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae if ((vendor_id == NVIDIA_VENDOR_ID) && NVIDIA_PCIE_RC_DEV_ID(dev_id)) {
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae /* Disable ECRC for all devices */
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae regs = pcie_get_aer_uce_mask() | npe_aer_uce_mask |
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae * Turn full scan on since the Error Source ID register may not
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae * have the correct ID.