npe_misc.c revision 49fbdd30212f016ddd49c4b5c997b0b827ff0962
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * CDDL HEADER START
70025d765b044c6d8594bb965a2247a61e991a99johnny *
70025d765b044c6d8594bb965a2247a61e991a99johnny * The contents of this file are subject to the terms of the
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * Common Development and Distribution License (the "License").
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * You may not use this file except in compliance with the License.
70025d765b044c6d8594bb965a2247a61e991a99johnny *
70025d765b044c6d8594bb965a2247a61e991a99johnny * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
70025d765b044c6d8594bb965a2247a61e991a99johnny * or http://www.opensolaris.org/os/licensing.
70025d765b044c6d8594bb965a2247a61e991a99johnny * See the License for the specific language governing permissions
70025d765b044c6d8594bb965a2247a61e991a99johnny * and limitations under the License.
70025d765b044c6d8594bb965a2247a61e991a99johnny *
70025d765b044c6d8594bb965a2247a61e991a99johnny * When distributing Covered Code, include this CDDL HEADER in each
70025d765b044c6d8594bb965a2247a61e991a99johnny * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
70025d765b044c6d8594bb965a2247a61e991a99johnny * If applicable, add the following below this CDDL HEADER, with the
70025d765b044c6d8594bb965a2247a61e991a99johnny * fields enclosed by brackets "[]" replaced with your own identifying
70025d765b044c6d8594bb965a2247a61e991a99johnny * information: Portions Copyright [yyyy] [name of copyright owner]
70025d765b044c6d8594bb965a2247a61e991a99johnny *
70025d765b044c6d8594bb965a2247a61e991a99johnny * CDDL HEADER END
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
70025d765b044c6d8594bb965a2247a61e991a99johnny * Use is subject to license terms.
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Library file that has miscellaneous support for npe(7d)
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny#include <sys/conf.h>
70025d765b044c6d8594bb965a2247a61e991a99johnny#include <sys/pci.h>
70025d765b044c6d8594bb965a2247a61e991a99johnny#include <sys/sunndi.h>
70025d765b044c6d8594bb965a2247a61e991a99johnny#include <sys/acpi/acpi.h>
70025d765b044c6d8594bb965a2247a61e991a99johnny#include <sys/acpi/acpi_pci.h>
70025d765b044c6d8594bb965a2247a61e991a99johnny#include <sys/acpica.h>
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae#include <sys/pci_cap.h>
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae#include <sys/pcie_impl.h>
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#include <sys/x86_archext.h>
8a5a0d1e4394737d73b1496b2cd844056e26c1b4anish#include <io/pciex/pcie_nvidia.h>
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet#include <io/pciex/pcie_nb5000.h>
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Prototype declaration
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnnyvoid npe_query_acpi_mcfg(dev_info_t *dip);
337fc9e235877b459e389f54daf9833bbc645439anishvoid npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
7a23d1009aa28ea040052630547929b9c5eb6ab4anishint npe_disable_empty_bridges_workaround(dev_info_t *child);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnaevoid npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl);
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeetvoid npe_intel_error_mask(ddi_acc_handle_t cfg_hdl);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaurboolean_t npe_is_child_pci(dev_info_t *dip);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaurboolean_t check_and_set_mmcfg(dev_info_t *dip);
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Default ecfga base address
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnnyint64_t npe_default_ecfga_base = 0xE0000000;
70025d765b044c6d8594bb965a2247a61e991a99johnny
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnaeextern uint32_t npe_aer_uce_mask;
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnaeextern boolean_t pcie_full_scan;
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur/* AMD's northbridges vendor-id and device-ids */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_NTBRDIGE_VID 0x1022 /* AMD vendor-id */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_HT_NTBRIDGE_DID 0x1100 /* HT Configuration */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_AM_NTBRIDGE_DID 0x1101 /* Address Map */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_DC_NTBRIDGE_DID 0x1102 /* DRAM Controller */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_MC_NTBRIDGE_DID 0x1103 /* Misc Controller */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_K10_NTBRIDGE_DID_0 0x1200
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_K10_NTBRIDGE_DID_1 0x1201
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_K10_NTBRIDGE_DID_2 0x1202
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_K10_NTBRIDGE_DID_3 0x1203
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_K10_NTBRIDGE_DID_4 0x1204
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur/*
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Check if the given device is an AMD northbridge
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define IS_BAD_AMD_NTBRIDGE(vid, did) \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur (((vid) == AMD_NTBRDIGE_VID) && \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur (((did) == AMD_HT_NTBRIDGE_DID) || \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ((did) == AMD_AM_NTBRIDGE_DID) || \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ((did) == AMD_DC_NTBRIDGE_DID) || \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ((did) == AMD_MC_NTBRIDGE_DID)))
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define IS_K10_AMD_NTBRIDGE(vid, did) \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur (((vid) == AMD_NTBRDIGE_VID) && \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur (((did) == AMD_K10_NTBRIDGE_DID_0) || \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ((did) == AMD_K10_NTBRIDGE_DID_1) || \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ((did) == AMD_K10_NTBRIDGE_DID_2) || \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ((did) == AMD_K10_NTBRIDGE_DID_3) || \
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ((did) == AMD_K10_NTBRIDGE_DID_4)))
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define MSR_AMD_NB_MMIO_CFG_BADDR 0xc0010058
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_MMIO_CFG_BADDR_ADDR_MASK 0xFFFFFFF00000ULL
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_MMIO_CFG_BADDR_ENA_MASK 0x000000000001ULL
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_MMIO_CFG_BADDR_ENA_ON 0x000000000001ULL
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur#define AMD_MMIO_CFG_BADDR_ENA_OFF 0x000000000000ULL
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Query the MCFG table using ACPI. If MCFG is found, setup the
70025d765b044c6d8594bb965a2247a61e991a99johnny * 'ecfga-base-address' (Enhanced Configuration Access base address)
70025d765b044c6d8594bb965a2247a61e991a99johnny * property accordingly. Otherwise, set the value of the property
70025d765b044c6d8594bb965a2247a61e991a99johnny * to the default value.
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnnyvoid
70025d765b044c6d8594bb965a2247a61e991a99johnnynpe_query_acpi_mcfg(dev_info_t *dip)
70025d765b044c6d8594bb965a2247a61e991a99johnny{
70025d765b044c6d8594bb965a2247a61e991a99johnny MCFG_TABLE *mcfgp;
70025d765b044c6d8594bb965a2247a61e991a99johnny CFG_BASE_ADDR_ALLOC *cfg_baap;
70025d765b044c6d8594bb965a2247a61e991a99johnny char *cfg_baa_endp;
70025d765b044c6d8594bb965a2247a61e991a99johnny uint64_t ecfga_base;
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny /* Query the MCFG table using ACPI */
db2bae3047e71d795bde12e3baa621f4b6cc8930Dana Myers if (AcpiGetTable(ACPI_SIG_MCFG, 1, (ACPI_TABLE_HEADER **)&mcfgp) ==
db2bae3047e71d795bde12e3baa621f4b6cc8930Dana Myers AE_OK) {
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny cfg_baap = (CFG_BASE_ADDR_ALLOC *)mcfgp->CfgBaseAddrAllocList;
70025d765b044c6d8594bb965a2247a61e991a99johnny cfg_baa_endp = ((char *)mcfgp) + mcfgp->Length;
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny while ((char *)cfg_baap < cfg_baa_endp) {
db2bae3047e71d795bde12e3baa621f4b6cc8930Dana Myers ecfga_base = cfg_baap->base_addr;
70025d765b044c6d8594bb965a2247a61e991a99johnny if (ecfga_base != (uint64_t)0) {
70025d765b044c6d8594bb965a2247a61e991a99johnny /*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Setup the 'ecfga-base-address' property to
70025d765b044c6d8594bb965a2247a61e991a99johnny * the base_addr found in the MCFG and return.
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnny (void) ndi_prop_update_int64(DDI_DEV_T_NONE,
70025d765b044c6d8594bb965a2247a61e991a99johnny dip, "ecfga-base-address", ecfga_base);
70025d765b044c6d8594bb965a2247a61e991a99johnny return;
70025d765b044c6d8594bb965a2247a61e991a99johnny }
70025d765b044c6d8594bb965a2247a61e991a99johnny cfg_baap++;
70025d765b044c6d8594bb965a2247a61e991a99johnny }
70025d765b044c6d8594bb965a2247a61e991a99johnny }
70025d765b044c6d8594bb965a2247a61e991a99johnny /*
70025d765b044c6d8594bb965a2247a61e991a99johnny * If MCFG is not found or ecfga_base is not found in MCFG table,
70025d765b044c6d8594bb965a2247a61e991a99johnny * set the 'ecfga-base-address' property to the default value.
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnny (void) ndi_prop_update_int64(DDI_DEV_T_NONE, dip,
70025d765b044c6d8594bb965a2247a61e991a99johnny "ecfga-base-address", npe_default_ecfga_base);
70025d765b044c6d8594bb965a2247a61e991a99johnny}
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny
70025d765b044c6d8594bb965a2247a61e991a99johnny/*
70025d765b044c6d8594bb965a2247a61e991a99johnny * Enable reporting of AER capability next pointer.
70025d765b044c6d8594bb965a2247a61e991a99johnny * This needs to be done only for CK8-04 devices
70025d765b044c6d8594bb965a2247a61e991a99johnny * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13
70025d765b044c6d8594bb965a2247a61e991a99johnny * NOTE: BIOS is disabling this, it needs to be enabled temporarily
70025d765b044c6d8594bb965a2247a61e991a99johnny */
70025d765b044c6d8594bb965a2247a61e991a99johnnyvoid
337fc9e235877b459e389f54daf9833bbc645439anishnpe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl)
70025d765b044c6d8594bb965a2247a61e991a99johnny{
337fc9e235877b459e389f54daf9833bbc645439anish ushort_t cya1;
70025d765b044c6d8594bb965a2247a61e991a99johnny
2f15eac90d333799a61f99c8b0f11a8524a716b9anish if ((pci_config_get16(cfg_hdl, PCI_CONF_VENID) == NVIDIA_VENDOR_ID) &&
2f15eac90d333799a61f99c8b0f11a8524a716b9anish (pci_config_get16(cfg_hdl, PCI_CONF_DEVID) ==
2f15eac90d333799a61f99c8b0f11a8524a716b9anish NVIDIA_CK804_DEVICE_ID) &&
2f15eac90d333799a61f99c8b0f11a8524a716b9anish (pci_config_get8(cfg_hdl, PCI_CONF_REVID) >=
2f15eac90d333799a61f99c8b0f11a8524a716b9anish NVIDIA_CK804_AER_VALID_REVID)) {
2f15eac90d333799a61f99c8b0f11a8524a716b9anish cya1 = pci_config_get16(cfg_hdl, NVIDIA_CK804_VEND_CYA1_OFF);
2f15eac90d333799a61f99c8b0f11a8524a716b9anish if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK))
2f15eac90d333799a61f99c8b0f11a8524a716b9anish (void) pci_config_put16(cfg_hdl,
2f15eac90d333799a61f99c8b0f11a8524a716b9anish NVIDIA_CK804_VEND_CYA1_OFF,
2f15eac90d333799a61f99c8b0f11a8524a716b9anish cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL);
2f15eac90d333799a61f99c8b0f11a8524a716b9anish }
70025d765b044c6d8594bb965a2247a61e991a99johnny}
7a23d1009aa28ea040052630547929b9c5eb6ab4anish
7a23d1009aa28ea040052630547929b9c5eb6ab4anish/*
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * If the bridge is empty, disable it
7a23d1009aa28ea040052630547929b9c5eb6ab4anish */
7a23d1009aa28ea040052630547929b9c5eb6ab4anishint
7a23d1009aa28ea040052630547929b9c5eb6ab4anishnpe_disable_empty_bridges_workaround(dev_info_t *child)
7a23d1009aa28ea040052630547929b9c5eb6ab4anish{
7a23d1009aa28ea040052630547929b9c5eb6ab4anish /*
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * Do not bind drivers to empty bridges.
7a23d1009aa28ea040052630547929b9c5eb6ab4anish * Fail above, if the bridge is found to be hotplug capable
7a23d1009aa28ea040052630547929b9c5eb6ab4anish */
7a23d1009aa28ea040052630547929b9c5eb6ab4anish if (ddi_driver_major(child) == ddi_name_to_major("pcie_pci") &&
7a23d1009aa28ea040052630547929b9c5eb6ab4anish ddi_get_child(child) == NULL &&
7a23d1009aa28ea040052630547929b9c5eb6ab4anish ddi_prop_get_int(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
7a23d1009aa28ea040052630547929b9c5eb6ab4anish "pci-hotplug-type", INBAND_HPC_NONE) == INBAND_HPC_NONE)
7a23d1009aa28ea040052630547929b9c5eb6ab4anish return (1);
7a23d1009aa28ea040052630547929b9c5eb6ab4anish
7a23d1009aa28ea040052630547929b9c5eb6ab4anish return (0);
7a23d1009aa28ea040052630547929b9c5eb6ab4anish}
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnaevoid
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnaenpe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl) {
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae uint32_t regs;
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae uint16_t dev_id = pci_config_get16(cfg_hdl, PCI_CONF_DEVID);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae if ((vendor_id == NVIDIA_VENDOR_ID) && NVIDIA_PCIE_RC_DEV_ID(dev_id)) {
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae /* Disable ECRC for all devices */
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae regs = pcie_get_aer_uce_mask() | npe_aer_uce_mask |
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae PCIE_AER_UCE_ECRC;
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae pcie_set_aer_uce_mask(regs);
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae /*
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae * Turn full scan on since the Error Source ID register may not
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae * have the correct ID.
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae */
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae pcie_full_scan = B_TRUE;
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae }
eae2e508a8e70b1ec407b10bd068c080651bbe5ckrishnae}
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeetvoid
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeetnpe_intel_error_mask(ddi_acc_handle_t cfg_hdl) {
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet uint32_t regs;
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet if (vendor_id == INTEL_VENDOR_ID) {
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet /*
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * Due to an errata in Intel's ESB2 southbridge, all ECRCs
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * generation/checking need to be disabled. There is a
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * workaround by setting a proprietary bit in the ESB2, but it
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * is not well documented or understood. If that bit is set in
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * the future, then ECRC generation/checking should be enabled
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * again.
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet *
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * Disable ECRC generation/checking by masking ECRC in the AER
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * UE Mask. The pcie misc module would then automatically
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet * disable ECRC generation/checking in the AER Control register.
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet */
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet regs = pcie_get_aer_uce_mask() | PCIE_AER_UCE_ECRC;
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet pcie_set_aer_uce_mask(regs);
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet }
5c0a55ff7158dbb6220c31dda253139cf9cf5fdeet}
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur/*
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Check's if this child is a PCI device.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Child is a PCI device if:
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * parent has a dev_type of "pci"
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * -and-
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * child does not have a dev_type of "pciex"
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur *
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * If the parent is not of dev_type "pci", then assume it is "pciex" and all
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * children should support using PCIe style MMCFG access.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur *
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * If parent's dev_type is "pci" and child is "pciex", then also enable using
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * PCIe style MMCFG access. This covers the case where NPE is "pci" and a PCIe
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * RP is beneath.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaurboolean_t
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaurnpe_child_is_pci(dev_info_t *dip) {
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur char *dev_type;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur boolean_t parent_is_pci, child_is_pciex;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip),
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur DDI_PROP_DONTPASS, "device_type", &dev_type) ==
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur DDI_PROP_SUCCESS) {
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur parent_is_pci = (strcmp(dev_type, "pci") == 0);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ddi_prop_free(dev_type);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur } else {
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur parent_is_pci = B_FALSE;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur }
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur "device_type", &dev_type) == DDI_PROP_SUCCESS) {
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur child_is_pciex = (strcmp(dev_type, "pciex") == 0);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur ddi_prop_free(dev_type);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur } else {
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur child_is_pciex = B_FALSE;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur }
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur return (parent_is_pci && !child_is_pciex);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur}
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur/*
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Checks to see if MMCFG is supported and enables it if necessary.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Returns: TRUE is MMCFG is support, FLASE is not.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur *
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * In general if a device sits below a parent who's "dev_type" is "pciex" the
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * support MMCFG. Otherwise, default back to legacy IOCFG access.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur *
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Enable Legacy PCI config space access for AMD K8 north bridges.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Host bridge: AMD HyperTransport Technology Configuration
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Host bridge: AMD Address Map
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Host bridge: AMD DRAM Controller
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Host bridge: AMD Miscellaneous Control
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * These devices do not support MMCFG access.
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur *
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur * Enable MMCFG via msr for AMD K10 north bridges
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur */
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaurboolean_t
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaurnpe_check_and_set_mmcfg(dev_info_t *dip)
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur{
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur int vendor_id, device_id;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur int64_t data;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur "vendor-id", -1);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur device_id = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur "device-id", -1);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur if (IS_K10_AMD_NTBRIDGE(vendor_id, device_id)) {
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur data = ddi_prop_get_int64(DDI_DEV_T_ANY, dip, 0,
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur "ecfga-base-address", 0);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur data &= AMD_MMIO_CFG_BADDR_ADDR_MASK;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur data |= AMD_MMIO_CFG_BADDR_ENA_ON;
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur wrmsr(MSR_AMD_NB_MMIO_CFG_BADDR, data);
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur }
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur return !(npe_child_is_pci(dip) ||
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur IS_BAD_AMD_NTBRIDGE(vendor_id, device_id));
49fbdd30212f016ddd49c4b5c997b0b827ff0962Erwin T Tsaur}