npe.c revision eae2e508a8e70b1ec407b10bd068c080651bbe5c
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Host to PCI-Express local bus driver
*/
#include <sys/pci_impl.h>
#include <sys/pcie_impl.h>
#include <sys/sysmacros.h>
#include <sys/ddi_intr.h>
/*
* Bus Operation functions
*/
void *, void *);
ddi_intr_handle_impl_t *, void *);
/*
* Disable URs and Received MA for all PCIe devices. Until x86 SW is changed so
* that random drivers do not do PIO accesses on devices that it does not own,
* these error bits must be disabled. SERR must also be disabled if URs have
* been masked.
*/
uint32_t npe_aer_ce_mask = 0;
struct bus_ops npe_bus_ops = {
NULL,
NULL,
NULL,
0, /* (*bus_get_eventcookie)(); */
0, /* (*bus_add_eventcall)(); */
0, /* (*bus_remove_eventcall)(); */
0, /* (*bus_post_event)(); */
0, /* (*bus_intr_ctl)(); */
0, /* (*bus_config)(); */
0, /* (*bus_unconfig)(); */
npe_fm_init, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
NULL, /* (*bus_fm_access_enter)(); */
NULL, /* (*bus_fm_access_exit)(); */
NULL, /* (*bus_power)(); */
npe_intr_ops /* (*bus_intr_op)(); */
};
/*
* One goal here is to leverage off of the pcihp.c source without making
* changes to it. Call into it's cb_ops directly if needed, piggybacking
* anything else needed by the pci_tools.c module. Only pci_tools and pcihp
* will be using the PCI devctl node.
*/
caddr_t, int *);
struct cb_ops npe_cb_ops = {
npe_open, /* open */
npe_close, /* close */
nodev, /* strategy */
nodev, /* print */
nodev, /* dump */
nodev, /* read */
nodev, /* write */
npe_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
npe_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
/*
* Device Node Operation functions
*/
DEVO_REV, /* devo_rev */
0, /* refcnt */
npe_info, /* info */
nulldev, /* identify */
nulldev, /* probe */
npe_attach, /* attach */
npe_detach, /* detach */
nulldev, /* reset */
&npe_cb_ops, /* driver operations */
&npe_bus_ops /* bus operations */
};
/*
* Internal routines in support of particular npe_ctlops.
*/
/*
* External support routine
*/
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
"Host to PCIe nexus driver %I%",
&npe_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
/* Save minimal state. */
void *npe_statep;
int
_init(void)
{
int e;
/*
* Initialize per-pci bus soft state pointer.
*/
if (e != 0)
return (e);
if ((e = mod_install(&modlinkage)) != 0)
return (e);
}
int
_fini(void)
{
int rc;
if (rc != 0)
return (rc);
return (rc);
}
int
{
}
/*ARGSUSED*/
static int
{
/*
* Use the minor number as constructed by pcihp, as the index value to
* ddi_soft_state_zalloc.
*/
if (cmd == DDI_RESUME)
return (DDI_SUCCESS);
"pciex") != DDI_PROP_SUCCESS) {
}
return (DDI_FAILURE);
/*
* Initialize hotplug support on this bus. At minimum
* (for non hotplug bus) this would create ":devctl" minor
* node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
* to this bus.
*/
return (DDI_FAILURE);
}
/* Second arg: initialize for pci_express root nexus */
(void) pcihp_uninit(devi);
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
static int
{
switch (cmd) {
case DDI_DETACH:
/* Uninitialize pcitool support. */
/*
* Uninitialize hotplug support on this bus.
*/
(void) pcihp_uninit(devi);
return (DDI_SUCCESS);
case DDI_SUSPEND:
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
}
static int
{
int rnumber;
int length;
int space;
int retval;
/*
* check for register number
*/
case DDI_MT_REGSPEC:
return (DDI_FAILURE);
break;
case DDI_MT_RNUMBER:
/*
* get ALL "reg" properties for dip, select the one of
* of interest. In x86, "assigned-addresses" property
* is identical to the "reg" property, so there is no
* need to cross check the two to determine the physical
* address of the registers.
* This routine still performs some validity checks to
* make sure that everything is okay.
*/
return (DDI_FAILURE);
/*
* validate the register number.
*/
length /= (sizeof (pci_regspec_t) / sizeof (int));
return (DDI_FAILURE);
}
/*
* copy the required entry.
*/
/*
* free the memory allocated by ddi_prop_lookup_int_array
*/
return (DDI_FAILURE);
break;
default:
return (DDI_ME_INVAL);
}
/*
* check for unmap and unlock of address space
*/
switch (space) {
case PCI_ADDR_IO:
break;
case PCI_ADDR_CONFIG:
/*
* Check for AMD's northbridges
* AND
* for any PCI device.
*
* This is a workaround fix for
* AMD-8132's inability to handle MMCFG
* accesses on Galaxy's PE servers
* AND
* to disable MMCFG for any PCI device.
*
* If a device is *not* found to have PCIe
* capability, then assume it is a PCI device.
*/
if (is_amd_northbridge(rdip) == 0 ||
DDI_PROP_DONTPASS, "pcie-capid-pointer",
!= DDI_DEFAULT_ACC) {
(void *)mp->map_handlep);
}
return (DDI_SUCCESS);
}
/* FALLTHROUGH */
case PCI_ADDR_MEM64:
/*
* MEM64 requires special treatment on map, to check
* that the device is below 4G. On unmap, however,
* we can assume that everything is OK... the map
* must have succeeded.
*/
/* FALLTHROUGH */
case PCI_ADDR_MEM32:
reg.regspec_bustype = 0;
break;
default:
return (DDI_FAILURE);
}
/*
* Adjust offset and length
* A non-zero length means override the one in the regspec.
*/
if (len != 0)
(void *)mp->map_handlep);
}
return (retval);
}
/* check for user mapping request - not legal for Config */
return (DDI_FAILURE);
}
/*
* Note that pci_fm_acc_setup() is called to serve two purposes
* i) enable legacy PCI I/O style config space access
* ii) register with FMA
*/
if (space == PCI_ADDR_CONFIG) {
/* Can't map config space without a handle */
return (DDI_FAILURE);
/* record the device address for future reference */
/*
* Check for AMD's northbridges, pci devices and
* devices underneath a pci bridge. This is to setup
* I/O based config space access.
*/
if (is_amd_northbridge(rdip) == 0 ||
"pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL) ==
int ret;
DDI_SUCCESS) {
!= DDI_DEFAULT_ACC) {
}
}
return (ret);
}
rdip, 0, "ecfga-base-address", 0);
}
/*
* range check
*/
return (DDI_FAILURE);
/*
* Adjust offset and length
* A non-zero length means override the one in the regspec.
*/
if (len != 0)
/*
* convert the pci regsec into the generic regspec used by the
* parent root nexus driver.
*/
switch (space) {
case PCI_ADDR_IO:
break;
case PCI_ADDR_CONFIG:
case PCI_ADDR_MEM64:
/*
* We can't handle 64-bit devices that are mapped above
* 4G or that are larger than 4G.
*/
return (DDI_FAILURE);
/*
* Other than that, we can treat them as 32-bit mappings
*/
/* FALLTHROUGH */
case PCI_ADDR_MEM32:
reg.regspec_bustype = 0;
break;
default:
return (DDI_FAILURE);
}
if (retval == DDI_SUCCESS) {
/*
* For config space gets force use of cautious access routines.
* These will handle default and protected mode accesses too.
*/
if (space == PCI_ADDR_CONFIG) {
}
}
}
return (retval);
}
/*ARGSUSED*/
static int
{
int rn;
int totreg;
struct attachspec *asp;
struct detachspec *dsp;
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
case DDI_CTLOPS_SIDDEV:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
*(int *)result = 0;
®len) != DDI_PROP_SUCCESS) {
return (DDI_FAILURE);
}
if (ctlop == DDI_CTLOPS_NREGS)
else if (ctlop == DDI_CTLOPS_REGSIZE) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
case DDI_CTLOPS_POWER:
{
/*
* We currently understand reporting of PCI_PM_IDLESPEED
* capability. Everything else is passed up.
*/
return (DDI_SUCCESS);
break;
}
case DDI_CTLOPS_PEEK:
case DDI_CTLOPS_POKE:
/* X86 systems support PME wakeup from suspended state */
case DDI_CTLOPS_ATTACH:
return (DDI_SUCCESS);
(void) pcie_postattach_child(rdip);
}
/* only do this for immediate children */
/* Not good, better stop now. */
"Couldn't pre-resume device %p",
(void *) dip);
/* NOTREACHED */
}
return (DDI_SUCCESS);
case DDI_CTLOPS_DETACH:
return (DDI_SUCCESS);
/* only do this for immediate children */
return (DDI_FAILURE);
return (DDI_SUCCESS);
default:
break;
}
}
/*
* npe_intr_ops
*/
static int
{
}
static int
{
char name[80];
/*
* Do not bind drivers to empty bridges.
* Fail above, if the bridge is found to be hotplug capable
*/
return (DDI_FAILURE);
return (DDI_FAILURE);
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
DDI_SUCCESS) {
/*
* Merged ok - return failure to remove the node.
*/
return (DDI_FAILURE);
}
/* workaround for DDIVS to run under PCI Express */
if (pci_allow_pseudo_children) {
/*
* If the "interrupts" property doesn't exist,
* this must be the ddivs no-intr case, and it returns
* DDI_SUCCESS instead of DDI_FAILURE.
*/
return (DDI_SUCCESS);
/*
* Create the ddi_parent_private_data for a pseudo
* child.
*/
return (DDI_SUCCESS);
}
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
return (DDI_NOT_WELL_FORMED);
}
"interrupts", -1) != -1)
else
/* Disable certain errors on PCIe drivers for x86 platforms */
/*
* If URs are disabled, mask SERRs as well, otherwise the system will
* still be notified of URs
*/
if (npe_aer_uce_mask & PCIE_AER_UCE_UR)
}
if (bus_p) {
/* Disable AER for certain NVIDIA Chipsets */
if ((vendor_id == NVIDIA_VENDOR_ID) &&
(device_id == NVIDIA_CK804_DEVICE_ID) &&
bus_p->bus_aer_off = 0;
(void) pcie_initchild(child);
/* If device is an NVIDIA RC do device specific error setup */
if ((vendor_id == NVIDIA_VENDOR_ID) &&
0x2);
}
}
return (DDI_SUCCESS);
}
static int
{
/*
* Strip the node to properly convert it back to prototype form
*/
return (DDI_SUCCESS);
}
/*
* When retrofitting this module for pci_tools, functions such as open, close,
* and ioctl are now pulled into this module. Before this, the functions in
* the pcihp module were referenced directly. Now they are called or
* referenced through the pcihp cb_ops structure from functions in this module.
*/
static int
{
}
static int
{
}
static int
{
return (ENXIO);
}
static int
{
}
static int
{
}
/*ARGSUSED*/
static int
{
}
/*ARGSUSED*/
static int
{
/*
* On current x86 systems, npe's callback does not get called for failed
* loads. If in the future this feature is used, the fault PA should be
* logged in the derr->fme_bus_specific field. The appropriate PCIe
* error handling code should be called and needs to be coordinated with
* safe access handling.
*/
return (DDI_FM_OK);
}