pciehpc_ck804.h revision 70025d765b044c6d8594bb965a2247a61e991a99
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _PCIEHPC_CK804_H
#define _PCIEHPC_CK804_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/* soft state data structure specific to CK8-04 */
typedef struct pciehpc_ck804 {
#define NVIDIA_VENDOR_ID 0x10de
#define CK804_DEVICE_ID 0x005d
#define CK804_LPC_BRIDGE_DEVID 0x0051
/* register offsets in Analog Control BAR */
#define MCP_NVA_TGIO_CTRL 0xCC
/* vendor specific register NV_XVR_VEND_XP (4 bytes) in PCI config space */
#define NV_XVR_VEND_XP 0xF00
/* bit definitions in NV_XVR_VEND_XP regiser */
#define NV_XVR_VEND_XP_DL_UP 0x40000000
/* bit definitions in NV_XVR_VEND_XP register */
/* bit definitions in Extended Slot Status register */
/* bit definitions in Extended Slot Control register */
/*
* bit definitions for Reference Clock Control (MCP_NVA_TGIO_CTRL)
*
* PE0_REFCLK is for device #E
* PE1_REFCLK is for device #D
* PE2_REFCLK is for device #C
* PE3_REFCLK is for device #B
*/
#define ENABLE_REFCLK 0
#define DISABLE_REFCLK 1
#ifdef __cplusplus
}
#endif
#endif /* _PCIEHPC_CK804_H */