pci_boot.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/pci_impl.h>
#include <sys/pci_cfgspace.h>
#include <sys/bootconf.h>
#include "mps_table.h"
#define pci_getb (*pci_getb_func)
#define pci_getw (*pci_getw_func)
#define pci_getl (*pci_getl_func)
#define pci_putb (*pci_putb_func)
#define pci_putw (*pci_putw_func)
#define pci_putl (*pci_putl_func)
#define CONFIG_INFO 0
#define CONFIG_UPDATE 1
#define CONFIG_NEW 2
extern int pci_bios_nbus;
int pci_boot_debug = 0;
extern struct memlist *find_bus_res(int, int);
/*
* Module prototypes
*/
ushort_t, int);
static void add_bus_range_prop(int);
static void add_ppb_ranges_prop(int);
static void add_bus_available_prop(int);
/*
* Enumerate all PCI devices
*/
void
{
uchar_t i, root_bus_addr = 0;
for (i = 0; i <= pci_bios_nbus; i++) {
pci_bus_res[i].sub_bus = i;
}
/*
* Now enumerate peer busses
*
* We loop till pci_bios_nbus. On most systems, there is
* one more bus at the high end, which implements the ISA
* compatibility bus. We don't care about that.
*
* Note: In the old (bootconf) enumeration, the peer bus
* address did not use the bus number, and there were
* too many peer busses created. The root_bus_addr is
* used to maintain the old peer bus address assignment.
* However, we stop enumerating phantom peers with no
* device below.
*/
for (i = 1; i <= pci_bios_nbus; i++) {
}
}
for (i = 0; i <= pci_bios_nbus; i++) {
}
}
void
pci_reprogram(void)
{
int i, pci_reconfig = 1;
char *onoff;
pci_reconfig = 0;
}
}
for (i = 0; i <= pci_bios_nbus; i++) {
/* configure devices not configured by bios */
if (pci_reconfig)
/* All dev programmed, so we can create available prop */
}
}
/*
* Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
*/
static void
{
int pci_regs[] = {0, 0, 0};
"device_type", "pci");
"#address-cells", 3);
"#size-cells", 2);
(void) ndi_devi_bind_driver(dip, 0);
if (bus != 0)
return;
/*
* Special treatment of bus 0:
* and make io space the entire range. There is no difference
* between prefetchable memory or not.
*/
pci_bus_res[0].mem_space =
}
/*
* For any fixed configuration (often compatability) pci devices
* and those with their own expansion rom, create device nodes
* to hold the already configured device details.
*/
void
{
struct pci_devfunc {
struct pci_devfunc *next;
if (config_op == CONFIG_NEW) {
} else
nfunc = 1;
int configured;
/* no function at this address */
continue;
}
(PCI_COMM_IO | PCI_COMM_MAE);
continue;
if (header == 0xff) {
continue; /* illegal value */
}
/*
* according to some mail from Microsoft posted
* to the pci-drivers alias, their only requirement
* for a multifunction device is for the 1st
* function to have to PCI_HEADER_MULTI bit set.
*/
nfunc = 8;
}
/*
* If dip isn't null, reprogram the device later.
* This only happens for CONFIG_INFO case.
*/
if (dip) {
}
}
}
if (config_op == CONFIG_NEW) {
while (devlist) {
"!reprogram pci device [%d/%d/%d] (%s)",
}
} else {
}
}
static int
{
static int prop_exist = -1;
static char *pciide_str;
char compat[32];
if (prop_exist == -1) {
&pciide_str) == DDI_SUCCESS);
}
if (!prop_exist)
return (0);
/* compare property value against various forms of compatible */
if (subvenid) {
return (1);
return (1);
return (1);
}
return (1);
return (1);
return (0);
}
static int
{
struct ide_table { /* table for PCI_MASS_OTHER */
} *entry;
/* XXX SATA devices: need a way to add dynamically */
{0x1095, 0x3112},
{0x1095, 0x3114},
{0x1095, 0x3512},
{0, 0}
};
if (basecl != PCI_CLASS_MASS)
return (0);
if (subcl == PCI_MASS_IDE) {
return (1);
}
return (0);
}
return (1);
entry++;
}
}
static int
{
static uint_t disp_classes[] = {
0x000100,
0x030000,
0x030001
};
for (i = 0; i < nclasses; i++) {
if (classcode == disp_classes[i])
return (1);
}
return (0);
}
static dev_info_t *
{
switch (header & PCI_HEADER_TYPE_M) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_CARDBUS:
break;
default:
subvenid = 0;
subdevid = 0;
break;
}
/* XXX should be use generic names? derive from class? */
/* figure out if this is pci-ide */
if (pciide)
else if (is_display(classcode))
else if (subvenid != 0)
else
/* make sure parent bus dip has been created */
}
DEVI_SID_NODEID, &dip);
/* add properties */
"class-code", classcode);
if (func == 0)
else
"unit-address", unitaddr);
/* add special stuff for header type */
if (subvenid != 0) {
"subsystem-id", subdevid);
"subsystem-vendor-id", subvenid);
}
"min-grant", mingrant);
"max-latency", maxlatency);
}
/* interrupt, record if not 0 */
if (intr != 0)
"interrupts", intr);
/*
* Add support for 133 mhz pci eventually
*/
if (status & PCI_STAT_FBBC)
"fast-back-to-back");
if (status & PCI_STAT_66MHZ)
"66mhz-capable");
if (status & PCI_STAT_UDF)
"udf-supported");
}
(void) ndi_devi_bind_driver(dip, 0);
/* special handling for pci-ide */
if (pciide) {
/*
* Create properties specified by P1275 Working Group
* Proposal #414 Version 1
*/
"device_type", "pci-ide");
"#address-cells", 1);
"#size-cells", 0);
/* allocate two child nodes */
"reg", 0);
(void) ndi_devi_bind_driver(cdip, 0);
"reg", 1);
(void) ndi_devi_bind_driver(cdip, 0);
reprogram = 0; /* don't reprogram pci-ide bridge */
}
if (reprogram)
return (dip);
return (NULL);
}
/*
* Set the compatible property to a value compliant with
* rev 2.1 of the IEEE1275 PCI binding.
*
* pciVVVV,DDDD.SSSS.ssss.RR (0)
* pciVVVV,DDDD.SSSS.ssss (1)
* pciSSSS,ssss (2)
* pciVVVV,DDDD.RR (3)
* pciVVVV,DDDD (4)
* pciclass,CCSSPP (5)
* pciclass,CCSS (6)
*
* The Subsystem (SSSS) forms are not inserted if
* subsystem-vendor-id is 0.
*
* Set with setprop and \x00 between each
* to generate the encoded string array form.
*/
void
{
int i, size;
char *compat[7];
#define COMPAT_BUFSIZE 256
i = 0;
if (subvenid) {
}
"compatible", compat, i);
}
/*
* Adjust the reg properties for a dual channel PCI-IDE device.
*
* NOTE: don't do anything that changes the order of the hard-decodes
* and programmed BARs. The kernel driver depends on these values
* being in this order regardless of whether they're for a 'native'
* mode BAR or not.
*/
/*
* config info for pci-ide devices
*/
static struct {
} pciide_bar[] = {
{ 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */
{ 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */
{ 0x04, 0, 0x170, 8 }, /* secondary lower BAR */
{ 0x04, 2, 0x376, 1 } /* secondary upper BAR */
};
static int
{
int hard_decode = 0;
/*
* Adjust the base and len for the BARs of the PCI-IDE
* device's primary and secondary controllers. The first
* two BARs are for the primary controller and the next
* two BARs are for the secondary controller. The fifth
* and sixth bars are never adjusted.
*/
} else {
hard_decode = 1;
}
}
/*
* if either base or len is zero make certain both are zero
*/
*basep = 0;
*lenp = 0;
hard_decode = 0;
}
return (hard_decode);
}
/*
* Add the "reg" and "assigned-addresses" property
*/
static int
{
int max_basereg, j, reprogram = 0;
if (bus == 0) /* for bus 0, there is only mem_space */
else
nasgn = 0;
(PCI_COMM_IO | PCI_COMM_MAE);
switch (header) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_PPB:
break;
case PCI_HEADER_CARDBUS:
break;
default:
max_basereg = 0;
break;
}
/*
* Create the register property by saving the current
* write 0xffffffff to the base register. Read the
* value back to determine the required size of the
* address space. Restore the base register
* contents.
*/
int hard_decode = 0;
/* determine the size of the address space */
/* construct phys hi,med.lo, size hi, lo */
/* i/o space */
/* XXX Adjust first 4 IDE registers */
if (pciide) {
if (subclass == PCI_MASS_OTHER)
} else if (value == 0) {
/* skip base regs with size of 0 */
continue;
}
if (!hard_decode) {
} else {
}
/*
* first pass - gather what's there
* config - allocate regions
*/
/* take out of the resource map of the bus */
(void) memlist_remove(io_res,
else if (*io_res)
reprogram = 1;
if (base != 0) {
/* XXX need to worry about 64-bit? */
}
if (base == 0) {
" IO space 0x%x for [%d/%d/%d]",
} else
enable = 1;
}
} else {
/* memory space */
} else {
base_hi = 0;
}
/* skip base regs with size of 0 */
if (value == 0) {
continue;
}
if (base & PCI_BASE_PREF_M) {
} else {
}
if (config_op == CONFIG_INFO) {
/* take out of the resource map of the bus */
(void) memlist_remove(mres,
} else if (*mres)
reprogram = 1;
}
if (base == 0) {
"mem space 0x%x for [%d/%d/%d]",
} else
enable = 1;
}
}
}
switch (header) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_PPB:
break;
default: /* including PCI_HEADER_CARDBUS */
goto done;
}
/*
* Add the expansion rom memory space
* Determine the size of the ROM base reg; don't write reserved bits
* ROM isn't in the PCI memory space.
*/
if (value != 0) {
}
/*
* The following are ISA resources. There are not part
* of the PCI local bus resources. So don't attempt to
* do resource accounting against PCI.
*/
/* add the three hard-decode, aliased address spaces for VGA */
/* VGA hard decode 0x3b0-0x3bb */
/* VGA hard decode 0x3c0-0x3df */
/* Video memory */
}
/* add the hard-decode, aliased address spaces for 8514 */
if ((baseclass == PCI_CLASS_DISPLAY) &&
(subclass == PCI_DISPLAY_VGA) &&
(progclass & PCI_DISPLAY_IF_8514)) {
/* hard decode 0x2e8 */
/* hard decode 0x2ea-0x2ef */
}
done:
"assigned-addresses",
}
return (reprogram);
}
static void
{
int i;
/* setup bus number hierarchy */
"device_type", "pci");
"#address-cells", 3);
"#size-cells", 2);
/* XXX need slot names */
/*
* According to PPB spec, the base register should be programmed
* with a value bigger than the limit register when there are
* no resources available. This applies to io, memory, and
* prefetchable memory.
*/
/* io range */
/* if 32-bit supported, make sure upper bits are not set */
}
}
}
/* mem range */
/* remove from parent resouce list */
}
}
/* prefetchable memory range */
/* if 64-bit supported, make sure upper bits are not set */
}
(uint64_t)pmem_range[0],
(uint64_t)pmem_range[0],
}
}
}
static const struct {
char *desc;
} class_pci[] = {
0, 0, 0, "Unspecified class",
0, 1, 0, "VGA compatible controller",
1, 0, 0, "SCSI bus controller",
1, 1, 0x80, "IDE controller", /* Special case - see below */
1, 2, 0, "Floppy controller",
1, 3, 0, "IPI bus controller",
1, 4, 0, "RAID controller",
1, 5, 0x20, "ATA controller with single DMA",
1, 5, 0x30, "ATA controller with chained DMA",
1, 6, 0, "Serial ATA Direct Port Access (DPA)",
1, 0x80, 0, "Mass storage controller",
1, 0x80, 1, "Mass storage controller",
2, 0, 0, "Ethernet controller",
2, 1, 0, "Token ring controller",
2, 2, 0, "FDDI controller",
2, 3, 0, "ATM controller",
2, 4, 0, "ISDN controller",
2, 5, 0, "WorldFip controller",
2, 6, 0, "PICMG 2.14 Multi computing controller",
2, 0x80, 0, "Network controller",
3, 0, 0, "VGA compatible controller",
3, 0, 1, "8514-compatible display controller",
3, 1, 0, "XGA video controller",
3, 2, 0, "3D controller",
3, 0x80, 0, "Video controller",
4, 0, 0, "Video device",
4, 1, 0, "Audio device",
4, 2, 0, "Computer Telephony device",
4, 0x80, 0, "Multimedia device",
5, 0, 0, "Ram",
5, 1, 0, "Flash memory",
5, 0x80, 0, "Memory controller",
6, 0, 0, "Host bridge",
6, 1, 0, "ISA bridge",
6, 2, 0, "EISA bridge",
6, 3, 0, "MCA bridge",
6, 4, 0, "PCI-PCI bridge",
6, 4, 1, "Subtractive Decode PCI-PCI bridge",
6, 5, 0, "PCMCIA bridge",
6, 6, 0, "NuBus bridge",
6, 7, 0, "CardBus bridge",
6, 8, 0, "RACE-way bridge transport mode",
6, 8, 1, "RACE-way bridge endpoint mode",
6, 9, 0x40, "Semi-transparent PCI-PCI primary bridge",
6, 9, 0x80, "Semi-transparent PCI-PCI secondary bridge",
6, 0xA, 0, "Infiniband-PCI bridge",
6, 0x80, 0, "Bridge device",
7, 0, 0, "Serial controller",
7, 0, 1, "16450-compatible serial controller",
7, 0, 2, "16550-compatible serial controller",
7, 0, 3, "16650-compatible serial controller",
7, 0, 4, "16750-compatible serial controller",
7, 0, 5, "16850-compatible serial controller",
7, 0, 6, "16950-compatible serial controller",
7, 1, 0, "Parallel port",
7, 1, 1, "Bidirectional parallel port",
7, 1, 2, "ECP 1.X parallel port",
7, 1, 3, "IEEE 1284 parallel port",
7, 1, 0xFE, "IEEE 1284 target device",
7, 2, 0, "Multiport serial controller",
7, 3, 0, "Modem controller",
7, 3, 1, "Hayes 16450-compatible modem",
7, 3, 2, "Hayes 16550-compatible modem",
7, 3, 3, "Hayes 16650-compatible modem",
7, 3, 4, "Hayes 16750-compatible modem",
7, 4, 0, "GPIB controller",
7, 5, 0, "Smartcard controller",
7, 0x80, 0, "Communication device",
8, 0, 0, "8259 PIC",
8, 0, 1, "ISA PIC",
8, 0, 2, "EISA PIC",
8, 0, 0x10, "I/O APIC",
8, 0, 0x20, "I/O(x) APIC",
8, 1, 0, "8237 DMA controller",
8, 1, 1, "ISA DMA controller",
8, 1, 2, "EISA DMA controller",
8, 2, 0, "8254 system timer",
8, 2, 1, "ISA system timer",
8, 2, 2, "EISA system timers",
8, 3, 0, "Real time clock",
8, 3, 1, "ISA real time clock",
8, 4, 0, "PCI Hot-Plug controller",
8, 0x80, 0, "System peripheral",
9, 0, 0, "Keyboard controller",
9, 1, 0, "Digitizer (pen)",
9, 2, 0, "Mouse controller",
9, 3, 0, "Scanner controller",
9, 4, 0, "Gameport controller",
9, 4, 1, "Gameport Legacy controller",
9, 0x80, 0, "Input controller",
10, 0, 0, "Generic Docking station",
10, 0x80, 0, "Docking station",
11, 0, 0, "386",
11, 1, 0, "486",
11, 2, 0, "Pentium",
11, 0x10, 0, "Alpha",
11, 0x20, 0, "Power-PC",
11, 0x30, 0, "MIPS",
11, 0x40, 0, "Co-processor",
12, 0, 0, "FireWire (IEEE 1394)",
12, 0, 0x10, "FireWire (IEEE 1394) OpenHCI compliant",
12, 1, 0, "ACCESS.bus",
12, 2, 0, "SSA",
12, 3, 0, "Universal Serial Bus UHCI compliant",
12, 3, 0x10, "Universal Serial Bus OHCI compliant",
12, 3, 0x20, "Universal Serial Bus EHCI compliant",
12, 3, 0x80, "Universal Serial Bus generic HCD",
12, 3, 0xFE, "Universal Serial Bus device",
12, 4, 0, "Fibre Channel",
12, 5, 0, "SMBus (System Management Bus)",
12, 6, 0, "InfiniBand",
12, 7, 0, "IPMI SMIC Interface",
12, 7, 1, "IPMI Keyboard Controller Style Interface",
12, 7, 2, "IPMI Block Transfer Interface",
12, 8, 0, "SERCOS Interface Standard",
12, 9, 0, "CANbus",
13, 0, 0, "IRDA Wireless controller",
13, 1, 0, "Consumer IR Wireless controller",
13, 0x10, 0, "RF Wireless controller",
13, 0x11, 0, "Bluetooth Wireless controller",
13, 0x12, 0, "Broadband Wireless controller",
13, 0x20, 0, "802.11a Wireless controller",
13, 0x21, 0, "802.11b Wireless controller",
13, 0x80, 0, "Wireless controller",
14, 0, 0, "I20 controller",
15, 1, 0, "TV Satellite controller",
15, 2, 0, "Audio Satellite controller",
15, 3, 0, "Voice Satellite controller",
15, 4, 0, "Data Satellite controller",
16, 0, 0, "Network and computing en/decryption",
17, 0, 0, "DPIO modules",
17, 1, 0, "Performance counters",
17, 0x20, 0, "Management card",
};
static void
{
const char *desc;
int i;
desc = "IDE controller";
} else {
for (desc = 0, i = 0; i < class_pci_items; i++) {
break;
}
}
if (i == class_pci_items) {
}
}
(char *)desc);
}
static void
add_bus_range_prop(int bus)
{
int bus_range[2];
return;
}
/* this should be in some header file, shared with pcicfg */
struct pcicfg_range {
};
static int
{
return (0);
/* assume 32-bit addresses */
return (1);
}
static void
add_ppb_ranges_prop(int bus)
{
int i = 0;
struct pcicfg_range *rp;
if (i != 0)
i * sizeof (struct pcicfg_range) / sizeof (int));
}
static int
{
int i = 0;
while (list) {
/* assume 32-bit addresses */
sp->pci_phys_mid = 0;
sp->pci_size_hi = 0;
sp++, i++;
}
return (i);
}
static void
{
int i, count;
struct pci_phys_spec *sp;
if (count == 0) /* nothing available */
return;
"available", (int *)sp,
i * sizeof (struct pci_phys_spec) / sizeof (int));
}