pci_boot.c revision 70025d765b044c6d8594bb965a2247a61e991a99
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/pci_impl.h>
#include <sys/pci_cfgspace.h>
#include <sys/bootconf.h>
#include <sys/pci_cfgspace.h>
#include <sys/pci_cfgspace_impl.h>
#include "../../../../common/pci/pci_strings.h"
#define pci_getb (*pci_getb_func)
#define pci_getw (*pci_getw_func)
#define pci_getl (*pci_getl_func)
#define pci_putb (*pci_putb_func)
#define pci_putw (*pci_putw_func)
#define pci_putl (*pci_putl_func)
#define CONFIG_INFO 0
#define CONFIG_UPDATE 1
#define CONFIG_NEW 2
#define COMPAT_BUFSIZE 512
extern int pci_bios_nbus;
int pci_boot_debug = 0;
extern struct memlist *find_bus_res(int, int);
/*
* Module prototypes
*/
ushort_t, int);
static void add_bus_range_prop(int);
static int pci_slot_names_prop(int, char *, int);
static void add_bus_slot_names_prop(int);
static void add_ppb_ranges_prop(int);
static void add_bus_available_prop(int);
static void alloc_res_array();
/*
* Enumerate all PCI devices
*/
void
{
uchar_t i, root_bus_addr = 0;
for (i = 0; i <= pci_bios_nbus; i++) {
pci_bus_res[i].sub_bus = i;
}
/*
* Now enumerate peer busses
*
* We loop till pci_bios_nbus. On most systems, there is
* one more bus at the high end, which implements the ISA
* compatibility bus. We don't care about that.
*
* Note: In the old (bootconf) enumeration, the peer bus
* address did not use the bus number, and there were
* too many peer busses created. The root_bus_addr is
* used to maintain the old peer bus address assignment.
* However, we stop enumerating phantom peers with no
* device below.
*/
for (i = 1; i <= pci_bios_nbus; i++) {
}
/* add slot-names property for named pci hot-plug slots */
}
for (i = 0; i <= pci_bios_nbus; i++) {
}
}
void
pci_reprogram(void)
{
int i, pci_reconfig = 1;
char *onoff;
pci_reconfig = 0;
}
}
for (i = 0; i <= pci_bios_nbus; i++) {
/* configure devices not configured by bios */
if (pci_reconfig)
/* All dev programmed, so we can create available prop */
}
}
/*
* Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
*/
static void
{
int pci_regs[] = {0, 0, 0};
"#address-cells", 3);
"#size-cells", 2);
/*
* If system has PCIe bus, then create different properties
*/
"device_type", "pci");
(void) ndi_devi_bind_driver(dip, 0);
if (bus != 0)
return;
/*
* Special treatment of bus 0:
* and make io space the entire range. There is no difference
* between prefetchable memory or not.
*/
pci_bus_res[0].mem_space =
}
/*
* For any fixed configuration (often compatability) pci devices
* and those with their own expansion rom, create device nodes
* to hold the already configured device details.
*/
void
{
struct pci_devfunc {
struct pci_devfunc *next;
if (config_op == CONFIG_NEW) {
} else
nfunc = 1;
/* no function at this address */
continue;
}
if (header == 0xff) {
continue; /* illegal value */
}
/*
* according to some mail from Microsoft posted
* to the pci-drivers alias, their only requirement
* for a multifunction device is for the 1st
* function to have to PCI_HEADER_MULTI bit set.
*/
nfunc = 8;
}
if (config_op == CONFIG_INFO) {
/*
* Create the node, unconditionally, on the
* first pass only. It may still need
* resource assignment, which will be
* done on the second, CONFIG_NEW, pass.
*/
/*
* If dip isn't null, put on a list to
* save for reprogramming when config_op
* is CONFIG_NEW.
*/
if (dip) {
KM_SLEEP);
}
}
}
}
if (config_op == CONFIG_NEW) {
while (devlist) {
"!reprogram pci device [%d/%d/%d] (%s)",
}
} else {
}
}
static int
{
static int prop_exist = -1;
static char *pciide_str;
char compat[32];
if (prop_exist == -1) {
&pciide_str) == DDI_SUCCESS);
}
if (!prop_exist)
return (0);
/* compare property value against various forms of compatible */
if (subvenid) {
return (1);
return (1);
return (1);
}
return (1);
return (1);
return (0);
}
static int
{
struct ide_table { /* table for PCI_MASS_OTHER */
} *entry;
/* XXX SATA devices: need a way to add dynamically */
{0x1095, 0x3112},
{0x1095, 0x3114},
{0x1095, 0x3512},
{0, 0}
};
if (basecl != PCI_CLASS_MASS)
return (0);
if (subcl == PCI_MASS_IDE) {
return (1);
}
return (0);
}
return (1);
entry++;
}
}
static int
{
static uint_t disp_classes[] = {
0x000100,
0x030000,
0x030001
};
for (i = 0; i < nclasses; i++) {
if (classcode == disp_classes[i])
return (1);
}
return (0);
}
static dev_info_t *
{
int pciex = 0;
ushort_t is_pci_bridge = 0;
switch (header & PCI_HEADER_TYPE_M) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_CARDBUS:
break;
default:
subvenid = 0;
subdevid = 0;
break;
}
/* XXX should be use generic names? derive from class? */
/* figure out if this is pci-ide */
&is_pci_bridge) == B_TRUE)
pciex = 1;
if (pciide)
else if (is_display(classcode))
else if (subvenid != 0)
else
/* make sure parent bus dip has been created */
}
DEVI_SID_NODEID, &dip);
/* add properties */
"class-code", classcode);
if (func == 0)
else
"unit-address", unitaddr);
/* add device_type for display nodes */
if (is_display(classcode)) {
"device_type", "display");
}
/* add special stuff for header type */
if (subvenid != 0) {
"subsystem-id", subdevid);
"subsystem-vendor-id", subvenid);
}
if (!pciex)
"min-grant", mingrant);
if (!pciex)
"max-latency", maxlatency);
}
/* interrupt, record if not 0 */
if (intr != 0)
"interrupts", intr);
/*
* Add support for 133 mhz pci eventually
*/
"fast-back-to-back");
"66mhz-capable");
if (status & PCI_STAT_UDF)
"udf-supported");
"physical-slot#", slot_num);
/* check for ck8-04 based PCI ISA bridge only */
(func == 0))
if (pciex && is_pci_bridge)
(char *)"PCIe-PCI bridge");
else
(void) ndi_devi_bind_driver(dip, 0);
/* special handling for pci-ide */
if (pciide) {
/*
* Create properties specified by P1275 Working Group
* Proposal #414 Version 1
*/
"device_type", "pci-ide");
"#address-cells", 1);
"#size-cells", 0);
/* allocate two child nodes */
"reg", 0);
(void) ndi_devi_bind_driver(cdip, 0);
"reg", 1);
(void) ndi_devi_bind_driver(cdip, 0);
reprogram = 0; /* don't reprogram pci-ide bridge */
}
if (reprogram)
return (dip);
return (NULL);
}
/*
* Set the compatible property to a value compliant with
* rev 2.1 of the IEEE1275 PCI binding.
* (Also used for PCI-Express devices).
*
* pciVVVV,DDDD.SSSS.ssss.RR (0)
* pciVVVV,DDDD.SSSS.ssss (1)
* pciSSSS,ssss (2)
* pciVVVV,DDDD.RR (3)
* pciVVVV,DDDD (4)
* pciclass,CCSSPP (5)
* pciclass,CCSS (6)
*
* The Subsystem (SSSS) forms are not inserted if
* subsystem-vendor-id is 0.
*
* NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
* property 2 is not created as per "1275 bindings for PCI Express Interconnect"
*
* Set with setprop and \x00 between each
* to generate the encoded string array form.
*/
void
int pciex)
{
int i = 0;
int size = COMPAT_BUFSIZE;
char *compat[13];
if (pciex) {
if (subvenid) {
}
(classcode >> 8));
}
if (subvenid) {
}
"compatible", compat, i);
}
/*
* Adjust the reg properties for a dual channel PCI-IDE device.
*
* NOTE: don't do anything that changes the order of the hard-decodes
* and programmed BARs. The kernel driver depends on these values
* being in this order regardless of whether they're for a 'native'
* mode BAR or not.
*/
/*
* config info for pci-ide devices
*/
static struct {
} pciide_bar[] = {
{ 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */
{ 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */
{ 0x04, 0, 0x170, 8 }, /* secondary lower BAR */
{ 0x04, 2, 0x376, 1 } /* secondary upper BAR */
};
static int
{
int hard_decode = 0;
/*
* Adjust the base and len for the BARs of the PCI-IDE
* device's primary and secondary controllers. The first
* two BARs are for the primary controller and the next
* two BARs are for the secondary controller. The fifth
* and sixth bars are never adjusted.
*/
} else {
hard_decode = 1;
}
}
/*
* if either base or len is zero make certain both are zero
*/
*basep = 0;
*lenp = 0;
hard_decode = 0;
}
return (hard_decode);
}
/*
* Add the "reg" and "assigned-addresses" property
*/
static int
{
int max_basereg, j, reprogram = 0;
if (bus == 0) /* for bus 0, there is only mem_space */
else
nasgn = 0;
/* Fetch PCI command, disable I/O and memory */
switch (header) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_PPB:
break;
case PCI_HEADER_CARDBUS:
break;
default:
max_basereg = 0;
break;
}
/*
* Create the register property by saving the current
* write 0xffffffff to the base register. Read the
* value back to determine the required size of the
* address space. Restore the base register
* contents.
*/
int hard_decode = 0;
/* determine the size of the address space */
/* construct phys hi,med.lo, size hi, lo */
/* i/o space */
/* XXX Adjust first 4 IDE registers */
if (pciide) {
if (subclass != PCI_MASS_IDE)
} else if (value == 0) {
/* skip base regs with size of 0 */
continue;
}
if (!hard_decode) {
} else {
}
/*
* first pass - gather what's there
* config - allocate regions
*/
/* take out of the resource map of the bus */
(void) memlist_remove(io_res,
else if (*io_res)
reprogram = 1;
if (base != 0) {
/* XXX need to worry about 64-bit? */
}
if (base == 0) {
" IO space [%d/%d/%d] BAR@0x%x"
" length 0x%x",
} else
enable |= PCI_COMM_IO;
}
} else {
/* memory space */
} else {
base_hi = 0;
}
/* skip base regs with size of 0 */
if (value == 0) {
continue;
}
if (base & PCI_BASE_PREF_M) {
} else {
}
if (config_op == CONFIG_INFO) {
/* take out of the resource map of the bus */
(void) memlist_remove(mres,
} else if (*mres)
reprogram = 1;
}
if (base == 0) {
"mem space [%d/%d/%d] BAR@0x%x"
" length 0x%x",
} else
enable |= PCI_COMM_MAE;
}
}
}
switch (header) {
case PCI_HEADER_ZERO:
break;
case PCI_HEADER_PPB:
break;
default: /* including PCI_HEADER_CARDBUS */
goto done;
}
/*
* Add the expansion rom memory space
* Determine the size of the ROM base reg; don't write reserved bits
* ROM isn't in the PCI memory space.
*/
if (value & PCI_BASE_ROM_ENABLE)
else
value = 0;
if (value != 0) {
/* take it out of the memory resource */
(void) memlist_remove(mem_res,
}
/*
* The following are ISA resources. There are not part
* of the PCI local bus resources. So don't attempt to
* do resource accounting against PCI.
*/
/* add the three hard-decode, aliased address spaces for VGA */
/* VGA hard decode 0x3b0-0x3bb */
/* VGA hard decode 0x3c0-0x3df */
/* Video memory */
}
/* add the hard-decode, aliased address spaces for 8514 */
if ((baseclass == PCI_CLASS_DISPLAY) &&
(subclass == PCI_DISPLAY_VGA) &&
(progclass & PCI_DISPLAY_IF_8514)) {
/* hard decode 0x2e8 */
/* hard decode 0x2ea-0x2ef */
}
done:
"assigned-addresses",
}
/* restore device enables */
return (reprogram);
}
static void
int pciex)
{
char *dev_type;
int i;
/*
* Some BIOSes lie about max pci busses, we allow for
* such mistakes here
*/
if (subbus > pci_bios_nbus) {
}
/* setup bus number hierarchy */
"device_type", dev_type);
"#address-cells", 3);
"#size-cells", 2);
/*
* According to PPB spec, the base register should be programmed
* with a value bigger than the limit register when there are
* no resources available. This applies to io, memory, and
* prefetchable memory.
*/
/* io range */
}
/* if 32-bit supported, make sure upper bits are not set */
}
}
/* mem range */
/* remove from parent resouce list */
}
}
/* prefetchable memory range */
(uint64_t)pmem_range[0],
(uint64_t)pmem_range[0],
}
/* if 64-bit supported, make sure upper bits are not set */
}
}
}
extern const struct pci_class_strings_s class_pci[];
extern int class_pci_items;
static void
{
const char *desc;
int i;
desc = "IDE controller";
} else {
for (desc = 0, i = 0; i < class_pci_items; i++) {
break;
}
}
if (i == class_pci_items)
}
(char *)desc);
}
static void
add_bus_range_prop(int bus)
{
int bus_range[2];
return;
}
/*
* pci irq routing information table
*/
static int pci_irq_nroutes;
static pci_irq_route_t *pci_irq_routes;
/*
* Issue the bios get irq routing information table interrupt
*
* Despite the name, the information in the table is only
* used to derive slot names for some named pci hot-plug slots.
*
* Returns the number of irq routing table entries returned
* by the bios, or 0 and optionally, the number of entries required.
*/
static int
{
int i, n;
int rval = 0;
if (nneededp)
*nneededp = 0;
/*
* Set up irq routing header with the size and address
* of some useable low-memory data addresses. Initalize
*/
n = nroutes * sizeof (pci_irq_route_t);
for (i = 0; i < n; i++)
bufp[i] = 0;
sizeof (pci_irq_route_t));
if (nneededp)
*nneededp = n;
} else {
/*
* Copy resulting irq routing data from low memory up to
* the kernel address space, avoiding memcpy as usual.
*/
if (n <= nroutes) {
for (i = 0; i < n * sizeof (pci_irq_route_t); i++)
rval = n;
}
}
return (rval);
}
static void
{
int n = N_PCI_IRQ_ROUTES;
int nneeded = 0;
int nroutes;
/*
* Get irq routing table information.
* Allocate a buffer for an initial default number of entries.
* If the bios indicates it needs a larger buffer, try it again.
* Drive on if it still won't cooperate and play nice after that.
*/
if (nneeded > N_PCI_IRQ_ROUTES_MAX) {
"pci: unable to get IRQ routing information, "
"required buffer space of %d entries exceeds max\n",
nneeded);
return;
}
n = nneeded;
if (nroutes == 0) {
"pci: unable to get IRQ routing information, "
"required buffer space for %d entries\n", n);
}
}
if (nroutes > 0) {
}
}
/*
* Use the results of the PCI BIOS call that returned the routing tables
* to build the 1275 slot-names property for the indicated bus.
* Results are returned in buf. Length is return value, -1 is returned on
* overflow and zero is returned if no data exists to build a property.
*/
static int
{
if (pci_irq_nroutes == 0)
return (0);
nnames = 0;
mask = 0;
for (i = 0; i < pci_irq_nroutes; i++)
slot[i] = 0xff;
for (i = 0; i < pci_irq_nroutes; i++) {
continue;
if (pci_irq_routes[i].pir_slot != 0) {
nnames++;
}
}
if (nnames == 0)
return (0);
return (-1);
plen = 4;
for (i = 0; i < pci_irq_nroutes; i++) {
if (slot[i] == 0xff)
continue;
}
return (plen);
}
/*
* Add slot-names property for any named pci hot-plug slots
*/
static void
{
char slotprop[256];
int len;
if (len > 0) {
}
}
/* this should be in some header file, shared with pcicfg */
struct pcicfg_range {
};
static int
{
return (0);
/* assume 32-bit addresses */
return (1);
}
static void
add_ppb_ranges_prop(int bus)
{
int i = 0;
struct pcicfg_range *rp;
if (i != 0)
i * sizeof (struct pcicfg_range) / sizeof (int));
}
static int
{
int i = 0;
while (list) {
/* assume 32-bit addresses */
sp->pci_phys_mid = 0;
sp->pci_size_hi = 0;
sp++, i++;
}
return (i);
}
static void
{
int i, count;
struct pci_phys_spec *sp;
if (count == 0) /* nothing available */
return;
"available", (int *)sp,
i * sizeof (struct pci_phys_spec) / sizeof (int));
}
static void
alloc_res_array(void)
{
static int array_max = 0;
int old_max;
void *old_res;
return; /* array is big enough */
if (array_max == 0)
array_max <<= 1;
if (old_res) { /* copy content and free old array */
old_max * sizeof (struct pci_bus_resource));
}
}