pci.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Host to PCI local bus driver
*/
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/ddi_subrdefs.h>
#include <sys/pci_impl.h>
#include <sys/pci_cfgspace.h>
#include <sys/pci_intr_lib.h>
#include <sys/pci_tools.h>
#include <sys/pci_tools_var.h>
#include "pci_var.h"
/* Save minimal state. */
void *pci_statep;
/*
* Bus Operation functions
*/
void *, void *);
ddi_intr_handle_impl_t *, void *);
static int pci_get_priority(dev_info_t *, int, int *);
static int pci_get_nintrs(dev_info_t *, int, int *);
/* Extern decalrations */
psm_intr_op_t, int *);
struct bus_ops pci_bus_ops = {
NULL,
NULL,
NULL,
0, /* (*bus_get_eventcookie)(); */
0, /* (*bus_add_eventcall)(); */
0, /* (*bus_remove_eventcall)(); */
0, /* (*bus_post_event)(); */
0, /* (*bus_intr_ctl)(); */
0, /* (*bus_config)(); */
0, /* (*bus_unconfig)(); */
NULL, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
NULL, /* (*bus_fm_access_enter)(); */
NULL, /* (*bus_fm_access_exit)(); */
NULL, /* (*bus_power)(); */
pci_intr_ops /* (*bus_intr_op)(); */
};
int *rvalp);
/*
* One goal here is to leverage off of the pcihp.c source without making
* changes to it. Call into it's cb_ops directly if needed, piggybacking
* anything else needed by the pci_tools.c module. Only pci_tools and pcihp
* will be using the PCI devctl node.
*/
struct cb_ops pci_cb_ops = {
pci_open, /* open */
pci_close, /* close */
nodev, /* strategy */
nodev, /* print */
nodev, /* dump */
nodev, /* read */
nodev, /* write */
pci_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
pci_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
/*
* Device Node Operation functions
*/
void **result);
DEVO_REV, /* devo_rev */
0, /* refcnt */
pci_info, /* info */
nulldev, /* identify */
nulldev, /* probe */
pci_attach, /* attach */
pci_detach, /* detach */
nulldev, /* reset */
&pci_cb_ops, /* driver operations */
&pci_bus_ops /* bus operations */
};
/*
* Internal routines in support of particular pci_ctlops.
*/
/*
* Miscellaneous internal function
*/
/*
* These are the access routines. The pci_bus_map sets the handle
* to point to these.
*/
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
"host to PCI nexus driver %I%",
&pci_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
int
_init(void)
{
int e;
/*
* Initialize per-pci bus soft state pointer.
*/
if (e != 0)
return (e);
if ((e = mod_install(&modlinkage)) != 0)
return (e);
}
int
_fini(void)
{
int rc;
if (rc != 0)
return (rc);
return (rc);
}
int
{
}
/*ARGSUSED*/
static int
{
/*
* Use the minor number as constructed by pcihp, as the index value to
* ddi_soft_state_zalloc.
*/
!= DDI_PROP_SUCCESS) {
}
}
return (DDI_FAILURE);
}
/*
* Initialize hotplug support on this bus. At minimum
* (for non hotplug bus) this would create ":devctl" minor
* node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
* to this bus.
*/
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
static int
{
/*
* Uninitialize hotplug support on this bus.
*/
(void) pcihp_uninit(devi);
return (DDI_SUCCESS);
}
static int
{
int assigned_addr_len;
int i;
int rc;
int number;
(phys_hi & PCI_RELOCAT_B))
return (DDI_SUCCESS);
/*
* the "reg" property specifies relocatable, get and interpret the
* "assigned-addresses" property.
*/
DDI_PROP_DONTPASS, "assigned-addresses",
if (rc != DDI_PROP_SUCCESS)
return (DDI_FAILURE);
/*
* Scan the "assigned-addresses" for one that matches the specified
* "reg" property entry.
*/
for (i = 0; i < number; i++) {
phys_hi) {
return (DDI_SUCCESS);
}
}
return (DDI_FAILURE);
}
static int
{
int rnumber;
int length;
int rc;
int space;
/*
* check for register number
*/
case DDI_MT_REGSPEC:
return (DDI_FAILURE);
break;
case DDI_MT_RNUMBER:
/*
* get ALL "reg" properties for dip, select the one of
* of interest. In x86, "assigned-addresses" property
* is identical to the "reg" property, so there is no
* need to cross check the two to determine the physical
* address of the registers.
* This routine still performs some validity checks to
* make sure that everything is okay.
*/
if (rc != DDI_PROP_SUCCESS) {
return (DDI_FAILURE);
}
/*
* validate the register number.
*/
length /= (sizeof (pci_regspec_t) / sizeof (int));
return (DDI_FAILURE);
}
/*
* copy the required entry.
*/
/*
* free the memory allocated by ddi_prop_lookup_int_array
*/
return (DDI_FAILURE);
break;
default:
return (DDI_ME_INVAL);
}
/*
* check for unmap and unlock of address space
*/
/*
* Adjust offset and length
* A non-zero length means override the one in the regspec.
*/
if (len != 0)
switch (space) {
case PCI_ADDR_CONFIG:
/* No work required on unmap of Config space */
return (DDI_SUCCESS);
case PCI_ADDR_IO:
break;
case PCI_ADDR_MEM64:
/*
* MEM64 requires special treatment on map, to check
* that the device is below 4G. On unmap, however,
* we can assume that everything is OK... the map
* must have succeeded.
*/
/* FALLTHROUGH */
case PCI_ADDR_MEM32:
reg.regspec_bustype = 0;
break;
default:
return (DDI_FAILURE);
}
}
/* check for user mapping request - not legal for Config */
return (DDI_FAILURE);
}
/*
* check for config space
* On x86, CONFIG is not mapped via MMU and there is
* no endian-ness issues. Set the attr field in the handle to
* indicate that the common routines to call the nexus driver.
*/
if (space == PCI_ADDR_CONFIG) {
/* Can't map config space without a handle */
return (DDI_FAILURE);
}
/* endian-ness check */
return (DDI_FAILURE);
/*
* range check
*/
return (DDI_FAILURE);
/* record the device address for future reference */
return (DDI_SUCCESS);
}
/*
* range check
*/
return (DDI_FAILURE);
}
/*
* Adjust offset and length
* A non-zero length means override the one in the regspec.
*/
if (len != 0)
/*
* convert the pci regsec into the generic regspec used by the
* parent root nexus driver.
*/
switch (space) {
case PCI_ADDR_IO:
break;
case PCI_ADDR_MEM64:
/*
* We can't handle 64-bit devices that are mapped above
* 4G or that are larger than 4G.
*/
if (pci_rp->pci_phys_mid != 0 ||
pci_rp->pci_size_hi != 0)
return (DDI_FAILURE);
/*
* Other than that, we can treat them as 32-bit mappings
*/
/* FALLTHROUGH */
case PCI_ADDR_MEM32:
reg.regspec_bustype = 0;
break;
default:
return (DDI_FAILURE);
}
}
/*
* pci_get_priority:
* Figure out the priority of the device
*/
static int
{
(void *)dip));
NULL)
return (DDI_FAILURE);
return (DDI_SUCCESS);
}
/*
* pci_get_nintrs:
* Figure out how many interrupts the device supports
*/
static int
{
int ret;
*nintrs = 0;
if (DDI_INTR_IS_MSI_OR_MSIX(type))
else {
ret = DDI_FAILURE;
"interrupts", -1) != -1) {
*nintrs = 1;
ret = DDI_SUCCESS;
}
}
return (ret);
}
/*
* pci_intr_ops: bus_intr_op() function for interrupt support
*/
/* ARGSUSED */
static int
{
int priority = 0;
int psm_status = 0;
int pci_status = 0;
int types = 0;
int i, j;
int behavior;
"pci_intr_ops: pdip 0x%p, rdip 0x%p, op %x handle 0x%p\n",
/* Process the request */
switch (intr_op) {
/* Fixed supported by default */
*(int *)result = DDI_INTR_TYPE_FIXED;
/* Figure out if MSI or MSI-X is supported? */
return (DDI_SUCCESS);
if (psm_intr_ops != NULL) {
/* MSI or MSI-X is supported, OR it in */
"supported types: 0x%x\n", (void *)rdip,
*(int *)result));
}
break;
case DDI_INTROP_NINTRS:
return (DDI_FAILURE);
break;
case DDI_INTROP_ALLOC:
/*
* MSI or MSIX (figure out number of vectors available)
* FIXED interrupts: just return available interrupts
*/
(psm_intr_ops != NULL) &&
&priority) == DDI_SUCCESS)) {
/* verify behavior flag and take appropriate action */
if ((behavior == DDI_INTR_ALLOC_STRICT) &&
"behavior %x, couldn't get enough intrs\n",
behavior));
return (DDI_EAGAIN);
}
if (msix_p)
msix_p);
}
}
/* Figure out if this device supports MASKING */
} else
return (DDI_FAILURE);
break;
case DDI_INTROP_FREE:
(psm_intr_ops != NULL)) {
if (msix_p &&
--msix_p->msix_intrs_in_use == 0) {
}
}
}
break;
case DDI_INTROP_GETPRI:
DDI_SUCCESS) /* Get the priority */
return (DDI_FAILURE);
priority));
break;
case DDI_INTROP_SETPRI:
/* Validate the interrupt priority passed */
if (*(int *)result > LOCK_LEVEL)
return (DDI_FAILURE);
/* Ensure that PSM is all initialized */
if (psm_intr_ops == NULL)
return (DDI_FAILURE);
/* Change the priority */
return (DDI_FAILURE);
/* update ispec */
break;
case DDI_INTROP_ADDISR:
/* update ispec */
break;
case DDI_INTROP_REMISR:
/* Get the interrupt structure pointer */
break;
case DDI_INTROP_GETCAP:
/*
* MSI capability register(s)
*/
&pci_status);
/* next check with pcplusmp */
if (psm_intr_ops != NULL)
"psm_status = %x, pci_rval = %x, pci_status = %x\n",
*(int *)result = 0;
return (DDI_FAILURE);
}
if (psm_rval == PSM_SUCCESS)
*(int *)result = psm_status;
if (pci_rval == DDI_SUCCESS)
*(int *)result |= pci_status;
*(int *)result));
break;
case DDI_INTROP_SETCAP:
*(int *)result));
if (psm_intr_ops == NULL)
return (DDI_FAILURE);
" returned failure\n"));
return (DDI_FAILURE);
}
break;
case DDI_INTROP_ENABLE:
if (psm_intr_ops == NULL)
return (DDI_FAILURE);
return (DDI_FAILURE);
break;
case DDI_INTROP_DISABLE:
if (psm_intr_ops == NULL)
return (DDI_FAILURE);
break;
case DDI_INTROP_BLOCKENABLE:
return (DDI_FAILURE);
}
/* Check if psm_intr_ops is NULL? */
if (psm_intr_ops == NULL)
return (DDI_FAILURE);
for (i = 0; i < hdlp->ih_scratch1; i++) {
"pci_enable_intr failed for %d\n", i));
for (j = 0; j < i; j++)
return (DDI_FAILURE);
}
}
break;
case DDI_INTROP_BLOCKDISABLE:
return (DDI_FAILURE);
}
/* Check if psm_intr_ops is present */
if (psm_intr_ops == NULL)
return (DDI_FAILURE);
for (i = 0; i < hdlp->ih_scratch1; i++) {
}
break;
case DDI_INTROP_SETMASK:
case DDI_INTROP_CLRMASK:
/*
* First handle in the config space
*/
if (intr_op == DDI_INTROP_SETMASK) {
} else {
}
/* For MSI/X; no need to check with pcplusmp */
return (pci_status);
/* For fixed interrupts only: handle config space first */
break;
/* For fixed interrupts only: confer with pcplusmp next */
if (psm_intr_ops != NULL) {
/* If interrupt is shared; do nothing */
return (pci_status);
if (intr_op == DDI_INTROP_SETMASK)
else
}
case DDI_INTROP_GETPENDING:
/*
* MSI capability register(s)
*/
/* On failure; next try with pcplusmp */
"psm_rval = %x, psm_status = %x, pci_rval = %x, "
pci_status));
*(int *)result = 0;
return (DDI_FAILURE);
}
if (psm_rval != PSM_FAILURE)
*(int *)result = psm_status;
else if (pci_rval != DDI_FAILURE)
*(int *)result = pci_status;
*(int *)result));
break;
case DDI_INTROP_NAVAIL:
/* Priority in the handle not initialized yet */
} else {
*(int *)result = 1;
}
*(int *)result));
break;
default:
}
return (DDI_SUCCESS);
}
static int
{
int vector;
/* Translate the interrupt if needed */
/* translate the interrupt if needed */
/* Add the interrupt handler */
return (DDI_FAILURE);
return (DDI_SUCCESS);
}
static void
{
int vector;
/* translate the interrupt if needed */
/* Disable the interrupt handler */
}
/*ARGSUSED*/
static int
{
int rn;
int totreg;
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
case DDI_CTLOPS_NINTRS:
if (ddi_get_parent_data(rdip))
*(int *)result = 1;
else
*(int *)result = 0;
return (DDI_SUCCESS);
case DDI_CTLOPS_XLATE_INTRS:
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
*(int *)result = 0;
®len) != DDI_PROP_SUCCESS) {
return (DDI_FAILURE);
}
if (ctlop == DDI_CTLOPS_NREGS)
else if (ctlop == DDI_CTLOPS_REGSIZE) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
case DDI_CTLOPS_POWER: {
/*
* We currently understand reporting of PCI_PM_IDLESPEED
* capability. Everything else is passed up.
*/
return (DDI_SUCCESS);
}
}
default:
}
/* NOTREACHED */
}
/*
* Assign the address portion of the node name
*/
static int
{
char **unit_addr;
uint_t n;
if (ndi_dev_is_persistent_node(child) == 0) {
/*
* For .conf node, use "unit-address" property
*/
"cannot find unit-address in %s.conf",
return (DDI_FAILURE);
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
return (DDI_FAILURE);
}
/* copy the device identifications */
/*
* free the memory allocated by ddi_prop_lookup_int_array
*/
if (func != 0) {
} else {
}
return (DDI_SUCCESS);
}
static int
{
struct ddi_parent_private_data *pdptr;
char name[80];
return (DDI_FAILURE);
}
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
/*
* Merged ok - return failure to remove the node.
*/
return (DDI_FAILURE);
}
/* workaround for ddivs to run under PCI */
if (pci_allow_pseudo_children) {
/*
* If the "interrupts" property doesn't exist,
* this must be the ddivs no-intr case, and it returns
* DDI_SUCCESS instead of DDI_FAILURE.
*/
return (DDI_SUCCESS);
/*
* Create the ddi_parent_private_data for a pseudo
* child.
*/
(sizeof (struct ddi_parent_private_data) +
return (DDI_SUCCESS);
}
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
return (DDI_NOT_WELL_FORMED);
}
"interrupts", -1) != -1) {
pdptr = (struct ddi_parent_private_data *)
kmem_zalloc((sizeof (struct ddi_parent_private_data) +
} else
return (DDI_SUCCESS);
}
static int
{
struct ddi_parent_private_data *pdptr;
}
/*
* Strip the node to properly convert it back to prototype form
*/
return (DDI_SUCCESS);
}
/*
* These are the get and put functions to be shared with drivers. The
* mutex locking is done inside the functions referenced, rather than
* here, and is thus shared across PCI child drivers and any other
* consumers of PCI config space (such as the ACPI subsystem).
*
* The configuration space addresses come in as pointers. This is fine on
* a 32-bit system, where the VM space and configuration space are the same
* size. It's not such a good idea on a 64-bit system, where memory
* addresses are twice as large as configuration space addresses. At some
* point in the call tree we need to take a stand and say "you are 32-bit
* from this time forth", and this seems like a nice self-contained place.
*/
static uint8_t
{
int reg;
reg);
return (rval);
}
static void
{
uint8_t *h, *d;
h = host_addr;
d = dev_addr;
if (flags == DDI_DEV_AUTOINCR)
*h++ = pci_config_rd8(hdlp, d++);
else
*h++ = pci_config_rd8(hdlp, d);
}
static uint16_t
{
int reg;
reg);
return (rval);
}
static void
{
uint16_t *h, *d;
h = host_addr;
d = dev_addr;
if (flags == DDI_DEV_AUTOINCR)
*h++ = pci_config_rd16(hdlp, d++);
else
*h++ = pci_config_rd16(hdlp, d);
}
static uint32_t
{
int reg;
return (rval);
}
static void
{
uint32_t *h, *d;
h = host_addr;
d = dev_addr;
if (flags == DDI_DEV_AUTOINCR)
*h++ = pci_config_rd32(hdlp, d++);
else
*h++ = pci_config_rd32(hdlp, d);
}
static void
{
int reg;
}
static void
{
uint8_t *h, *d;
h = host_addr;
d = dev_addr;
if (flags == DDI_DEV_AUTOINCR)
pci_config_wr8(hdlp, d++, *h++);
else
pci_config_wr8(hdlp, d, *h++);
}
static void
{
int reg;
}
static void
{
uint16_t *h, *d;
h = host_addr;
d = dev_addr;
if (flags == DDI_DEV_AUTOINCR)
pci_config_wr16(hdlp, d++, *h++);
else
pci_config_wr16(hdlp, d, *h++);
}
static void
{
int reg;
}
static void
{
uint32_t *h, *d;
h = host_addr;
d = dev_addr;
if (flags == DDI_DEV_AUTOINCR)
pci_config_wr32(hdlp, d++, *h++);
else
pci_config_wr32(hdlp, d, *h++);
}
static uint64_t
{
dp++;
return (val);
}
static void
{
dp++;
}
static void
{
if (flags == DDI_DEV_AUTOINCR) {
} else {
}
}
static void
{
if (flags == DDI_DEV_AUTOINCR) {
} else {
}
}
/*
* When retrofitting this module for pci_tools, functions such as open, close,
* and ioctl are now pulled into this module. Before this, the functions in
* the pcihp module were referenced directly. Now they are called or
* referenced through the pcihp cb_ops structure from functions in this module.
*/
static int
{
}
static int
{
}
static int
int *rvalp)
{
}
/*
* PCI tools.
*/
switch (cmd) {
case PCITOOL_DEVICE_SET_REG:
case PCITOOL_DEVICE_GET_REG:
/* Require full privileges. */
if (secpolicy_kmdb(credp))
else
break;
case PCITOOL_NEXUS_SET_REG:
case PCITOOL_NEXUS_GET_REG:
/* Require full privileges. */
if (secpolicy_kmdb(credp))
else
break;
case PCITOOL_DEVICE_SET_INTR:
/* Require PRIV_SYS_RES_CONFIG */
if (secpolicy_ponline(credp)) {
break;
}
/*FALLTHRU*/
/* These require no special privileges. */
case PCITOOL_DEVICE_GET_INTR:
case PCITOOL_DEVICE_NUM_INTR:
break;
default:
break;
}
}
return (rv);
}
static int
{
}
static int
{
}