intel_nhm.h revision e3d60c9bd991a9826cbfa63b10595d44e123b9c4
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _INTEL_NHM_H
#define _INTEL_NHM_H
#ifdef __cplusplus
extern "C" {
#endif
#define NHM_CPU 0x2c408086
#define MAX_CPU_NODES 2
#define CPU_PCI_DEVS 6
#define CPU_PCI_FUNCS 6
#define MAX_BUS_NUMBER max_bus_number
#define MC_CONTROL_RD(cpu) \
#define MC_STATUS_RD(cpu) \
#define MC_SMI_SPARE_DIMM_ERROR_STATUS_RD(cpu) \
#define MC_SCRUB_CONTROL_RD(cpu) \
0x4c, reg);
#define MC_RAS_STATUS_RD(cpu) \
reg);
0x4c, 0)
0x60, 0)
#define MC_DIMM_CLK_RATIO_STATUS(cpu) \
/*
* MC_CONTROL
*/
/*
* MC_STATUS
*/
/*
* MC_CHANNEL_DIMM_INIT_PARAMS
*/
/*
* MC_DOD_CH
*/
#define DIMMWIDTH 8
/*
* MC_SAG_CH
*/
#define CH_ADDRESS_OFFSET(reg) \
/*
* MC_RIR_LIMIT_CH
*/
/*
* MC_RIR_WAY_CH
*/
#define MAX_RIR_WAY 4
/*
* MC_RAS_ENABLES
*/
/*
* MC_RAS_STATUS
*/
/*
* MC_SSRSTATUS
*/
/*
* MC_SSR_CONTROL
*/
#define SSR_IDLE 0
#define SSR_SCRUB 1
#define SSR_SPARE 2
/*
* MC_SCRUB_CONTROL
*/
/*
* MC_DIMM_CLK_RATIO_STATUS
*/
/*
* MC_SMI_SPARE_DIMM_ERROR_STATUS_RD
*/
#define MAX_MEMORY_CONTROLLERS MAX_CPU_NODES
#define CHANNELS_PER_MEMORY_CONTROLLER 3
#define MAX_DIMMS_PER_CHANNEL 3
/*
* SAD_DRAM_RULE
*/
#define INTERLEAVE_NWAY 8
#define MAX_SAD_DRAM_RULE 8
/*
* TAD_DRAM_RULE
*/
#define MAX_TAD_DRAM_RULE 8
#define VRANK_SZ 0x40000000
/*
* MC_CHANNEL_MAPPER
*/
extern int max_bus_number;
#ifdef __cplusplus
}
#endif
#endif /* _INTEL_NHM_H */