intel_nbdrv.c revision 20c794b39650d115e17a15983b6b82e46238cf45
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/mc_intel.h>
#include "nb_log.h"
#include "nb5000.h"
char _depends_on[] = "drv/smbios";
char *inb_mc_snapshot;
static dev_info_t *inb_dip;
int nb_allow_detach = 0;
static uint64_t
{
uint8_t i, j;
uint64_t h = 0;
uint8_t branch_interleave = 0;
for (i = 0; i < NB_MEM_RANK_SELECT; i++) {
for (j = 0; j < NB_RANKS_IN_SELECT; j++) {
way = j;
i = NB_MEM_RANK_SELECT;
break;
}
}
}
if (lt == 0) {
for (i = 0; lt == 0 && i < NB_MEM_BRANCH_SELECT; i++) {
break;
}
}
}
*interleave = il;
*hole_base = h;
return (base);
}
void
{
int i;
if (hole_size) {
}
limit);
if (interleave > 1) {
(void) nvlist_add_uint32(newrank[i],
(void) nvlist_add_uint32(newrank[i],
if (branch_interleave) {
(void) nvlist_add_uint32(newrank[i],
}
}
}
}
nvlist_t *
{
uint8_t t;
char sbuf[65];
} else {
}
/* create Sun Serial number from SPD data */
t = sizeof (nb_dimm->part_number);
sbuf[t] = 0;
}
sbuf[t] = 0;
}
sbuf[t] = 0;
return (newdimm);
}
static void
{
int nd;
uint8_t i, j;
KM_SLEEP);
for (i = 0; i < nchannels; i++) {
nd = 0;
for (j = 0; j < nb_dimms_per_channel; j++) {
nd++;
}
dimmpp++;
}
if (nd) {
(void) nvlist_add_nvlist_array(newchannel[i],
for (j = 0; j < nd; j++)
nvlist_free(dimmlist[j]);
}
}
}
static char *
{
char *mc;
switch (nb_chipset) {
case INTEL_NB_7300:
mc = "Intel 7300";
break;
case INTEL_NB_5000P:
mc = "Intel 5000P";
break;
case INTEL_NB_5000V:
mc = "Intel 5000V";
break;
case INTEL_NB_5000X:
mc = "Intel 5000X";
break;
case INTEL_NB_5000Z:
mc = "Intel 5000Z";
break;
default:
mc = "Intel 5000";
break;
}
return (mc);
}
static void
{
if (inb_mc_nvl)
inb_mc_nvl = nvl;
}
static void
{
if (inb_mc_snapshot == NULL)
return;
inb_mc_snapshotsz = 0;
}
static int
{
if (inb_mc_snapshot != NULL)
return (0);
NV_ENCODE_XDR, KM_SLEEP) != 0)
return (-1);
return (0);
}
/*ARGSUSED*/
static int
int *rvalp)
{
int rc = 0;
return (EINVAL);
if (!rw_tryupgrade(&inb_mc_lock)) {
return (EAGAIN);
}
if (inb_mc_nvl)
(void) inb_mc_snapshot_update();
}
switch (cmd) {
case MC_IOC_SNAPSHOT_INFO:
mode) < 0)
break;
case MC_IOC_SNAPSHOT:
mode) < 0)
break;
}
return (rc);
}
/*ARGSUSED*/
static int
void **result)
{
if ((infocmd != DDI_INFO_DEVT2DEVINFO &&
return (DDI_FAILURE);
}
if (infocmd == DDI_INFO_DEVT2DEVINFO)
else
return (0);
}
static int
{
if (cmd == DDI_RESUME) {
return (DDI_SUCCESS);
}
if (cmd != DDI_ATTACH)
return (DDI_FAILURE);
inb_mc_name());
if (nb_dev_init()) {
return (DDI_FAILURE);
}
"ddi_mem_ctrl", 0) != DDI_SUCCESS) {
" for memory controller\n");
}
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
static int
{
return (DDI_SUCCESS);
return (DDI_SUCCESS);
} else {
return (DDI_FAILURE);
}
}
/*ARGSUSED*/
static int
{
return (EINVAL);
return (EINVAL);
}
return (0);
}
/*ARGSUSED*/
static int
{
return (0);
}
static struct cb_ops inb_mc_cb_ops = {
nodev, /* not a block driver */
nodev, /* no print routine */
nodev, /* no dump routine */
nodev, /* no read routine */
nodev, /* no write routine */
nodev, /* no devmap routine */
nodev, /* no mmap routine */
nodev, /* no segmap routine */
nochpoll, /* no chpoll routine */
0, /* not a STREAMS driver */
};
static struct dev_ops inb_mc_ops = {
DEVO_REV, /* devo_rev */
0, /* devo_refcnt */
inb_mc_getinfo, /* devo_getinfo */
nulldev, /* devo_identify */
nulldev, /* devo_probe */
inb_mc_attach, /* devo_attach */
inb_mc_detach, /* devo_detach */
nodev, /* devo_reset */
&inb_mc_cb_ops, /* devo_cb_ops */
NULL, /* devo_bus_ops */
NULL /* devo_power */
};
"Intel 5000 Memory Controller Hub Module",
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
int
_init(void)
{
int err;
return (err);
}
int
{
}
int
_fini(void)
{
int err;
nb_unload();
}
return (err);
}