authamd_main.c revision a4e4e13f4001644f2f960e3be0056c22b3a40fd1
20c794b39650d115e17a15983b6b82e46238cf45gavinm * CDDL HEADER START
20c794b39650d115e17a15983b6b82e46238cf45gavinm * The contents of this file are subject to the terms of the
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Common Development and Distribution License (the "License").
20c794b39650d115e17a15983b6b82e46238cf45gavinm * You may not use this file except in compliance with the License.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
20c794b39650d115e17a15983b6b82e46238cf45gavinm * See the License for the specific language governing permissions
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and limitations under the License.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * When distributing Covered Code, include this CDDL HEADER in each
20c794b39650d115e17a15983b6b82e46238cf45gavinm * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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20c794b39650d115e17a15983b6b82e46238cf45gavinm * CDDL HEADER END
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Use is subject to license terms.
20c794b39650d115e17a15983b6b82e46238cf45gavinm#pragma ident "%Z%%M% %I% %E% SMI"
20c794b39650d115e17a15983b6b82e46238cf45gavinm * "Generic AMD" model-specific support. If no more-specific support can
20c794b39650d115e17a15983b6b82e46238cf45gavinm * be found, or such modules declines to initialize, then for AuthenticAMD
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cpus this module can have a crack at providing some AMD model-specific
20c794b39650d115e17a15983b6b82e46238cf45gavinm * support that at least goes beyond common MCA architectural features
20c794b39650d115e17a15983b6b82e46238cf45gavinm * if not down to the nitty-gritty level for a particular model. We
20c794b39650d115e17a15983b6b82e46238cf45gavinm * are layered on top of a cpu module, likely cpu.generic, so there is no
20c794b39650d115e17a15983b6b82e46238cf45gavinm * need for us to perform common architecturally-accessible functions.
20c794b39650d115e17a15983b6b82e46238cf45gavinm (X86_CHIPREV_AMD_F_REV_B | X86_CHIPREV_AMD_F_REV_C0 | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm X86_CHIPREV_AMD_F_REV_CG | X86_CHIPREV_AMD_F_REV_D | \
20c794b39650d115e17a15983b6b82e46238cf45gavinm (X86_CHIPREV_AMD_10_REV_A | X86_CHIPREV_AMD_10_REV_B)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Bitmasks of support for various features. Try to enable features
20c794b39650d115e17a15983b6b82e46238cf45gavinm * via inclusion in one of these bitmasks and check that at the
20c794b39650d115e17a15983b6b82e46238cf45gavinm * feature imlementation - that way new family support may often simply
20c794b39650d115e17a15983b6b82e46238cf45gavinm * simply need to update these bitmasks.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Families that this module will provide some model-specific
20c794b39650d115e17a15983b6b82e46238cf45gavinm * support for (if no more-specific module claims it first).
20c794b39650d115e17a15983b6b82e46238cf45gavinm * We try to support whole families rather than differentiate down
20c794b39650d115e17a15983b6b82e46238cf45gavinm * to revision.
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((fam) == AUTHAMD_FAMILY_6 || (fam) == AUTHAMD_FAMILY_F || \
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm * Models that include an on-chip NorthBridge.
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_B) || \
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Families/revisions for which we can recognise main memory ECC errors.
20c794b39650d115e17a15983b6b82e46238cf45gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_B) || \
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Families/revisions that have an Online Spare Control Register
20c794b39650d115e17a15983b6b82e46238cf45gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F) || \
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Families/revisions for which we will perform NB MCA Config changes
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_B) || \
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Families/revisions that have chip cache scrubbers.
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_B) || \
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Families/revisions that have a NB misc register or registers -
20c794b39650d115e17a15983b6b82e46238cf45gavinm * evaluates to 0 if no support, otherwise the number of MC4_MISCj.
20c794b39650d115e17a15983b6b82e46238cf45gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F)? 1 : \
20c794b39650d115e17a15983b6b82e46238cf45gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A) ? 3 : 0))
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Families/revision for which we wish not to machine check for GART
20c794b39650d115e17a15983b6b82e46238cf45gavinm * table walk errors - bit 10 of NB CTL.
20c794b39650d115e17a15983b6b82e46238cf45gavinm (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_B) || \
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Families/revisions that are potentially L3 capable
20c794b39650d115e17a15983b6b82e46238cf45gavinm * We recognise main memory ECC errors for AUTHAMD_MEMECC_RECOGNISED
20c794b39650d115e17a15983b6b82e46238cf45gavinm * revisions as:
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - being reported by the NB
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - being a compound bus/interconnect error (external to chip)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - having LL of LG
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - having II of MEM (but could still be a master/target abort)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - having CECC or UECC set
20c794b39650d115e17a15983b6b82e46238cf45gavinm * We do not check the extended error code (first nibble of the
20c794b39650d115e17a15983b6b82e46238cf45gavinm * model-specific error code on AMD) since this has changed from
20c794b39650d115e17a15983b6b82e46238cf45gavinm * family 0xf to family 0x10 (ext code 0 now reserved on family 0x10).
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Instead we use CECC/UECC to separate off the master/target
20c794b39650d115e17a15983b6b82e46238cf45gavinm * abort cases.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * We insist that the detector be the NorthBridge bank; although
20c794b39650d115e17a15983b6b82e46238cf45gavinm * IC/DC can report some main memory errors, they do not capture
20c794b39650d115e17a15983b6b82e46238cf45gavinm * an address at sufficient resolution to be useful and the NB will
20c794b39650d115e17a15983b6b82e46238cf45gavinm * report most errors.
20c794b39650d115e17a15983b6b82e46238cf45gavinm MCAX86_ERRCODE_ISBUS_INTERCONNECT(MCAX86_ERRCODE(status)) && \
20c794b39650d115e17a15983b6b82e46238cf45gavinm MCAX86_ERRCODE_LL(MCAX86_ERRCODE(status)) == MCAX86_ERRCODE_LL_LG && \
20c794b39650d115e17a15983b6b82e46238cf45gavinm MCAX86_ERRCODE_II(MCAX86_ERRCODE(status)) == MCAX86_ERRCODE_II_MEM && \
20c794b39650d115e17a15983b6b82e46238cf45gavinm ((status) & (AMD_BANK_STAT_CECC | AMD_BANK_STAT_UECC)))
20c794b39650d115e17a15983b6b82e46238cf45gavinm * We recognise GART walk errors as:
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - being reported by the NB
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - being a compound TLB error
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - having LL of LG and TT of GEN
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - having UC set
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - possibly having PCC set (if source CPU)
20c794b39650d115e17a15983b6b82e46238cf45gavinm MCAX86_ERRCODE_LL(MCAX86_ERRCODE(status)) == MCAX86_ERRCODE_LL_LG && \
20c794b39650d115e17a15983b6b82e46238cf45gavinm MCAX86_ERRCODE_TT(MCAX86_ERRCODE(status)) == MCAX86_ERRCODE_TT_GEN && \
20c794b39650d115e17a15983b6b82e46238cf45gavinm FM_EREPORT_CPU_GENADM_GARTTBLWLK, /* use generic leafclass */
20c794b39650d115e17a15983b6b82e46238cf45gavinm 0 /* no additional payload */
20c794b39650d115e17a15983b6b82e46238cf45gavinmstatic struct authamd_chipshared *authamd_shared[AUTHAMD_MAX_CHIPS];
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_chip_once(authamd_data_t *authamd, enum authamd_cfgonce_bitnum what)
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (atomic_set_long_excl(&authamd->amd_shared->acs_cfgonce,
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_pcicfg_write(uint_t chipid, uint_t func, uint_t reg, uint32_t val)
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_pcicfg_read(uint_t chipid, uint_t func, uint_t reg)
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (cmi_pci_getl(0, chipid + 24, func, reg, 0, 0));
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_bankstatus_prewrite(cmi_hdl_t hdl, authamd_data_t *authamd)
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (cmi_hdl_rdmsr(hdl, MSR_AMD_HWCR, &hwcr) != CMI_SUCCESS)
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_bankstatus_postwrite(cmi_hdl_t hdl, authamd_data_t *authamd)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Read EccCnt repeatedly for all possible channel/chip-select combos:
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - read sparectl register
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - if EccErrCntWrEn is set, clear that bit in the just-read value
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and write it back to sparectl; this *may* clobber the EccCnt
20c794b39650d115e17a15983b6b82e46238cf45gavinm * for the channel/chip-select combination currently selected, so
20c794b39650d115e17a15983b6b82e46238cf45gavinm * we leave this bit clear if we had to clear it
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - cycle through all channel/chip-select combinations writing each
20c794b39650d115e17a15983b6b82e46238cf45gavinm * combination to sparectl before reading the register back for
20c794b39650d115e17a15983b6b82e46238cf45gavinm * EccCnt for that combination; since EccErrCntWrEn is clear
20c794b39650d115e17a15983b6b82e46238cf45gavinm * the writes to select what count to read will not themselves
20c794b39650d115e17a15983b6b82e46238cf45gavinm * zero any counts
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_read_ecccnt(authamd_data_t *authamd, struct authamd_logout *msl)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Check for feature support; this macro will test down to the
20c794b39650d115e17a15983b6b82e46238cf45gavinm * family revision number, whereafter we'll switch on family
20c794b39650d115e17a15983b6b82e46238cf45gavinm * assuming that future revisions will use the same register
20c794b39650d115e17a15983b6b82e46238cf45gavinm bzero(&msl->aal_eccerrcnt, sizeof (msl->aal_eccerrcnt));
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (0);
20c794b39650d115e17a15983b6b82e46238cf45gavinm authamd_pcicfg_read(chipid, MC_FUNC_MISCCTL, MC_CTL_REG_SPARECTL);
20c794b39650d115e17a15983b6b82e46238cf45gavinm for (chan = 0; chan < AUTHAMD_DRAM_NCHANNEL; chan++) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (1);
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Clear EccCnt for all possible channel/chip-select combos:
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - set EccErrCntWrEn in sparectl, if necessary
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - write 0 to EccCnt for all channel/chip-select combinations
20c794b39650d115e17a15983b6b82e46238cf45gavinm * - clear EccErrCntWrEn
20c794b39650d115e17a15983b6b82e46238cf45gavinm * If requested also disable the interrupts taken on counter overflow
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and on swap done.
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_clear_ecccnt(authamd_data_t *authamd, boolean_t clrint)
20c794b39650d115e17a15983b6b82e46238cf45gavinm authamd_pcicfg_read(chipid, MC_FUNC_MISCCTL, MC_CTL_REG_SPARECTL);
20c794b39650d115e17a15983b6b82e46238cf45gavinm for (chan = 0; chan < AUTHAMD_DRAM_NCHANNEL; chan++) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_init entry point.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * This module provides broad model-specific support for AMD families
20c794b39650d115e17a15983b6b82e46238cf45gavinm * 0x6, 0xf and 0x10. Future families will have to be evaluated once their
20c794b39650d115e17a15983b6b82e46238cf45gavinm * documentation is available.
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (authamd_ms_support_disable || !AUTHAMD_SUPPORTED(family))
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS)
20c794b39650d115e17a15983b6b82e46238cf45gavinm authamd = *datap = kmem_zalloc(sizeof (authamd_data_t), KM_SLEEP);
20c794b39650d115e17a15983b6b82e46238cf45gavinm sp = kmem_zalloc(sizeof (struct authamd_chipshared), KM_SLEEP);
20c794b39650d115e17a15983b6b82e46238cf45gavinm osp = atomic_cas_ptr(&authamd_shared[chipid], NULL, sp);
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (0);
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_logout_size entry point.
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (sizeof (struct authamd_logout));
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_mcgctl_val entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Instead of setting all bits to 1 we can set just those for the
20c794b39650d115e17a15983b6b82e46238cf45gavinm * error detector banks known to exist.
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_mcgctl_val(cmi_hdl_t hdl, int nbanks, uint64_t proposed)
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (nbanks < 64 ? (1ULL << nbanks) - 1 : proposed);
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_bankctl_skipinit entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinm * On K6 we do not initialize MC0_CTL since, reportedly, this bank (for DC)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * may produce spurious machine checks.
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm * Only allow a single core to setup the NorthBridge MCi_CTL register.
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm if (authamd->amd_shared->acs_family == AUTHAMD_FAMILY_6)
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm if (AUTHAMD_NBONCHIP(rev) && bank == AMD_MCA_BANK_NB) {
a4e4e13f4001644f2f960e3be0056c22b3a40fd1gavinm return (authamd_chip_once(authamd, AUTHAMD_CFGONCE_NBMCA) ==
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_bankctl_val entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_bankctl_val(cmi_hdl_t hdl, int bank, uint64_t proposed)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * The Intel MCA says we can write all 1's to enable #MC for
20c794b39650d115e17a15983b6b82e46238cf45gavinm * all errors, and AMD docs say much the same. But, depending
20c794b39650d115e17a15983b6b82e46238cf45gavinm * perhaps on other config registers, taking machine checks
20c794b39650d115e17a15983b6b82e46238cf45gavinm * for some errors such as GART TLB errors and master/target
20c794b39650d115e17a15983b6b82e46238cf45gavinm * aborts may be bad - they set UC and sometime also PCC, but
20c794b39650d115e17a15983b6b82e46238cf45gavinm * we should not always panic for these error types.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Our cms_error_action entry point can suppress such panics,
20c794b39650d115e17a15983b6b82e46238cf45gavinm * however we can also use the cms_bankctl_val entry point to
20c794b39650d115e17a15983b6b82e46238cf45gavinm * veto enabling of some of the known villains in the first place.
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (bank == AMD_MCA_BANK_NB && AUTHAMD_NOGARTTBLWLK_MC(rev))
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Bits to add to NB MCA config (after watchdog config).
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Bits to remove from NB MCA config (after watchdog config)
25f476773dea2a0ee593dcf662a38d5f02487196gavinmuint32_t authamd_nb_mcacfg_remove = AMD_NB_CFG_REMOVE_CMN;
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * NB Watchdog policy, and rate we use if enabling.
25f476773dea2a0ee593dcf662a38d5f02487196gavinm} authamd_nb_watchdog_policy = AUTHAMD_NB_WDOG_ENABLE_IF_DISABLED;
25f476773dea2a0ee593dcf662a38d5f02487196gavinmuint32_t authamd_nb_mcacfg_wdog = AMD_NB_CFG_WDOGTMRCNTSEL_4095 |
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Per-core cache scrubbing policy and rates.
25f476773dea2a0ee593dcf662a38d5f02487196gavinm AUTHAMD_SCRUB_BIOSDEFAULT, /* leave as BIOS configured */
25f476773dea2a0ee593dcf662a38d5f02487196gavinm AUTHAMD_SCRUB_MAX /* use higher of ours and BIOS rate */
25f476773dea2a0ee593dcf662a38d5f02487196gavinmuint32_t authamd_scrub_rate_dcache = 0xf; /* 64K per 0.67 seconds */
25f476773dea2a0ee593dcf662a38d5f02487196gavinmuint32_t authamd_scrub_rate_l2cache = 0xe; /* 1MB per 5.3 seconds */
25f476773dea2a0ee593dcf662a38d5f02487196gavinmuint32_t authamd_scrub_rate_l3cache = 0xd; /* 1MB per 2.7 seconds */
25f476773dea2a0ee593dcf662a38d5f02487196gavinmauthamd_scrubrate(uint32_t osrate, uint32_t biosrate, const char *varnm)
25f476773dea2a0ee593dcf662a38d5f02487196gavinm cmn_err(CE_WARN, "%s is too large, resetting to 0x%x\n",
25f476773dea2a0ee593dcf662a38d5f02487196gavinm cmn_err(CE_WARN, "Unknown authamd_scrub_policy %d - "
25f476773dea2a0ee593dcf662a38d5f02487196gavinm "using default policy of AUTHAMD_SCRUB_MAX",
25f476773dea2a0ee593dcf662a38d5f02487196gavinm /*FALLTHRU*/
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_mca_init entry point.
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinm * On chips with a NB online spare control register take control
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and clear ECC counts.
20c794b39650d115e17a15983b6b82e46238cf45gavinm authamd_chip_once(authamd, AUTHAMD_CFGONCE_ONLNSPRCFG)) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm * And since we are claiming the telemetry stop the BIOS receiving
20c794b39650d115e17a15983b6b82e46238cf45gavinm * an SMI on NB threshold overflow.
20c794b39650d115e17a15983b6b82e46238cf45gavinm authamd_chip_once(authamd, AUTHAMD_CFGONCE_NBTHRESH)) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F) &&
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * NB MCA Configuration Register.
25f476773dea2a0ee593dcf662a38d5f02487196gavinm authamd_chip_once(authamd, AUTHAMD_CFGONCE_NBMCACFG)) {
25f476773dea2a0ee593dcf662a38d5f02487196gavinm uint32_t val = authamd_pcicfg_read(chipid, MC_FUNC_MISCCTL,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm "unrecognised, using default policy",
25f476773dea2a0ee593dcf662a38d5f02487196gavinm /*FALLTHRU*/
25f476773dea2a0ee593dcf662a38d5f02487196gavinm break; /* if enabled leave rate intact */
25f476773dea2a0ee593dcf662a38d5f02487196gavinm /*FALLTHRU*/
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Bit 0 of the NB MCA Config register is reserved on family
25f476773dea2a0ee593dcf662a38d5f02487196gavinm if (X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_10_REV_A))
25f476773dea2a0ee593dcf662a38d5f02487196gavinm authamd_pcicfg_write(chipid, MC_FUNC_MISCCTL, MC_CTL_REG_NBCFG,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * Cache scrubbing. We can't enable DRAM scrubbing since
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * we don't know the DRAM base for this node.
25f476773dea2a0ee593dcf662a38d5f02487196gavinm authamd_chip_once(authamd, AUTHAMD_CFGONCE_CACHESCRUB)) {
25f476773dea2a0ee593dcf662a38d5f02487196gavinm uint32_t val = authamd_pcicfg_read(chipid, MC_FUNC_MISCCTL,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm l3cap = (authamd_pcicfg_read(chipid, MC_FUNC_MISCCTL,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm (val & AMD_NB_SCRUBCTL_DC_MASK) >> AMD_NB_SCRUBCTL_DC_SHIFT,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm "authamd_scrub_rate_dcache");
25f476773dea2a0ee593dcf662a38d5f02487196gavinm (val & AMD_NB_SCRUBCTL_L2_MASK) >> AMD_NB_SCRUBCTL_L2_SHIFT,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm "authamd_scrub_rate_l2cache");
25f476773dea2a0ee593dcf662a38d5f02487196gavinm (val & AMD_NB_SCRUBCTL_L3_MASK) >> AMD_NB_SCRUBCTL_L3_SHIFT,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm "authamd_scrub_rate_l3cache") : 0;
25f476773dea2a0ee593dcf662a38d5f02487196gavinm authamd_scrub_rate_dcache, authamd_scrub_rate_l2cache,
25f476773dea2a0ee593dcf662a38d5f02487196gavinm * cms_poll_ownermask entry point.
25f476773dea2a0ee593dcf662a38d5f02487196gavinmauthamd_poll_ownermask(cmi_hdl_t hdl, hrtime_t pintvl)
25f476773dea2a0ee593dcf662a38d5f02487196gavinm struct authamd_chipshared *acsp = authamd->amd_shared;
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_bank_logout entry point.
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_bank_logout(cmi_hdl_t hdl, int bank, uint64_t status,
20c794b39650d115e17a15983b6b82e46238cf45gavinm * For main memory ECC errors on revisions with an Online Spare
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Control Register grab the ECC counts by channel and chip-select
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and reset them to 0.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_error_action entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinmint authamd_forgive_pcc = 0; /* For test/debug only */
20c794b39650d115e17a15983b6b82e46238cf45gavinmint authamd_fake_poison = 0; /* For test/debug only */
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_error_action(cmi_hdl_t hdl, int ismc, int bank,
20c794b39650d115e17a15983b6b82e46238cf45gavinm uint64_t status, uint64_t addr, uint64_t misc, void *mslogout)
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (authamd_fake_poison && status & MSR_MC_STATUS_UC)
20c794b39650d115e17a15983b6b82e46238cf45gavinm disp = authamd_disp_match(hdl, bank, status, addr, misc, mslogout);
20c794b39650d115e17a15983b6b82e46238cf45gavinm * GART walk errors set UC and possibly PCC (if source CPU)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * but should not be regarded as terminal.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * May also want to consider master abort and target abort. These
20c794b39650d115e17a15983b6b82e46238cf45gavinm * also set UC and PCC (if src CPU) but the requester gets -1
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and I believe the IO stuff in Solaris will handle that.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_disp_match entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_disp_match(cmi_hdl_t hdl, int bank, uint64_t status,
20c794b39650d115e17a15983b6b82e46238cf45gavinm /* uint16_t errcode = MCAX86_ERRCODE(status); */
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Recognise main memory ECC errors
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Recognise GART walk errors
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (AUTHAMD_NOGARTTBLWLK_MC(rev) && AUTHAMD_IS_GARTERR(bank, status))
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_ereport_class entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_ereport_class(cmi_hdl_t hdl, cms_cookie_t mscookie,
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_ereport_add_resource(cmi_hdl_t hdl, authamd_data_t *authamd,
20c794b39650d115e17a15983b6b82e46238cf45gavinm nvlist_t *elems[AUTHAMD_DRAM_NCHANNEL * AUTHAMD_DRAM_NCS];
20c794b39650d115e17a15983b6b82e46238cf45gavinm uint8_t counts[AUTHAMD_DRAM_NCHANNEL * AUTHAMD_DRAM_NCS];
20c794b39650d115e17a15983b6b82e46238cf45gavinm for (chan = 0; chan < AUTHAMD_DRAM_NCHANNEL; chan++) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_fmri_hc_set(nvl, FM_HC_SCHEME_VERSION, NULL, NULL, 5,
20c794b39650d115e17a15983b6b82e46238cf45gavinm "motherboard", 0,
20c794b39650d115e17a15983b6b82e46238cf45gavinm "memory-controller", 0,
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_payload_set(ereport, FM_EREPORT_GENAMD_PAYLOAD_NAME_RESOURCE,
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_payload_set(ereport, FM_EREPORT_GENAMD_PAYLOAD_NAME_RESOURCECNT,
20c794b39650d115e17a15983b6b82e46238cf45gavinm for (i = 0; i < nelems; i++)
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_nvlist_destroy(elems[i], nva ? FM_NVA_RETAIN : FM_NVA_FREE);
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_ereport_add_logout entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_ereport_add_logout(cmi_hdl_t hdl, nvlist_t *ereport, nv_alloc_t *nva,
20c794b39650d115e17a15983b6b82e46238cf45gavinm int bank, uint64_t status, uint64_t addr, uint64_t misc,
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_payload_set(ereport, FM_EREPORT_GENAMD_PAYLOAD_NAME_SYND,
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (members & FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYNDTYPE) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (members & FM_EREPORT_GENAMD_PAYLOAD_FLAG_CKSYND) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_payload_set(ereport, FM_EREPORT_GENAMD_PAYLOAD_NAME_CKSYND,
20c794b39650d115e17a15983b6b82e46238cf45gavinm DATA_TYPE_UINT16, (uint16_t)AMD_NB_STAT_CKSYND(status),
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (members & FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYNDTYPE) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (members & FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCE &&
20c794b39650d115e17a15983b6b82e46238cf45gavinm authamd_ereport_add_resource(hdl, authamd, ereport, nva,
20c794b39650d115e17a15983b6b82e46238cf45gavinm * cms_msrinject entry point
20c794b39650d115e17a15983b6b82e46238cf45gavinmauthamd_msrinject(cmi_hdl_t hdl, uint_t msr, uint64_t val)
20c794b39650d115e17a15983b6b82e46238cf45gavinm authamd_ereport_add_logout, /* cms_ereport_add_logout */
20c794b39650d115e17a15983b6b82e46238cf45gavinm "Generic AMD model-specific MCA"