ao_mca.c revision 7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fe
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/privregs.h>
#include <sys/pci_impl.h>
#include <sys/x86_archext.h>
#include <sys/sysmacros.h>
#include <sys/cpu_module_impl.h>
#include <sys/pci_cfgspace_impl.h>
#include <sys/sysevent.h>
#include "ao.h"
#include "ao_mca_disp.h"
};
typedef struct ao_bank_cfg {
static const ao_bank_cfg_t ao_bank_cfgs[] = {
};
static const ao_error_disp_t ao_disp_unknown = {
};
/*
* This is quite awful but necessary to work around x86 system vendor's view of
* the world. Other operating systems (you know who you are) don't understand
* Opteron-specific error handling, so BIOS and system vendors often hide these
* conditions from them by using SMI polling to copy out any errors from the
* machine-check registers. When Solaris runs on a system with this feature,
* we want to disable the SMI polling so we can use FMA instead. Sadly, there
* isn't even a standard self-describing way to express the whole situation,
* so we have to resort to hard-coded values. This should all be changed to
* be a self-describing vendor-specific SMBIOS structure in the future.
*/
static const struct ao_smi_disable {
const char *asd_sys_vendor; /* SMB_TYPE_SYSTEM vendor prefix */
const char *asd_bios_vendor; /* SMB_TYPE_BIOS vendor prefix */
} ao_smi_disable[] = {
{ "Sun Microsystems", "American Megatrends", 0x502F, 0x59 },
};
static int
{
AO_MCA_R4_BIT_GEN, /* AMD_ERRCODE_R4_GEN */
AO_MCA_R4_BIT_RD, /* AMD_ERRCODE_R4_RD */
AO_MCA_R4_BIT_WR, /* AMD_ERRCODE_R4_WR */
AO_MCA_R4_BIT_DRD, /* AMD_ERRCODE_R4_DRD */
AO_MCA_R4_BIT_DWR, /* AMD_ERRCODE_R4_DWR */
AO_MCA_R4_BIT_IRD, /* AMD_ERRCODE_R4_IRD */
AO_MCA_R4_BIT_PREFETCH, /* AMD_ERRCODE_R4_PREFETCH */
AO_MCA_R4_BIT_EVICT, /* AMD_ERRCODE_R4_EVICT */
AO_MCA_R4_BIT_SNOOP /* AMD_ERRCODE_R4_SNOOP */
};
}
static int
{
AO_MCA_PP_BIT_SRC, /* AMD_ERRCODE_PP_SRC */
AO_MCA_PP_BIT_RSP, /* AMD_ERRCODE_PP_RSP */
AO_MCA_PP_BIT_OBS, /* AMD_ERRCODE_PP_OBS */
AO_MCA_PP_BIT_GEN /* AMD_ERRCODE_PP_GEN */
};
}
static int
{
AO_MCA_II_BIT_MEM, /* AMD_ERRCODE_II_MEM */
0,
AO_MCA_II_BIT_IO, /* AMD_ERRCODE_II_IO */
AO_MCA_II_BIT_GEN /* AMD_ERRCODE_II_GEN */
};
}
static uint8_t
{
return (val);
}
static int
{
/*
* If the bank's status register indicates overflow, then we can no
* longer rely on the value of CECC: our experience with actual fault
* injection has shown that multiple CE's overwriting each other shows
* AMD_BANK_STAT_CECC and AMD_BANK_STAT_UECC both set to zero. This
* should be clarified in a future BKDG or by the Revision Guide.
*/
if (status & AMD_BANK_STAT_OVER) {
}
return (0);
/*
* r4 and pp bits are stored separately, so we mask off and compare them
* for the code types that use them. Once we've taken the r4 and pp
* bits out of the equation, we can directly compare the resulting code
* with the one stored in the ao_error_disp_t.
*/
if (AMD_ERRCODE_ISMEM(code)) {
return (0);
} else if (AMD_ERRCODE_ISBUS(code)) {
return (0);
}
}
static const ao_error_disp_t *
{
const ao_error_disp_t *aed;
return (aed);
}
return (&ao_disp_unknown);
}
void
{
}
{
}
/*
* Setup individual bank detectors after stashing their bios settings.
*/
static void
{
int i;
for (i = 0; i < AMD_MCA_BANK_COUNT; i++, bankcfg++) {
}
}
/*
* Bits to be added to the NorthBridge (NB) configuration register.
* See BKDG 3.29 Section 3.6.4.2 for more information.
*/
/*
* Bits to be cleared from the NorthBridge (NB) configuration register.
* See BKDG 3.29 Section 3.6.4.2 for more information.
*/
/*
* Bits to be used if we configure the NorthBridge (NB) Watchdog. The watchdog
* triggers a machine check exception when no response to an NB system access
* occurs within a specified time interval. If the BIOS (i.e. platform design)
* has enabled the watchdog, we leave its rate alone. If the BIOS has not
* enabled the watchdog, we enable it and set the rate to one specified below.
* To disable the watchdog, add the AMD_NB_CFG_WDOGTMRDIS bit to ao_nb_cfg_add.
*/
static void
{
if (chip_plat_get_clogid(CPU) != 0)
return; /* only configure NB once per CPU */
/*
* Read the NorthBridge (NB) configuration register in PCI space,
* modify the settings accordingly, and store the new value back.
*/
/*
* If the watchdog was disabled, enable it according to the policy
* described above. Then apply the ao_nb_cfg_[add|remove] masks.
*/
if (val & AMD_NB_CFG_WDOGTMRDIS) {
val &= ~AMD_NB_CFG_WDOGTMRDIS;
val |= ao_nb_cfg_wdog;
}
val &= ~ao_nb_cfg_remove;
val |= ao_nb_cfg_add;
}
/*
* Capture the machine-check exception state into our per-CPU logout area, and
* dispatch a copy of the logout area to our error queue for ereport creation.
* If 'rp' is non-NULL, we're being called from trap context; otherwise we're
* being polled or poked by the injector. We return the number of errors
* found through 'np', and a boolean indicating whether the error is fatal.
* The caller is expected to call fm_panic() if we return fatal (non-zero).
*/
int
{
int i, fatal, n = 0;
/*
* Iterate over the banks of machine-check registers, read the address
* and status registers into the logout area, and clear them as we go.
*/
for (i = 0; i < AMD_MCA_BANK_COUNT; i++) {
}
if (ao_mca_stack_flag)
else
acl->acl_stackdepth = 0;
/*
* Clear MCG_STATUS, indicating that machine-check trap processing is
* complete. Once we do this, another machine-check trap can occur.
*/
wrmsr(IA32_MSR_MCG_STATUS, 0);
/*
* If we took a machine-check trap, then the error is fatal if the
* return instruction pointer is not valid in the global register.
*/
/*
* Now iterate over the saved logout area, determining whether the
* error that we saw is fatal or not based upon our dispositions
* and the hardware's indicators of whether or not we can resume.
*/
for (i = 0; i < AMD_MCA_BANK_COUNT; i++) {
const ao_error_disp_t *aed;
continue;
/*
* If we are taking a machine-check exception and the overflow
* bit is set or our context is corrupt, then we must die.
* NOTE: This code assumes that if the overflow bit is set and
* we didn't take a #mc exception (i.e. the poller found it),
* then multiple correctable errors overwrote each other.
* This will need to change if we eventually use the Opteron
* Rev E exception mechanism for detecting correctable errors.
*/
fatal = 1;
/*
* If we are taking a machine-check exception and we don't
* recognize the error case at all, then assume it's fatal.
* This will need to change if we eventually use the Opteron
* Rev E exception mechanism for detecting correctable errors.
*/
fatal = 1;
n++;
}
if (n > 0) {
}
*np = n; /* return number of errors found to caller */
return (fatal);
}
static uint_t
{
if (is_nb) {
AMD_NB_CFG_CHIPKILLECCEN) != 0) {
} else {
}
} else {
}
}
static void
{
unump->unum_offset);
}
static void
{
int nelems = 0;
int i;
for (i = 0; i < MC_UNUM_NDIMM; i++) {
break;
unump, i);
}
for (i = 0; i < nelems; i++)
}
static void
{
if (members & FM_EREPORT_PAYLOAD_FLAG_BANK_STAT) {
}
if (members & FM_EREPORT_PAYLOAD_FLAG_BANK_NUM) {
}
if (members & FM_EREPORT_PAYLOAD_FLAG_ADDR) {
}
}
if (members & FM_EREPORT_PAYLOAD_FLAG_SYND) {
}
if (members & FM_EREPORT_PAYLOAD_FLAG_SYND_TYPE) {
}
if (members & FM_EREPORT_PAYLOAD_FLAG_IP) {
}
if (members & FM_EREPORT_PAYLOAD_FLAG_PRIV) {
}
if (members & FM_EREPORT_PAYLOAD_FLAG_RESOURCE) {
int addrvalid;
}
}
}
static void
{
char buf[FM_MAX_CLASS];
if (panicstr) {
return;
} else {
}
/*
* Create the scheme "cpu" FMRI
*/
/*
* Encode all the common data into the ereport.
*/
/*
* Encode the error-specific data that was saved in the logout area.
*/
if (panicstr) {
} else {
}
}
/*ARGSUSED*/
void
{
int i;
for (i = 0; i < AMD_MCA_BANK_COUNT; i++) {
const ao_error_disp_t *aed;
}
}
}
int
{
}
/*ARGSUSED*/
int
{
int i;
for (i = 0; i < nregs; i++)
return (0);
}
void
ao_mca_init(void *data)
{
int i;
/*
* If the hardware's bank count is different than what we expect, then
* we're running on some Opteron variant that we don't understand yet.
*/
return;
}
/*
* Configure the logout areas. We preset every logout area's acl_ao
* pointer to refer back to our per-CPU state for errorq drain usage.
*/
for (i = 0; i < AO_MCA_LOGOUT_NUM; i++)
/*
* Throw away all existing bank state. We do this because some BIOSes,
* perhaps during POST, do things to the machine that cause MCA state
* to be updated. If we interpret this state as an actual error, we
* may end up indicting something that's not actually broken.
*/
for (i = 0; i < sizeof (ao_bank_cfgs) / sizeof (ao_bank_cfg_t); i++)
}
/*ARGSUSED*/
void
ao_mca_post_init(void *data)
{
const struct ao_smi_disable *asd;
/*
* Fetch the System and BIOS vendor strings from SMBIOS and see if they
* match a value in our table. If so, disable SMI error polling. This
* is grotesque and should be replaced by self-describing vendor-
* specific SMBIOS data or a specification enhancement instead.
*/
continue;
"Solaris Fault Management for AMD Processors");
break;
}
}
}
/*
* Called after a CPU has been marked with CPU_FAULTED. Not called on the
* faulted CPU. cpu_lock is held.
*/
/*ARGSUSED*/
void
ao_faulted_enter(void *data)
{
/*
* Nothing to do here. We'd like to turn off the faulted CPU's
* correctable error detectors, but that can only be done by the
* faulted CPU itself. cpu_get_state() will now return P_FAULTED,
* allowing the poller to skip this CPU until it is re-enabled.
*/
}
/*
* Called after the CPU_FAULTED bit has been cleared from a previously-faulted
* CPU. Not called on the faulted CPU. cpu_lock is held.
*/
void
ao_faulted_exit(void *data)
{
/*
* We'd like to clear the faulted CPU's MCi_STATUS registers so as to
* avoid generating ereports for errors which occurred while the CPU was
* officially faulted. Unfortunately, those registers can only be
* cleared by the CPU itself, so we can't do it here.
*
* We're going to set the UNFAULTING bit on the formerly-faulted CPU's
* MCA state. This will tell the poller that the MCi_STATUS registers
* can't yet be trusted. The poller, which is the first thing we
* control that'll execute on that CPU, will clear the registers, and
* will then clear the bit.
*/
}